JP2014239578A - Switching power supply device - Google Patents

Switching power supply device Download PDF

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JP2014239578A
JP2014239578A JP2013119969A JP2013119969A JP2014239578A JP 2014239578 A JP2014239578 A JP 2014239578A JP 2013119969 A JP2013119969 A JP 2013119969A JP 2013119969 A JP2013119969 A JP 2013119969A JP 2014239578 A JP2014239578 A JP 2014239578A
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JP6150425B2 (en
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誠 濱口
Makoto Hamaguchi
誠 濱口
翔太 今村
Shota Imamura
翔太 今村
和志 高見
Kazuyuki Takami
和志 高見
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Cosel Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To detect output detection voltages, corresponding to respective regions, appropriately without being interdependent, by differentiating the detection characteristics of the output detection voltage, detected by dividing it with a resistance voltage-dividing circuit, in a rated operation region and a protective operation region lower than that.SOLUTION: An output detection voltage Vs is outputted by dividing the output voltage from a step-up chopper circuit 10 by means of a resistance voltage-dividing circuit, and a control IC 30 is provided with a normal voltage detecting section 36 and a start voltage detecting section 38. A control section 32 starts switching operation of a FET 20 when a start signal is obtained, and operates the FET 20 in a rated operation range if a normal voltage detection signal has been obtained after start. A correction circuit 40 feeds a bias current to a resistor 28 of the resistance voltage-dividing circuit by conducting a diode 44 connected with a voltage source 42, and generates a bias voltage, and then raises the output detection voltage of the resistance voltage-dividing circuit by the bias voltage, thus obtaining the characteristics different from the output voltage detection characteristics determined by the resistance ratio of the resistance voltage-dividing circuit.

Description

本発明は、昇圧チョッパ回路を備えたスイッチング電源装置に関する。
The present invention relates to a switching power supply device including a boost chopper circuit.

従来、この種のスイッチング電源としては、例えば図９に示すものがある。図９に示すように、スイッチング電源装置は、交流電源１４を全波整流する全波整流回路１６に続いて力率を改善すると共に出力電圧を昇圧する昇圧チョッパ回路１０を設け、続いて昇圧チョッパ回路１０の出力電圧を安定化して負荷に供給するＤＣ−ＤＣコンバータ１２を設けている。   Conventionally, an example of this type of switching power supply is shown in FIG. As shown in FIG. 9, the switching power supply device is provided with a boost chopper circuit 10 that improves the power factor and boosts the output voltage following the full-wave rectifier circuit 16 that performs full-wave rectification of the AC power supply 14, and then boosts the chopper. A DC-DC converter 12 that stabilizes the output voltage of the circuit 10 and supplies it to a load is provided.

昇圧チョッパ回路１０は、チョークコイル１８、スイッチング素子として機能するＦＥＴ２０、整流用ダイオード２２、コンデンサ２４で構成され、制御ＩＣ３０により、入力する全波整流した電圧波形のエンベロープに合せてスイッチング電流のピークを制御するようにＦＥＴ２０をスイッチング制御することで、スイッチング電流の平均電流を入力電圧の正弦波形に近い波形として力率を改善し、また入力電圧を昇圧して安定化した直流電圧を出力している。   The step-up chopper circuit 10 includes a choke coil 18, an FET 20 that functions as a switching element, a rectifying diode 22, and a capacitor 24, and the control IC 30 sets a switching current peak in accordance with the envelope of the full-wave rectified voltage waveform that is input. By controlling the switching of the FET 20 so as to control, the power factor is improved by setting the average current of the switching current to a waveform close to the sine waveform of the input voltage, and the input voltage is boosted to output a stabilized DC voltage. .

制御ＩＣ３０は、制御部３２、入力電圧検出部３４、正常電圧検出部３６及び起動電圧検出部３８を備え、入力電圧検出端子ＩＮ１に全波整流回路１６からの全波整流電圧Ｖｉを入力し、出力電圧検出端子ＩＮ２に、抵抗２６，２８の抵抗分圧回路で検出した昇圧チョッパ回路１０の出力電圧Ｖｏを分圧した出力検出電圧Ｖｓを入力している。
The control IC 30 includes a control unit 32, an input voltage detection unit 34, a normal voltage detection unit 36, and a startup voltage detection unit 38, and inputs the full-wave rectified voltage Vi from the full-wave rectifier circuit 16 to the input voltage detection terminal IN1, An output detection voltage Vs obtained by dividing the output voltage Vo of the step-up chopper circuit 10 detected by the resistance voltage dividing circuit of the resistors 26 and 28 is input to the output voltage detection terminal IN2.

特開平２０１１−２２９２３３号公報JP 2011-229233 A 特開平２０１１−２２３８１９号公報Japanese Patent Application Laid-Open No. 2011-223819

図１０は昇圧チョッパ回路１０の出力電圧Ｖｏとこれを分圧した出力検出電圧Ｖｓについて、所定の定格出力電圧範囲（ＤＣ−ＤＣコンバータ１２の定格入力電圧範囲）を決める定格動作領域Ａと、動作を停止して保護する保護動作領域Ｂを示したグラフ図である。   FIG. 10 shows a rated operation region A for determining a predetermined rated output voltage range (rated input voltage range of the DC-DC converter 12) for the output voltage Vo of the boost chopper circuit 10 and the output detection voltage Vs obtained by dividing the output voltage Vo, and the operation. It is the graph which showed the protection operation area | region B which stops and protects.

定格動作領域Ａと保護動作領域Ｂは、制御ＩＣ３０に設けた正常電圧検出部３６と起動電圧検出部３８における閾値の設定で決めている。   The rated operation area A and the protection operation area B are determined by setting thresholds in the normal voltage detection unit 36 and the startup voltage detection unit 38 provided in the control IC 30.

保護動作領域Ｂは出力検出電圧Ｖｓが起動閾値電圧Ｖｔｈ１以下の範囲であり、例えばスイッチング電源装置を起動した直後は、出力検出電圧Ｖｓが起動閾値電圧Ｖｔｈ１以下にあることから、これを検出して起動電圧検出部３８は起動信号をオフしており、制御部３２によりＦＥＴ２０のスイッチング動作を停止している。   The protection operation region B is a range in which the output detection voltage Vs is less than or equal to the start threshold voltage Vth1, for example, immediately after starting the switching power supply device, the output detection voltage Vs is less than or equal to the start threshold voltage Vth1, The starting voltage detection unit 38 turns off the starting signal, and the control unit 32 stops the switching operation of the FET 20.

起動後の時間の経過に伴い出力検出電圧Ｖｓが上昇し、起動閾値電圧Ｖｔｈ１を超えると起動電圧検出部３８が起動信号をオンし、制御部３２が動作してＦＥＴ２０のスイッチング制御を開始し、ＦＥＴ２０のオンにより流れる電流でチョークコイル１８にエネルギーを蓄積し、続いてＦＥＴ２０のオフによりチョークコイル１８に蓄積したエネルギーを放出して整流ダイオード２２を介してコンデンサ２４を充電する動作を繰り返し、これに伴い出力電圧検出電圧Ｖｓが上昇し、下限閾値電圧Ｖｔｈ２と上限閾値電圧Ｖｔｈ３で決まる定格出力範囲となる定格動作領域Ａに入ると、出力電圧を入力電圧に対し昇圧した所定電圧に維持するように安定化させるＦＥＴ２０のスイッチング制御を行う。   The output detection voltage Vs increases with the lapse of time after startup, and when the startup threshold voltage Vth1 is exceeded, the startup voltage detection unit 38 turns on the startup signal, the control unit 32 operates to start switching control of the FET 20, Energy is accumulated in the choke coil 18 by the current that flows when the FET 20 is turned on, and then the operation of discharging the energy accumulated in the choke coil 18 by turning off the FET 20 and charging the capacitor 24 via the rectifier diode 22 is repeated. Accordingly, when the output voltage detection voltage Vs rises and enters the rated operation region A that is a rated output range determined by the lower limit threshold voltage Vth2 and the upper limit threshold voltage Vth3, the output voltage is maintained at a predetermined voltage boosted with respect to the input voltage. Switching control of the FET 20 to be stabilized is performed.

このように昇圧チョッパ回路１０にあっては、起動電圧検出部３８の保護動作領域Ｂの動作点を決める起動閾値電圧Ｖｔｈ１と、定格動作領域Ａを決める下限閾値電圧Ｖｔｈ２及び上限閾値電圧Ｖｔｈ３を個別に設定しているが、制御ＩＣ３０には出力電圧検出端子ＩＮ２が１つしか設けられていないため、起動電圧検出部３８と出力電圧検出部３６に対し、個別に抵抗分圧回路を設けることができず、そのため、抵抗２６，２８を直列接続した単一の抵抗分圧回路で検出した出力検出電圧Ｖｓを、起動電圧検出部３８と出力電圧検出部３６に共通に入力するようにしている。   As described above, in the step-up chopper circuit 10, the starting threshold voltage Vth1 that determines the operating point of the protection operation region B of the starting voltage detector 38, the lower threshold voltage Vth2 and the upper threshold voltage Vth3 that determine the rated operating region A are individually set. However, since the control IC 30 is provided with only one output voltage detection terminal IN2, a resistance voltage dividing circuit may be provided separately for the start-up voltage detection unit 38 and the output voltage detection unit 36. For this reason, the output detection voltage Vs detected by the single resistance voltage dividing circuit in which the resistors 26 and 28 are connected in series is input to the start-up voltage detection unit 38 and the output voltage detection unit 36 in common.

このため出力電圧Ｖｏから抵抗分圧回路により検出する出力検出電圧Ｖｓは、抵抗２６の抵抗値をＲ２６、抵抗２８の抵抗値をＲ２８とすると、
Ｖｓ＝Ｖｏ×Ｒ２８／（Ｒ２６＋Ｒ２８）
として決まる。 Therefore, the output detection voltage Vs detected from the output voltage Vo by the resistance voltage dividing circuit is R26 as the resistance value of the resistor 26 and R28 as the resistance value of the resistor 28.
Vs = Vo × R28 / (R26 + R28)
Determined as

この場合の分圧比率Ｋ＝Ｒ２８／（Ｒ２６＋Ｒ２８）を、例えば定格動作領域Ａの下限閾値電圧Ｖｔｈ２及び上限閾値電圧Ｖｔｈ３が、定格出力範囲を与える出力電圧の下限電圧（Ｖｏ）２と上限電圧（Ｖｏ）３から得られるように決定した場合、特性直線１００に示すように、保護動作領域Ｂの起動閾値電圧Ｖｔｈ１を与える起動出力電圧（Ｖｏ）１は一義的に決まる。   In this case, the voltage dividing ratio K = R28 / (R26 + R28) is set such that, for example, the lower limit threshold voltage Vth2 and the upper limit threshold voltage Vth3 of the rated operation region A are the lower limit voltage (Vo) 2 and the upper limit voltage (Vo2) of the output voltage giving the rated output range. Vo) 3 is determined to be obtained from the characteristic line 100, the starting output voltage (Vo) 1 that gives the starting threshold voltage Vth1 of the protection operation region B is uniquely determined.

しかし、定格動作領域Ａの動作点に依存して決まった保護動作領域Ｂの動作点を決める起動出力電圧（Ｖｏ）１は、保護動作領域Ｂの本来の動作点を与える起動出力電圧がそれより低い起動出力電圧（Ｖｏ）１‘であったとすると、これに対し高めに設定されることになる。   However, the startup output voltage (Vo) 1 that determines the operating point of the protected operating area B determined depending on the operating point of the rated operating area A is higher than the starting output voltage that gives the original operating point of the protected operating area B. If the start output voltage (Vo) 1 ′ is low, it is set higher than this.

このためスイッチング電源装置を起動した場合に、昇圧チョッパ回路１０が動作を開始するまでの遅れ時間が長くなる。また、起動出力電圧（Ｖｏ）１を高めに設定しているため、昇圧チョッパ回路１０の出力電圧Ｖｏが、定格動作領域Ａの下限閾値電圧Ｖｔｈ２に対応した出力電圧（Ｖｏ）２を下回った場合、本来の停止保護を必要とする起動出力電圧（Ｖｏ）１‘に下がる前に、起動出力電圧（Ｖｏ）１以下となって動作を停止し、これにより後段のＤＣ−ＤＣコンバータ１２の入力電圧が低下し、安定した動作が損なわれる。   For this reason, when the switching power supply device is activated, the delay time until the boost chopper circuit 10 starts operating becomes longer. In addition, since the startup output voltage (Vo) 1 is set higher, the output voltage Vo of the step-up chopper circuit 10 is lower than the output voltage (Vo) 2 corresponding to the lower limit threshold voltage Vth2 of the rated operation region A. Before the start-up output voltage (Vo) 1 ′, which originally requires stop protection, drops below the start-up output voltage (Vo) 1, the operation is stopped, whereby the input voltage of the subsequent DC-DC converter 12 is stopped. And the stable operation is impaired.

この昇圧チョッパ回路１０の動作開始の遅れ時間を解消するためには、保護動作領域Ｂの起動閾値電圧Ｖｔｈ１に、本来の起動出力電圧（Ｖｏ）１‘に合せるように抵抗分圧回路の分圧比率Ｋを設定し、点線で示す直線特性１０２とすればよいが、この場合には、定格動作領域Ａの動作点を決める定格出力電圧の範囲が低い側に大きくシフトし、昇圧チョッパ回路１０の本来の動作が損なわれてしまう。   In order to eliminate the delay time of the operation start of the step-up chopper circuit 10, the voltage dividing circuit of the resistance voltage dividing circuit is adjusted so as to match the starting threshold voltage Vth1 of the protection operation region B with the original starting output voltage (Vo) 1 ′. The ratio K may be set and the linear characteristic 102 indicated by the dotted line may be set. In this case, the range of the rated output voltage that determines the operating point of the rated operating region A is greatly shifted to the lower side, and the boost chopper circuit 10 The original operation is impaired.

本発明は、抵抗分圧回路で分圧して検出した昇圧チョッパ回路の出力検出電圧を、定格動作領域とそれより低い保護動作領域で異なる検出特性とし、各領域の動作点に対応する出力検出電圧を相互に依存することなく適切に検出可能とするスイッチング電源装置を提供することを目的とする。
In the present invention, the output detection voltage of the boost chopper circuit detected by dividing by the resistance voltage dividing circuit has different detection characteristics in the rated operation region and the lower protection operation region, and the output detection voltage corresponding to the operation point in each region It is an object of the present invention to provide a switching power supply device that can appropriately detect the power supply without depending on each other.

（スイッチング電源装置）
本発明は、
スイッチング動作により力率を改善すると共に入力電圧を昇圧して所定の出力電圧に安定化する昇圧チョッパ回路と、
昇圧チョッパ回路の出力電圧を、直列接続した少なくとも２つの抵抗で分圧して出力検出電圧を出力する抵抗分圧回路と、
抵抗分圧回路の出力検出電圧が所定の定格動作領域にあることを検出して正常電圧検出信号を出力する正常電圧検出部と、
抵抗分圧回路の出力検出電圧が定格動作領域の下限より低い所定の起動閾値電圧未満の場合に起動信号の出力を停止し、起動閾値電圧に達した場合に起動信号を出力する起動電圧検出部と、
起動電圧検出部から起動信号が得られた場合に昇圧チョッパ回路のスイッチング動作を開始して起動し、当該起動後に、正常電圧検出部から正常電圧検出信号が得られている場合に昇圧チョッパ回路を定格動作領域で動作させる制御部と、
を備えたスイッチング電源装置に於いて、
抵抗分圧回路の出力検出電圧が定格動作領域の下限より低く且つ起動閾値電圧より高い所定の補正上限電圧以下の場合に、抵抗分圧回路にバイアス電流を流して所定のバイアス電圧を発生し、抵抗分圧回路の出力検出電圧をバイアス電圧により引き上げる補正回路を設けたことを特徴とする。 (Switching power supply)
The present invention
A step-up chopper circuit that improves the power factor by switching operation and boosts the input voltage to stabilize it to a predetermined output voltage;
A resistance voltage dividing circuit for dividing the output voltage of the boost chopper circuit by at least two resistors connected in series and outputting an output detection voltage;
A normal voltage detection unit that detects that the output detection voltage of the resistance voltage divider circuit is in a predetermined rated operation region and outputs a normal voltage detection signal;
A start-up voltage detector that stops the output of the start signal when the output detection voltage of the resistance voltage divider circuit is lower than a predetermined start threshold voltage lower than the lower limit of the rated operation region, and outputs a start signal when the start threshold voltage is reached When,
When the activation signal is obtained from the activation voltage detector, the switching operation of the boost chopper circuit is started and activated, and when the normal voltage detection signal is obtained from the normal voltage detector after the activation, the boost chopper circuit is activated. A controller that operates in the rated operating range;
In a switching power supply device with
When the output detection voltage of the resistance voltage dividing circuit is lower than a predetermined correction upper limit voltage lower than the lower limit of the rated operation region and higher than the start threshold voltage, a bias current is passed through the resistance voltage dividing circuit to generate a predetermined bias voltage, A correction circuit is provided for raising the output detection voltage of the resistance voltage dividing circuit by a bias voltage.

（補正回路の詳細）
補正回路は、
所定の補正上限電圧を出力する電圧源と、
電圧源と抵抗分圧回路の分圧点との間に接続したダイオードと、
を備え、
電圧源は、補正上限電圧をダイオードに印加し、抵抗分圧回路の出力検出電圧が補正上限電圧以下の場合にダイオードを導通して抵抗分圧回路にバイアス電流を流し、抵抗分圧回路の出力検出電圧が補正上限電圧を超えた場合にダイオードを非導通として抵抗分圧回路に流すバイアス電流を停止する。 (Details of correction circuit)
The correction circuit
A voltage source that outputs a predetermined correction upper limit voltage;
A diode connected between the voltage source and the voltage dividing point of the resistance voltage dividing circuit;
With
The voltage source applies the correction upper limit voltage to the diode, and when the output detection voltage of the resistance voltage divider circuit is less than or equal to the correction upper limit voltage, the diode is turned on to pass a bias current to the resistance voltage divider circuit, and the output of the resistance voltage divider circuit When the detection voltage exceeds the correction upper limit voltage, the diode is made non-conductive and the bias current flowing through the resistance voltage dividing circuit is stopped.

（補正回路詳細）
補正回路のダイオードに代えて、トランジスタ又はＦＥＴを用いる。 (Details of correction circuit)
A transistor or FET is used instead of the diode of the correction circuit.

（全波整流とＤＣ−ＤＣコンバータ）
昇圧チョッパ回路の入力側に、交流電圧を入力して全波整流電圧を出力する全波整流回路を設け、昇圧チョッパ回路の出力側に、ＤＣ-ＤＣコンバータを設ける。 (Full-wave rectification and DC-DC converter)
A full-wave rectifier circuit that inputs an AC voltage and outputs a full-wave rectified voltage is provided on the input side of the boost chopper circuit, and a DC-DC converter is provided on the output side of the boost chopper circuit.

（制御ＩＣ）
正常電圧検出部と起動電圧検出部は、昇圧チョッパ回路の制御部として機能する制御ＩＣに内蔵され、
制御ＩＣは単一の出力電圧検出端子を備え、当該出力電圧検出端子に抵抗分圧回路の分圧点を接続して出力検出電圧を入力し、
制御ＩＣに内蔵した出力電圧検出部と起動電圧検出部は、出力検出端子を共通に入力接続する。
(Control IC)
The normal voltage detection unit and the startup voltage detection unit are incorporated in a control IC that functions as a control unit of the boost chopper circuit.
The control IC has a single output voltage detection terminal, connects the voltage dividing point of the resistance voltage dividing circuit to the output voltage detection terminal, and inputs the output detection voltage.
The output voltage detection unit and the start-up voltage detection unit built in the control IC are connected to the output detection terminal in common.

本発明のスイッチング電源装置によれば、昇圧チョッパ回路に設けた抵抗分圧回路の出力検出電圧が定格動作電圧領域の下限より低く且つ起動閾値電圧より高い所定の補正上限電圧以下の場合に、補正回路の電圧源からダイオードを介して抵抗分圧回路にバイアス電流を流して所定のバイアス電圧を発生し、抵抗分圧回路の出力検出電圧をバイアス電圧により引き上げるようにしたため、起動閾値電圧に対応した出力検出電圧を、抵抗分圧回路の抵抗分圧比で決まる電圧より低い電圧に設定することができ、スイッチング電源装置を起動した場合に、昇圧チョッパ回路のスイッチング動作を開始するまでの時間を短くすることができる。   According to the switching power supply device of the present invention, when the output detection voltage of the resistance voltage dividing circuit provided in the boost chopper circuit is lower than the lower limit of the rated operating voltage region and higher than the start threshold voltage, the correction is performed. A bias current is supplied from the voltage source of the circuit to the resistance voltage dividing circuit through the diode to generate a predetermined bias voltage, and the output detection voltage of the resistance voltage dividing circuit is raised by the bias voltage, so that it corresponds to the start threshold voltage. The output detection voltage can be set to a voltage lower than the voltage determined by the resistance voltage dividing ratio of the resistance voltage dividing circuit, and when the switching power supply device is started, the time until the switching operation of the boost chopper circuit is started is shortened. be able to.

また、昇圧チョッパ回路が起動してスイッチング動作により出力電圧が上昇し、抵抗分圧回路による出力検出電圧が補正回路に設けて電圧源からの補正上限電圧を超えると、ダイオードが自動的にオフして抵抗分圧回路に流すバイアス電流を停止し、これにより抵抗分圧回路の分圧比率に基づく出力電圧の検出特性に戻り、定格動作領域における昇圧チョッパ回路の定格動作を適正に行うことができる。   Also, when the boost chopper circuit is activated and the output voltage rises due to the switching operation, and the output detection voltage by the resistance voltage divider circuit is provided in the correction circuit and exceeds the correction upper limit voltage from the voltage source, the diode is automatically turned off. This stops the bias current flowing through the resistor voltage divider circuit, thereby returning to the output voltage detection characteristic based on the voltage dividing ratio of the resistor voltage divider circuit, and properly performing the rated operation of the boost chopper circuit in the rated operation region. .

また、昇圧チョッパ回路の出力電圧の定格動作領域を外れる低下変動に対し、抵抗分圧回路のバイアスにより起動閾値電圧に対応した出力電圧を低めに設定しているため、出力電圧の低下変動に対し本来の保護動作領域に入らない限り昇圧チョッパ回路の動作を停止することはなく、定格動作範囲を超えて出力電圧に低下変動しても、後段のＤＣ−ＤＣコンバータを安定して動作させることができる。   In addition, the output voltage corresponding to the start threshold voltage is set to a lower value by the bias of the resistance voltage divider circuit against the fluctuation that falls outside the rated operating range of the output voltage of the boost chopper circuit. The step-up chopper circuit operation is not stopped unless it enters the original protection operation region, and the subsequent DC-DC converter can be stably operated even if the output voltage exceeds the rated operation range and fluctuates. it can.

また、抵抗分圧回路をバイアスする補正回路は、電圧源とダイオードで構成する簡単な回路で済み、少ない部品点数で安価に構成することを可能とする。
Further, the correction circuit for biasing the resistance voltage dividing circuit may be a simple circuit composed of a voltage source and a diode, and can be configured inexpensively with a small number of parts.

本発明によるスイッチング電源装置の実施形態を示した回路ブロック図The circuit block diagram which showed embodiment of the switching power supply device by this invention 図１の実施形態による出力電圧検出特性とバイアス特性を示したグラフ図The graph which showed the output voltage detection characteristic and bias characteristic by embodiment of FIG. 補正回路のダイオードに抵抗を接続した他の実施形態を示した回路ブロック図Circuit block diagram showing another embodiment in which a resistor is connected to the diode of the correction circuit 抵抗分圧回路に分圧抵抗を追加した他の実施形態を示した回路ブロック図Circuit block diagram showing another embodiment in which a voltage dividing resistor is added to the resistor voltage dividing circuit 補正回路にＮＰＮトランジスタを用いた他の実施形態を示した回路ブロック図Circuit block diagram showing another embodiment using an NPN transistor in the correction circuit 補正回路にＰＮＰトランジスタを用いた他の実施形態を示した回路ブロック図Circuit block diagram showing another embodiment using a PNP transistor in the correction circuit 補正回路にＮチャンネルＦＥＴを用いた他の実施形態を示した回路ブロック図Circuit block diagram showing another embodiment using an N-channel FET as a correction circuit 補正回路にＰチャンネルＦＥＴを用いた他の実施形態を示した回路ブロック図Circuit block diagram showing another embodiment using a P-channel FET as a correction circuit 従来のスイッチング電源装置を示した回路ブロック図Circuit block diagram showing a conventional switching power supply 従来の出力電圧検出特性を示したグラフ図Graph showing conventional output voltage detection characteristics

［スイッチング電源装置の構成］
図１は、本発明によるスイッチング電源装置の実施形態を示した回路ブロック図である。 [Configuration of switching power supply unit]
FIG. 1 is a circuit block diagram showing an embodiment of a switching power supply device according to the present invention.

図１に示すように、本実施形態のスイッチング電源装置は、昇圧チョッパ回路１０とＤＣ−ＤＣコンバータ１２で構成する。ＤＣ−ＤＣコンバータ１２は、フライバック方式又はフォワード方式の絶縁型コンバータなどであり、適宜の負荷を接続する。   As shown in FIG. 1, the switching power supply device according to the present embodiment includes a boost chopper circuit 10 and a DC-DC converter 12. The DC-DC converter 12 is a flyback-type or forward-type isolated converter or the like, and is connected to an appropriate load.

（昇圧チョッパ回路の概略）
昇圧チョッパ回路１０は、交流電源１４からの交流電圧を全波整流する全波整流回路１６からの全波整流出力を入力し、チョークコイル１８、スイッチング素子として機能するＦＥＴ２０、整流用ダイオード２２、コンデンサ２４、抵抗２６，２８を備えた抵抗分圧回路、及び制御ＩＣ３０で構成する。 (Outline of boost chopper circuit)
The step-up chopper circuit 10 receives a full-wave rectified output from a full-wave rectifier circuit 16 that full-wave rectifies an AC voltage from an AC power supply 14, and inputs a choke coil 18, an FET 20 that functions as a switching element, a rectifier diode 22, and a capacitor. 24, a resistance voltage dividing circuit having resistors 26 and 28, and a control IC 30.

制御ＩＣ３０は、制御部３２、入力電圧検出部３４、正常電圧検出部３６及び起動電圧検出部３８を備え、入力電圧検出端子ＩＮ１に全波整流回路１６からの全波整流電圧Ｖｉを入力し、出力電圧検出端子ＩＮ２に、抵抗２６，２８の抵抗分圧回路で検出した昇圧チョッパ回路１０の出力電圧Ｖｏを分圧した出力検出電圧Ｖｓを入力している。   The control IC 30 includes a control unit 32, an input voltage detection unit 34, a normal voltage detection unit 36, and a startup voltage detection unit 38, and inputs the full-wave rectified voltage Vi from the full-wave rectifier circuit 16 to the input voltage detection terminal IN1, An output detection voltage Vs obtained by dividing the output voltage Vo of the step-up chopper circuit 10 detected by the resistance voltage dividing circuit of the resistors 26 and 28 is input to the output voltage detection terminal IN2.

制御ＩＣ３０は、入力する全波整流した電圧波形のエンベロープに合せてスイッチング電流のピークを制御するようにＦＥＴ２０をスイッチング制御することで、スイッチング電流の平均電流を入力電圧の正弦波形に近い波形として力率を改善し、また入力電圧を昇圧して安定化した直流電圧をＤＣ−ＤＣコンバータ１２に出力する。   The control IC 30 performs switching control of the FET 20 so as to control the peak of the switching current in accordance with the envelope of the input full-wave rectified voltage waveform, thereby making the average current of the switching current as a waveform close to the sine waveform of the input voltage. The output voltage is improved and the input voltage is boosted and stabilized to output a stabilized DC voltage to the DC-DC converter 12.

即ち、昇圧チョッパ回路１０は、交流電源１４の投入により動作を開始すると、この段階では制御ＩＣ３０の制御部３２によるＦＥＴ２０のスイッチング動作は停止しており、全波整流回路１６の全波整流による電流がチョークコイル１８及び整流用ダイオード２２を介してコンデンサ２４の充電を開始する。このため起動後の時間の経過に伴って出力電圧Ｖｏが上昇し、抵抗分圧回路で検出した出力検出電圧Ｖｓが所定の起動閾値電圧を超えると起動電圧検出部３８が起動信号をオンし、制御部３２が動作してＦＥＴ２０のスイッチング制御を開始し、ＦＥＴ２０のオンにより流れる電流でチョークコイル１８にエネルギーを蓄積し、続いてＦＥＴ２０のオフによりチョークコイル１８に蓄積したエネルギーを放出して整流ダイオード２２を介してコンデンサ２４を充電する動作を繰り返す。これに伴い出力電圧Ｖｏが上昇し、その出力検出電圧Ｖｓが所定の定格出力電圧範囲となる定格動作領域に入ると、出力電圧を入力電圧に対し昇圧した所定電圧に維持するように安定化させるＦＥＴ２０のスイッチング制御を行う。   That is, when the boost chopper circuit 10 starts operating when the AC power supply 14 is turned on, the switching operation of the FET 20 by the control unit 32 of the control IC 30 is stopped at this stage, and the current generated by the full-wave rectification of the full-wave rectifier circuit 16 is stopped. Starts charging the capacitor 24 via the choke coil 18 and the rectifying diode 22. For this reason, the output voltage Vo increases with the lapse of time after startup, and when the output detection voltage Vs detected by the resistance voltage dividing circuit exceeds a predetermined startup threshold voltage, the startup voltage detection unit 38 turns on the startup signal, The control unit 32 operates to start the switching control of the FET 20, accumulates energy in the choke coil 18 with the current flowing when the FET 20 is turned on, and subsequently releases the energy accumulated in the choke coil 18 by turning off the FET 20. The operation of charging the capacitor 24 through 22 is repeated. Along with this, when the output voltage Vo rises and the output detection voltage Vs enters a rated operation region in which a predetermined rated output voltage range is reached, the output voltage is stabilized so as to be maintained at a predetermined voltage boosted with respect to the input voltage. Switching control of the FET 20 is performed.

これに加え本実施形態にあっては、抵抗２６，２８による抵抗分圧回路に対し、その検出特性を補正する補正回路４０を設けている。   In addition to this, in the present embodiment, a correction circuit 40 is provided for correcting the detection characteristics of the resistance voltage dividing circuit including the resistors 26 and 28.

補正回路４０は、電圧源４２とダイオード４４を備え、電圧源４２の出力を、ダイオード４４を介して抵抗分圧回路の抵抗２６と抵抗２８の間の分圧点に接続している。   The correction circuit 40 includes a voltage source 42 and a diode 44, and an output of the voltage source 42 is connected to a voltage dividing point between the resistor 26 and the resistor 28 of the resistor voltage dividing circuit via the diode 44.

電圧源４２は所定の補正上限電圧Ｖａをダイオード４４に印加し、抵抗２６，２８で出力電圧Ｖｏを分圧した出力検出電圧Ｖｓが電圧源４２から印加する補正上限電圧Ｖａ以下の場合、ダイオード４４を順方向バイアスして導通して、抵抗分圧回路の抵抗Ｒ２８にバイアス電流Ｉｂを流して所定のバイアス電圧Ｖｂを発生し、抵抗分圧回路の出力検出電圧Ｖｓをバイアス電圧Ｖｂにより引き上げ、
Ｖｓ＝Ｖｓ＋Ｖｂ
として制御ＩＣ３０の出力電圧検出端子ＩＮ２に加えるようにしている。 The voltage source 42 applies a predetermined correction upper limit voltage Va to the diode 44, and when the output detection voltage Vs obtained by dividing the output voltage Vo by the resistors 26 and 28 is equal to or lower than the correction upper limit voltage Va applied from the voltage source 42, the diode 44. Is forward-biased to be conducted, a bias current Ib is caused to flow through the resistor R28 of the resistance voltage dividing circuit to generate a predetermined bias voltage Vb, and the output detection voltage Vs of the resistance voltage dividing circuit is raised by the bias voltage Vb.
Vs = Vs + Vb
Is applied to the output voltage detection terminal IN2 of the control IC 30.

また、抵抗２６，２８で出力電圧Ｖｏを分圧した出力検出電圧Ｖｓが電圧源４２から印加する補正上限電圧Ｖａを上回った場合には、ダイオード４４を逆方向にバイアスして非導通とし、抵抗分圧回路の抵抗Ｒ２８に流しているバイアス電流Ｉｂを停止してバイアス電圧Ｖｂの発生を解除し、抵抗２６，２８の値により分圧した出力検出電圧Ｖｓを制御ＩＣ３０の出力電圧検出端子ＩＮ２に加えるようにしている。   When the output detection voltage Vs obtained by dividing the output voltage Vo by the resistors 26 and 28 exceeds the correction upper limit voltage Va applied from the voltage source 42, the diode 44 is biased in the reverse direction to be non-conductive, and the resistance The bias current Ib flowing through the resistor R28 of the voltage dividing circuit is stopped to cancel the generation of the bias voltage Vb, and the output detection voltage Vs divided by the values of the resistors 26 and 28 is applied to the output voltage detection terminal IN2 of the control IC 30. I try to add it.

（出力検出電圧のバイアス電圧による補正）
図２は、図１の実施形態による抵抗分圧回路の出力電圧検出特性と補正回路によりバイアスした出力電圧検出特性を示したグラフ図である。 (Correction of output detection voltage by bias voltage)
FIG. 2 is a graph showing the output voltage detection characteristic of the resistance voltage dividing circuit according to the embodiment of FIG. 1 and the output voltage detection characteristic biased by the correction circuit.

図２に示すように、直線特性１００は、図１９の従来回路の場合と同様、抵抗分圧回路の抵抗２６，２８の分圧で決まる出力電圧検出特性であり、抵抗２６の抵抗値をＲ２６、抵抗２８の抵抗値をＲ２８とすると、出力検出電圧Ｖｓは
Ｖｓ＝Ｖｏ×Ｒ２８／（Ｒ２６＋Ｒ２８） 式（１）
として求まる。 As shown in FIG. 2, the linear characteristic 100 is an output voltage detection characteristic determined by the voltage division of the resistors 26 and 28 of the resistance voltage dividing circuit, as in the case of the conventional circuit of FIG. 19, and the resistance value of the resistor 26 is set to R26. When the resistance value of the resistor 28 is R28, the output detection voltage Vs is Vs = Vo × R28 / (R26 + R28) Equation (1)
It is obtained as

ここで、昇圧チョッパ回路１０の定格動作領域Ａの下限電圧を（Ｖｏ）２、上限電圧を（Ｖｏ）３とすると、これに対応する抵抗分圧回路で検出した出力検出電圧Ｖｓは、直線特性１００に従って下限閾値電圧Ｖｔｈ２、上限閾値電圧Ｖｔｈ３となり、これを制御ＩＣ３０の正常電圧検出部３６に設定して定格動作領域Ａを検出し、出力電圧Ｖｏが（Ｖｏ）２〜（Ｖｏ）３の範囲となるように制御部３０によりＦＥＴ２０をスイッチング制御する定格動作を行わせる。   Here, when the lower limit voltage of the rated operation region A of the boost chopper circuit 10 is (Vo) 2 and the upper limit voltage is (Vo) 3, the output detection voltage Vs detected by the corresponding resistance voltage dividing circuit is linear characteristics. According to 100, the lower limit threshold voltage Vth2 and the upper limit threshold voltage Vth3 are set in the normal voltage detection unit 36 of the control IC 30 to detect the rated operation area A, and the output voltage Vo is in the range of (Vo) 2 to (Vo) 3. The control unit 30 performs a rated operation for switching control of the FET 20 so that

これに対し補正回路４０の電圧源４２は、ダイオード４４に対し、定格動作領域Ａの下限閾値電圧Ｖｔｈ２より低く、昇圧チョッパ回路１０のスイッチング動作を停止する保護動作範囲Ｂを決める所定の起動閾値電圧Ｖｔｈ１より高い範囲に設定した所定の補正上限電圧Ｖａを印加する。   On the other hand, the voltage source 42 of the correction circuit 40 is lower than the lower limit threshold voltage Vth2 of the rated operation region A with respect to the diode 44 and has a predetermined start threshold voltage that determines the protection operation range B in which the switching operation of the boost chopper circuit 10 is stopped. A predetermined correction upper limit voltage Va set in a range higher than Vth1 is applied.

ここで、保護動作範囲Ｂの動作点（起動開始点）Ｐを決める出力起動電圧を（Ｖｏ）１とすると、このときの抵抗分圧回路の直線特性１００（点線部分）により検出されるＱ点の出力検出電圧（Ｖｓ）１は、
（Ｖｓ）１＝（Ｖｏ）１×Ｒ２８／（Ｒ２６＋Ｒ２８） 式（２）
で与えられ、このＱ点を起動閾値電圧Ｖｔｈ１となるＰ点に引き上げるに必要なバイアス電圧Ｖｂは
Ｖｂ＝Ｖｔｈ１−（Ｖｓ）１ 式（３）
となる。 Here, if the output starting voltage that determines the operating point (starting start point) P of the protection operating range B is (Vo) 1, the Q point detected by the linear characteristic 100 (dotted line portion) of the resistance voltage dividing circuit at this time The output detection voltage (Vs) 1 of
(Vs) 1 = (Vo) 1 * R28 / (R26 + R28) Formula (2)
The bias voltage Vb required to raise the Q point to the P point that becomes the starting threshold voltage Vth1 is Vb = Vth1- (Vs) 1 (3)
It becomes.

そこで、昇圧チョッパ回路１０の出力電圧Ｖｏを零ボルトとした場合に、ダイオード４４を介して抵抗分圧回路の抵抗２８にバイアス電流Ｉｂを流し、抵抗２８の両端に発生する電圧が式（３）で与えられるバイアス電圧Ｖｂとなるように、バイアス電流Ｉｂを決めることで、
Ｖｂ＝Ｉｂ×Ｒ２８
を発生し、これよりＱ点を通る抵抗分圧回路による直線特性１００を、バイアス電圧Ｖｂだけ高い方にシフトしたＰ点を通る直線特性１０４に補正することができる。 Therefore, when the output voltage Vo of the step-up chopper circuit 10 is set to zero volts, the bias current Ib is passed through the resistor 28 of the resistance voltage dividing circuit via the diode 44, and the voltage generated at both ends of the resistor 28 is expressed by the equation (3). By determining the bias current Ib to be the bias voltage Vb given by
Vb = Ib × R28
Thus, the linear characteristic 100 by the resistance voltage dividing circuit passing through the Q point can be corrected to the linear characteristic 104 passing through the P point shifted higher by the bias voltage Vb.

バイアス電圧Ｖｂにより補正した直線特性１０４は、出力電圧Ｖｏの増加に伴い抵抗分圧回路による点線部分の直線特性１００で示すように出力検出電圧Ｖｓが増加すると、これにバイアス電圧Ｖｂを加算した電圧として増加する特性となる。   The linear characteristic 104 corrected by the bias voltage Vb is a voltage obtained by adding the bias voltage Vb to the output detection voltage Vs when the output detection voltage Vs increases as indicated by the linear characteristic 100 of the dotted line portion by the resistance voltage dividing circuit as the output voltage Vo increases. As the characteristic increases.

出力電圧Ｖｏの増加に伴い、抵抗分圧回路による直線特性１００の点線部分に従って増加する出力検出電圧Ｖｓが、電圧源４２から印加している補正上限電圧Ｖａからダイオード４４の順方向降下電圧を差し引いたＲ点の電圧に達すると、ダイオード４４の順方向降下電圧が減少を始めてバイアス電流が略直線的に減少し、このためＲ点の電圧にバイアス電圧Ｖｂを加算して得ている直線特性１０４に従った出力検出電圧ＶｓはＳ点から略一定となる。   As the output voltage Vo increases, the output detection voltage Vs that increases according to the dotted line portion of the linear characteristic 100 by the resistance voltage dividing circuit subtracts the forward drop voltage of the diode 44 from the correction upper limit voltage Va applied from the voltage source 42. When the voltage at the point R is reached, the forward drop voltage of the diode 44 starts to decrease and the bias current decreases approximately linearly. Therefore, the linear characteristic 104 obtained by adding the bias voltage Vb to the voltage at the point R is obtained. The output detection voltage Vs according to the above becomes substantially constant from the S point.

そして、抵抗分圧回路による直線特性１００の点線部分に従って増加する出力検出電圧Ｖｓが電圧源４２から印加している補正上限電圧Ｖａを上回るＴ点に達すると、ダイオード４４が逆バイアスを受けて非導通となり、抵抗２８に流れるバイアス電流が停止し、抵抗２６，２８により決まる直線特性１００に移行する。   When the output detection voltage Vs, which increases according to the dotted line portion of the linear characteristic 100 by the resistance voltage dividing circuit, reaches a point T exceeding the correction upper limit voltage Va applied from the voltage source 42, the diode 44 receives a reverse bias and is not turned on. Conduction is established, the bias current flowing through the resistor 28 is stopped, and the linear characteristic 100 determined by the resistors 26 and 28 is shifted to.

一方、昇圧チョッパ回路１０が定格動作領域Ａで動作中に、抵抗分圧回路の障害などにより出力電圧Ｖｏが大きく低下した場合には、出力電圧検出特性は、直線特性１００からＴ点、Ｓ点を通って直線特性１０４に移行し、Ｐ点で起動閾値電圧Ｖｔｈ１を下回った場合に、制御ＩＣ３０の起動電圧検出部３８からの起動信号がオフとなり、制御部３２がＦＥＴ２０のスイッチングを停止して保護動作を行う。   On the other hand, when the output voltage Vo is greatly reduced while the boost chopper circuit 10 is operating in the rated operation region A due to a failure of the resistance voltage dividing circuit, the output voltage detection characteristic is changed from the linear characteristic 100 to the T point and the S point. When the control signal shifts to the linear characteristic 104 and falls below the activation threshold voltage Vth1 at the point P, the activation signal from the activation voltage detection unit 38 of the control IC 30 is turned off, and the control unit 32 stops switching of the FET 20 Perform protective actions.

このように補正回路４０により補正した保護動作領域Ｂに対応した直線特性１０４は、出力電圧Ｖｏが保護動作領域Ｂを超えて定格動作領域Ａに入るまでの間に、自動的に、定格動作領域Ａに対応した直線特性１００に切り替わる出力電圧検出特性が得られる。   Thus, the linear characteristic 104 corresponding to the protection operation region B corrected by the correction circuit 40 is automatically applied to the rated operation region until the output voltage Vo exceeds the protection operation region B and enters the rated operation region A. An output voltage detection characteristic that switches to the linear characteristic 100 corresponding to A is obtained.

［補正回路の他の実施形態］
図３は補正回路のダイオードに抵抗を接続した他の実施形態を示した回路ブロック図であり、入力側の全波整流回路は省略している。 [Other Embodiments of Correction Circuit]
FIG. 3 is a circuit block diagram showing another embodiment in which a resistor is connected to a diode of the correction circuit, and a full-wave rectifier circuit on the input side is omitted.

図３に示すように、昇圧チョッパ回路１０は、チョークコイル１８、ＦＥＴ２０、整流用ダイオード２２、コンデンサ２４、抵抗２６，２８を備えた抵抗分圧回路、及び制御ＩＣ３０を備え、更に、抵抗分圧回路の抵抗２８をバイアスする補正回路４０を設けており、図１の実施形態と基本的に同じになることから、同一符号を付して説明を省略する。   As shown in FIG. 3, the step-up chopper circuit 10 includes a choke coil 18, an FET 20, a rectifying diode 22, a capacitor 24, a resistor voltage divider circuit having resistors 26 and 28, and a control IC 30, and further a resistor voltage divider. A correction circuit 40 for biasing the circuit resistor 28 is provided, which is basically the same as that of the embodiment of FIG.

本実施形態の補正回路４０は、ダイオード４４の前後に抵抗４５，４６を直列接続しており、電圧源４２を抵抗４５、ダイオード４４及び抵抗４６を介して抵抗分圧回路の抵抗２６，２８の分圧点に接続している。   In the correction circuit 40 of this embodiment, resistors 45 and 46 are connected in series before and after the diode 44, and the voltage source 42 is connected to the resistors 26 and 28 of the resistor voltage dividing circuit via the resistor 45, the diode 44 and the resistor 46. Connected to the voltage dividing point.

このようにダイオード４４の前後に必要に応じて抵抗４５，４６を接続することで、図２のバイアス電圧Ｖｂを設定するために抵抗２８に流すバイアス電流Ｉｂの設定調整や、定格動作領域Ａと保護動作領域Ｂとの間の直線特性１００と直線特性１０４の間の移行を行うＳ点及びＴ点を与える電圧源４２からの補正上限電圧Ｖａの分圧によるダイオード４４への印加などの設定調整を可能とする。   In this way, by connecting the resistors 45 and 46 as necessary before and after the diode 44, the setting adjustment of the bias current Ib flowing through the resistor 28 to set the bias voltage Vb of FIG. Setting adjustment such as application to the diode 44 by voltage division of the correction upper limit voltage Va from the voltage source 42 giving the S point and the T point for transition between the linear characteristic 100 and the linear characteristic 104 between the protection operation region B Is possible.

［抵抗分圧回路の他の実施形態］
図４は抵抗分圧回路に分圧抵抗を追加した他の実施形態を示した回路ブロック図であり、入力側の全波整流回路は省略している。 [Other Embodiments of Resistance Divider Circuit]
FIG. 4 is a circuit block diagram showing another embodiment in which a voltage dividing resistor is added to the resistor voltage dividing circuit, and a full-wave rectifier circuit on the input side is omitted.

図４に示すように、昇圧チョッパ回路１０は、チョークコイル１８、ＦＥＴ２０、整流用ダイオード２２、コンデンサ２４、抵抗２６，２８を備えた抵抗分圧回路、及び制御ＩＣ３０を備え、更に、抵抗分圧回路の抵抗２８をバイアスする補正回路４０を設けており、図１の実施形態と基本的に同じになることから、同一符号を付して説明を省略する。   As shown in FIG. 4, the step-up chopper circuit 10 includes a choke coil 18, an FET 20, a rectifying diode 22, a capacitor 24, a resistor voltage divider circuit including resistors 26 and 28, and a control IC 30, and further includes a resistor voltage divider. A correction circuit 40 for biasing the circuit resistor 28 is provided, which is basically the same as that of the embodiment of FIG.

本実施形態の抵抗分圧回路は、抵抗２６，２８に加え、その間に抵抗４８を設けて直列接続しており、出力電圧検出電圧Ｖｏは抵抗４８と抵抗２８の間から取り出しており、この場合の図２の直線特性１００は、抵抗４８の抵抗値をＲ４８とすると、
Ｖｓ＝Ｖｏ×Ｒ２８／（Ｒ２６＋Ｒ２８＋Ｒ４８）
となる。 The resistance voltage dividing circuit of the present embodiment is connected in series by providing a resistor 48 between the resistors 26 and 28, and the output voltage detection voltage Vo is taken out between the resistor 48 and the resistor 28. The linear characteristic 100 of FIG. 2 indicates that the resistance value of the resistor 48 is R48.
Vs = Vo × R28 / (R26 + R28 + R48)
It becomes.

また、補正回路４０は抵抗２６と抵抗４８の間に接続し、抵抗４８，２８の直列回路にバイアス電流Ｉｂを流してバイアス電圧Ｖｂを発生可能としている。この場合、図２の保護動作領域Ｂの動作点Ｐを決める出力起動電圧を（Ｖｏ）１とすると、抵抗分圧回路の直線特性１００（点線部分）により検出されるＱ点の出力検出電圧（Ｖｓ）１は、
（Ｖｓ）１＝（Ｖｏ）１×Ｒ２８／（Ｒ２６＋Ｒ２８＋Ｒ４８）
で与えられ、このＱ点を起動閾値電圧Ｖｔｈ１となるＰ点に引き上げるに必要なバイアス電圧Ｖｂは
Ｖｂ＝Ｖｔｈ１−（Ｖｓ）１
となる。 The correction circuit 40 is connected between the resistor 26 and the resistor 48, and a bias current Ib is allowed to flow through the series circuit of the resistors 48 and 28 so as to generate the bias voltage Vb. In this case, assuming that the output starting voltage for determining the operating point P in the protection operating region B in FIG. 2 is (Vo) 1, the output detection voltage (Q point) detected by the linear characteristic 100 (dotted line portion) of the resistance voltage dividing circuit ( Vs) 1 is
(Vs) 1 = (Vo) 1 × R28 / (R26 + R28 + R48)
The bias voltage Vb required to raise the Q point to the P point that becomes the starting threshold voltage Vth1 is Vb = Vth1- (Vs) 1
It becomes.

このように必要に応じて抵抗分圧回路に３つ以上の抵抗を設けて直列接続するようにしても良い。   In this way, if necessary, three or more resistors may be provided in the resistance voltage dividing circuit and connected in series.

［補正回路のダイオードを置き換えた実施形態］
図５は補正回路にＮＰＮトランジスタを用いた他の実施形態を示した回路ブロック図である。図５に示すように、補正回路４０は電圧源４２を、ＮＰＮトランジスタ５０を介して抵抗分圧回路の抵抗２６と抵抗２８の間に接続している。ＮＰＮトランジスタ５０はコレクタとベース間を接続しており、電圧源４２からコレクタに印加する電圧がエミッタより高い場合、ＮＰＮトランジスタ５０は導通し、ダイオードと等価に動作して抵抗２８にバイアス電流を流してバイアス電圧を発生し、図２に示した直線特性１０４に従った出力検出電圧を生成する。 [Embodiment in which diode of correction circuit is replaced]
FIG. 5 is a circuit block diagram showing another embodiment using an NPN transistor in the correction circuit. As shown in FIG. 5, the correction circuit 40 has a voltage source 42 connected between a resistor 26 and a resistor 28 of a resistor voltage dividing circuit via an NPN transistor 50. The NPN transistor 50 is connected between the collector and the base, and when the voltage applied from the voltage source 42 to the collector is higher than the emitter, the NPN transistor 50 conducts and operates equivalent to a diode to pass a bias current through the resistor 28. Thus, a bias voltage is generated, and an output detection voltage according to the linear characteristic 104 shown in FIG. 2 is generated.

図６は補正回路にＰＮＰトランジスタを用いた他の実施形態を示した回路ブロック図である。図６に示すように、補正回路４０は電圧源４２を、ＰＮＰトランジスタ５２を介して抵抗分圧回路の抵抗２６と抵抗２８の間に接続している。ＰＮＰトランジスタ５２はベースとコレクタ間を接続しており、電圧源４２からエミッタに印加する電圧がコレクタより高い場合、ＰＮＰトランジスタ５２は導通し、ダイオードと等価に動作して抵抗２８にバイアス電流を流すことによるバイアス電圧の発生で、図２に示した直線特性１０４に従った出力検出電圧を生成する。   FIG. 6 is a circuit block diagram showing another embodiment using a PNP transistor in the correction circuit. As shown in FIG. 6, the correction circuit 40 has a voltage source 42 connected between a resistor 26 and a resistor 28 of a resistance voltage dividing circuit via a PNP transistor 52. The PNP transistor 52 is connected between the base and the collector, and when the voltage applied from the voltage source 42 to the emitter is higher than the collector, the PNP transistor 52 conducts and operates equivalently to a diode to pass a bias current through the resistor 28. Thus, the output detection voltage according to the linear characteristic 104 shown in FIG. 2 is generated.

図７は補正回路にＮチャンネルＦＥＴを用いた他の実施形態を示した回路ブロック図である。図７に示すように、補正回路４０は電圧源４２を、ＮチャンネルＦＥＴ５４を介して抵抗分圧回路の抵抗２６と抵抗２８の間に接続している。ＮチャンネルＦＥＴ５４はドレインＤとゲートＧ間を接続しており、電圧源４２からドレインＤに印加する電圧がソースＳより高い場合、ＮチャンネルＦＥＴ５４は導通し、ダイオードと等価に動作して抵抗２８にバイアス電流を流すことによるバイアス電圧の発生で、図２に示した直線特性１０４に従った出力検出電圧を生成する。   FIG. 7 is a circuit block diagram showing another embodiment using an N-channel FET as a correction circuit. As shown in FIG. 7, the correction circuit 40 has a voltage source 42 connected between a resistor 26 and a resistor 28 of a resistance voltage dividing circuit via an N-channel FET 54. The N-channel FET 54 is connected between the drain D and the gate G, and when the voltage applied from the voltage source 42 to the drain D is higher than the source S, the N-channel FET 54 conducts and operates equivalent to a diode to the resistor 28. By generating a bias voltage by flowing a bias current, an output detection voltage according to the linear characteristic 104 shown in FIG. 2 is generated.

図８は補正回路にＰチャンネルＦＥＴを用いた他の実施形態を示した回路ブロック図である。図８に示すように、補正回路４０は電圧源４２を、ＰチャンネルＦＥＴ５６を介して抵抗分圧回路の抵抗２６と抵抗２８の間に接続している。ＰチャンネルＦＥＴ５６はゲートＧとソースＳ間を接続しており、電圧源４２からドレインＤに印加する電圧がソースＳより高い場合、ＰチャンネルＦＥＴ５６は導通し、ダイオードと等価に動作して抵抗２８にバイアス電流を流すことによるバイアス電圧の発生で、図２に示した直線特性１０４に従った出力検出電圧を生成する。   FIG. 8 is a circuit block diagram showing another embodiment using a P-channel FET for the correction circuit. As shown in FIG. 8, the correction circuit 40 has a voltage source 42 connected between a resistor 26 and a resistor 28 of a resistance voltage dividing circuit via a P-channel FET 56. The P-channel FET 56 is connected between the gate G and the source S, and when the voltage applied from the voltage source 42 to the drain D is higher than the source S, the P-channel FET 56 conducts and operates equivalent to a diode to the resistor 28. By generating a bias voltage by flowing a bias current, an output detection voltage according to the linear characteristic 104 shown in FIG. 2 is generated.

［本発明の変形例］
上記の実施形態は、抵抗分圧回路により昇圧チョッパ回路の出力電圧を検出する場合を例にとるものであったが、異なる出力検出特性による２つの動作点を必要とする場合に、一方の出力電圧検出特性を抵抗分圧回路により設定し、他方の出力検出特性をバイアス電圧の発生により補正して設定するものであれば、適宜の出力電圧を検出して制御する装置に広く適用することができる。 [Modification of the present invention]
In the above embodiment, the case where the output voltage of the boost chopper circuit is detected by the resistance voltage dividing circuit is taken as an example. However, when two operating points with different output detection characteristics are required, one output is detected. As long as the voltage detection characteristic is set by a resistance voltage dividing circuit and the other output detection characteristic is corrected and set by generation of a bias voltage, it can be widely applied to devices that detect and control an appropriate output voltage. it can.

また、本発明はその目的と利点を損なうことのない適宜の変形を含み、更に上記の実施形態に示した数値による限定は受けない。
The present invention includes appropriate modifications without impairing the object and advantages thereof, and is not limited by the numerical values shown in the above embodiments.

１０：昇圧チョッパ回路
１２：ＤＣ−ＤＣコンバータ
１４：交流電源
１６：全波整流回路
１８：チョークコイル
２０：ＦＥＴ
２２：整流用ダイオード
２４：コンデンサ
２６，２８：抵抗
３０：制御ＩＣ
３２：制御部
３４：入力電圧検出部
３６：正常電圧検出部
３８：起動電圧検出部
４０：補正回路
４２：電圧源
４４：ダイオード
５０：ＮＰＮトランジスタ
５２：ＰＮＰトランジスタ
５４：ＮチャンネルＦＥＴ
５６：ＰチャンネルＦＥＴ 10: Boost chopper circuit 12: DC-DC converter 14: AC power supply 16: Full-wave rectifier circuit 18: Choke coil 20: FET
22: Diode for rectification 24: Capacitor 26, 28: Resistor 30: Control IC
32: Control unit 34: Input voltage detection unit 36: Normal voltage detection unit 38: Start-up voltage detection unit 40: Correction circuit 42: Voltage source 44: Diode 50: NPN transistor 52: PNP transistor 54: N-channel FET
56: P-channel FET

Claims (5)

スイッチング動作により力率を改善すると共に入力電圧を昇圧して所定の出力電圧に安定化する昇圧チョッパ回路と、
前記昇圧チョッパ回路の出力電圧を、直列接続した少なくとも２つの抵抗で分圧して出力検出電圧を出力する抵抗分圧回路と、
前記抵抗分圧回路の出力検出電圧が所定の定格動作領域にあることを検出して正常電圧検出信号を出力する正常電圧検出部と、
前記抵抗分圧回路の出力検出電圧が前期定格動作領域の下限より低い所定の起動閾値電圧未満の場合に起動信号の出力を停止し、前記起動閾値電圧に達した場合に起動信号を出力する起動電圧検出部と、
前記起動電圧検出部から起動信号が得られた場合に昇圧チョッパ回路のスイッチング動作を開始して起動し、当該起動後に、前記正常電圧検出部から正常電圧検出信号が得られている場合に昇圧チョッパ回路を前記定格動作領域で動作させる制御部と、
を備えたスイッチング電源装置に於いて、
前記抵抗分圧回路の出力検出電圧が前記定格動作領域の下限より低く且つ前記起動閾値電圧より高い所定の補正上限電圧以下の場合に、前記抵抗分圧回路にバイアス電流を流して所定のバイアス電圧を発生し、前記抵抗分圧回路の出力検出電圧をバイアス電圧により引き上げる補正回路を設けたことを特徴とするスイッチング電源装置。
A step-up chopper circuit that improves the power factor by switching operation and boosts the input voltage to stabilize it to a predetermined output voltage;
A resistor voltage dividing circuit for dividing the output voltage of the boost chopper circuit by at least two resistors connected in series and outputting an output detection voltage;
A normal voltage detection unit for detecting that the output detection voltage of the resistance voltage divider circuit is in a predetermined rated operation region and outputting a normal voltage detection signal;
The start of outputting the start signal when the output detection voltage of the resistance voltage divider circuit is less than a predetermined start threshold voltage lower than the lower limit of the rated operation range of the previous period and when the start threshold voltage is reached A voltage detector;
When a startup signal is obtained from the startup voltage detector, the switching operation of the boost chopper circuit is started and started, and after the startup, when the normal voltage detection signal is obtained from the normal voltage detector, the boost chopper A control unit for operating a circuit in the rated operation region;
In a switching power supply device with
When the output detection voltage of the resistance voltage divider circuit is lower than a predetermined correction upper limit voltage lower than the lower limit of the rated operating region and higher than the start threshold voltage, a bias current is passed through the resistor voltage divider circuit to generate a predetermined bias voltage. And a correction circuit that raises the output detection voltage of the resistance voltage dividing circuit with a bias voltage.
請求項１記載のスイッチング電源装置に於いて、前記補正回路は、
前記所定の補正上限電圧を出力する電圧源と、
前記電圧源と前記抵抗分圧回路の分圧点との間に接続したダイオードと、
を備え、
前記電圧源は、前記補正上限電圧を前記ダイオードに印加し、前記抵抗分圧回路の出力検出電圧が前記補正上限電圧以下の場合に前記ダイオードを導通して前記抵抗分圧回路にバイアス電流を流し、前記抵抗分圧回路の出力検出電圧が前記補正上限電圧を超えた場合に前記ダイオードを非導通として前記抵抗分圧回路に流すバイアス電流を停止することを特徴とするスイッチング電源装置。
The switching power supply device according to claim 1, wherein the correction circuit includes:
A voltage source for outputting the predetermined correction upper limit voltage;
A diode connected between the voltage source and a voltage dividing point of the resistance voltage dividing circuit;
With
The voltage source applies the correction upper limit voltage to the diode, and when the output detection voltage of the resistance voltage dividing circuit is equal to or lower than the correction upper limit voltage, the voltage source is turned on to pass a bias current to the resistance voltage dividing circuit. When the output detection voltage of the resistance voltage divider circuit exceeds the correction upper limit voltage, the diode is made non-conductive and the bias current flowing through the resistance voltage divider circuit is stopped.
請求項１記載のスイッチング電源装置に於いて、前記補正回路のダイオードに代えて、トランジスタ又はＦＥＴを用いたことを特徴とするスイッチング電源装置。
2. The switching power supply device according to claim 1, wherein a transistor or an FET is used instead of the diode of the correction circuit.
請求項１記載のスイッチング電源装置に於いて、
前記昇圧チョッパ回路の入力側に、交流電圧を入力して全波整流電圧を出力する全波整流回路を設け、
前記昇圧チョッパ回路の出力側に、ＤＣ-ＤＣコンバータを設けたことを特徴とするスイッチング電源装置。
In the switching power supply device according to claim 1,
Provided on the input side of the boost chopper circuit is a full-wave rectifier circuit that inputs an alternating voltage and outputs a full-wave rectified voltage;
A switching power supply comprising a DC-DC converter on the output side of the step-up chopper circuit.
請求項１記載のスイッチング電源装置に於いて、
前記正常電圧検出部と前記起動電圧検出部は、前記昇圧チョッパ回路の制御部として機能する制御ＩＣに内蔵され、
前記制御ＩＣは単一の出力電圧検出端子を備え、当該出力電圧検出端子に前記抵抗分圧回路の分圧点を接続して出力検出電圧を入力し、
前記制御ＩＣに内蔵した前記出力電圧検出部と前記起動電圧検出部は、前記出力検出端子を共通に入力接続したことを特徴とするスイッチング電源装置。 In the switching power supply device according to claim 1,
The normal voltage detection unit and the starting voltage detection unit are built in a control IC that functions as a control unit of the boost chopper circuit,
The control IC includes a single output voltage detection terminal, connects the voltage dividing point of the resistance voltage dividing circuit to the output voltage detection terminal, and inputs an output detection voltage;
The switching power supply device, wherein the output voltage detection unit and the start-up voltage detection unit incorporated in the control IC have the output detection terminals connected in common.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109245513A (en) * 2018-11-09 2019-01-18 深圳南云微电子有限公司 A kind of start-up circuit

Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2008079448A (en) * 2006-09-22 2008-04-03 Matsushita Electric Ind Co Ltd Voltage boosting power supply unit
JP2011229233A (en) * 2010-04-16 2011-11-10 Cosel Co Ltd Power factor improvement circuit and starting operation control method thereof

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Publication number Priority date Publication date Assignee Title
JP2008079448A (en) * 2006-09-22 2008-04-03 Matsushita Electric Ind Co Ltd Voltage boosting power supply unit
JP2011229233A (en) * 2010-04-16 2011-11-10 Cosel Co Ltd Power factor improvement circuit and starting operation control method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109245513A (en) * 2018-11-09 2019-01-18 深圳南云微电子有限公司 A kind of start-up circuit
CN109245513B (en) * 2018-11-09 2024-04-09 深圳南云微电子有限公司 Starting circuit

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