JP2013533613A - 電子切替デバイスの生産 - Google Patents
電子切替デバイスの生産 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
- H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/851—Division of substrate
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
シクロヘキシルベンゼン(CAS番号827−52−1)としても公知のフェニルシクロヘキサン、
1,3−ジイソプロペニルベンゼン(CAS番号3748−13−8)、
テトラリン(CAS番号119−64−2)、
ブチルフェニルエーテル(CAS番号1126−79−0)、
N−メチル−2−ピロリドン(CAS番号872−50−4)、
2−(2−ブトキシエトキシ)エチルアセテート(CAS番号124−17−4)、
エチレングリコールブチルエーテル(CAS番号111−76−2)、
ジエチレングリコールモノエチルエーテルアセテート(CAS番号112−15−2)、
2−(2−メトキシエトキシ)エチルアセテート(CAS番号629−38−9)、
ヘキサノール(CAS番号111−27−3)、
オクタノール、
FC−70、
トリエチレングリコールジメチルエーテル(CAS番号112−49−2)、
2−エチル−1−ヘキサノール(CAS番号104−76−7)
を含む。
Claims (12)
- 1つ以上の電子切替デバイスを生産する方法であって、各切替デバイスは、2つの電極間の半導体チャネルと、切替電極から前記半導体チャネルを隔離する誘電性素子とを備え、
前記方法は、回転する第1ローラから基板上に材料を移送することによって、前記1つ以上の切替デバイスの前記半導体チャネルまたは前記誘電性素子を少なくとも部分的に形成するために前記材料の層を前記基板に蒸着させることを含む、方法。 - 前記基板に蒸着された前記層は、約7%未満の厚みの不均一性を示す、請求項1に記載の方法。
- 前記第1ローラの一回の回転でパターン層を形成するために、前記基板の選択された領域に前記材料を選択的に蒸着させることを含む、請求項1または2に記載の方法。
- 前記パターン層の組み合わされた範囲にわたる前記パターン層の厚みの不均一性は、約7%未満である、請求項3に記載の方法。
- 前記基板は、前記基板の各選択された領域において複数のパターン導電層を画定し、前記材料のパターン層は、前記パターン導電層のそれぞれにわたって前記材料の各層を提供する、請求項3または4に記載の方法。
- 前記パターン導電層のそれぞれが、トランジスタの各アレイのためのソース−ドレイン電極対の各アレイ、またはトランジスタの各アレイのためのゲート線の各アレイを画定する、請求項5に記載の方法。
- 第2ローラに前記材料を塗布し、前記第1のローラと前記第2のローラとを回転させる間に、前記第2ローラから前記第1ローラに前記材料を移送することと、前記基板上に前記第1ローラから移送された前記材料の後縁が、前記基板上に蒸着された前記層の残りの部分の平均厚よりも実質的に大きくない厚みを有するように前記第2ローラの接線速度を制御することとをさらに包含する、請求項1〜6のうちのいずれか1項に記載の方法。
- 前記第1ローラよりも速い接線速度で前記第2ローラを回転させる間に、前記第1ローラに前記第2ローラから前記材料を移送することを含む、請求項7に記載の方法。
- 前記第2ローラの前記接線速度は、前記第1ローラの前記接線速度よりも約2%〜約5%大きい、請求項8に記載の方法。
- 前記第1ローラの表面は、前記材料を受け取り、保持するための複数の平行溝を画定し、前記方法は、前記平行溝に対して垂直な方向で、前記第1ローラの上に1つ以上の洗浄溶剤を通すことによって前記第1ローラを洗浄(クリーニング)することをさらに含む、請求項1〜9のうちのいずれか1項に記載の方法。
- 前記第1ローラは、前記材料を受け取るための表面マットを備え、前記マットは、30%以上の前記材料による膨張を示すことはない、請求項1〜10のうちのいずれか1項に記載の方法。
- 前記第1ローラは、前記材料を受け取るための表面マットを備え、前記材料は、溶剤を備え、前記マットは、30%以上の前記溶剤による膨張を示すことはない、請求項1〜11のうちのいずれか1項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1009406.8A GB2480875B (en) | 2010-06-04 | 2010-06-04 | Production of electronic switching devices |
GB1009406.8 | 2010-06-04 | ||
PCT/EP2011/059223 WO2011151460A1 (en) | 2010-06-04 | 2011-06-03 | Production of electronic switching devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013533613A true JP2013533613A (ja) | 2013-08-22 |
JP6125997B2 JP6125997B2 (ja) | 2017-05-10 |
Family
ID=42471192
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013512941A Active JP6125997B2 (ja) | 2010-06-04 | 2011-06-03 | 電子切替デバイスの生産 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8987116B2 (ja) |
EP (1) | EP2572389B1 (ja) |
JP (1) | JP6125997B2 (ja) |
KR (1) | KR20130087004A (ja) |
CN (1) | CN103155193B (ja) |
GB (1) | GB2480875B (ja) |
WO (1) | WO2011151460A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6444055A (en) * | 1987-08-12 | 1989-02-16 | Seiko Epson Corp | Protective circuit |
WO2014091960A1 (ja) * | 2012-12-12 | 2014-06-19 | 株式会社ダイセル | 有機トランジスタ製造用溶剤又は溶剤組成物 |
GB2519081B (en) * | 2013-10-08 | 2019-07-03 | Flexenable Ltd | Electronic devices including organic materials |
US9362355B1 (en) | 2015-11-13 | 2016-06-07 | International Business Machines Corporation | Nanosheet MOSFET with full-height air-gap spacer |
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JP2005316310A (ja) * | 2004-04-30 | 2005-11-10 | Micro Engineering Inc | 液晶ディスプレイの製造方法 |
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JP2006190757A (ja) * | 2005-01-05 | 2006-07-20 | Konica Minolta Holdings Inc | 有機半導体層の形成方法および有機薄膜トランジスタの製造方法 |
JP2007067390A (ja) * | 2005-08-05 | 2007-03-15 | Sony Corp | 半導体装置の製造方法および半導体装置の製造装置 |
US20090074974A1 (en) * | 2007-09-18 | 2009-03-19 | Toppan Printing Co. | Method for Manufacturing Organic Functional Layer and Organic Functional Device, and Organic Functional Device Manufacturing Apparatus |
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JPH08250455A (ja) * | 1995-02-15 | 1996-09-27 | Texas Instr Inc <Ti> | 化学機械的に研磨される半導体ウェーハ面から汚染粒子を除去する方法および装置 |
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-
2010
- 2010-06-04 GB GB1009406.8A patent/GB2480875B/en not_active Expired - Fee Related
-
2011
- 2011-06-03 WO PCT/EP2011/059223 patent/WO2011151460A1/en active Application Filing
- 2011-06-03 EP EP11727666.7A patent/EP2572389B1/en not_active Not-in-force
- 2011-06-03 CN CN201180035973.3A patent/CN103155193B/zh active Active
- 2011-06-03 US US13/701,981 patent/US8987116B2/en active Active
- 2011-06-03 JP JP2013512941A patent/JP6125997B2/ja active Active
- 2011-06-03 KR KR1020137000294A patent/KR20130087004A/ko not_active Application Discontinuation
Patent Citations (8)
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JPS5853479A (ja) * | 1981-09-24 | 1983-03-30 | Seiko Epson Corp | 薄膜の製造方法 |
JPS63308923A (ja) * | 1987-06-11 | 1988-12-16 | Sony Corp | 半導体装置の製造方法 |
JP2005316310A (ja) * | 2004-04-30 | 2005-11-10 | Micro Engineering Inc | 液晶ディスプレイの製造方法 |
DE102004046428A1 (de) * | 2004-09-24 | 2006-06-08 | Infineon Technologies Ag | Hochvolumenverfahren zur Prozessierung einer molekularen selbstorganisierten Monolage als Gate-Dielektrikum bei der Herstellung organischer Feldeffekt-Transistoren |
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JP2007067390A (ja) * | 2005-08-05 | 2007-03-15 | Sony Corp | 半導体装置の製造方法および半導体装置の製造装置 |
US20090074974A1 (en) * | 2007-09-18 | 2009-03-19 | Toppan Printing Co. | Method for Manufacturing Organic Functional Layer and Organic Functional Device, and Organic Functional Device Manufacturing Apparatus |
JP2009090637A (ja) * | 2007-09-18 | 2009-04-30 | Toppan Printing Co Ltd | 有機機能層及び有機機能性素子の製造方法並びに有機機能性素子製造装置 |
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EP2572389B1 (en) | 2017-09-06 |
EP2572389A1 (en) | 2013-03-27 |
GB2480875B (en) | 2014-09-03 |
WO2011151460A1 (en) | 2011-12-08 |
CN103155193B (zh) | 2016-02-10 |
US8987116B2 (en) | 2015-03-24 |
GB201009406D0 (en) | 2010-07-21 |
GB2480875A (en) | 2011-12-07 |
US20130157443A1 (en) | 2013-06-20 |
KR20130087004A (ko) | 2013-08-05 |
JP6125997B2 (ja) | 2017-05-10 |
CN103155193A (zh) | 2013-06-12 |
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