JP2013510376A - プローブアクティビティレベルの追跡による性能状態の制御 - Google Patents
プローブアクティビティレベルの追跡による性能状態の制御 Download PDFInfo
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
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Abstract
処理ノードは、その内部キャシング又はメモリシステムに関連するプローブアクティビティレベルを追跡する。プローブアクティビティレベルがスレッショルドプローブアクティビティレベルを超えると、処理ノードの性能状態がその当座の性能状態よりも高くされて、高められた性能能力をプローブ要求に応答して提供する。プローブアクティビティレベルがスレッショルドプローブアクティビティレベルを超えたことに応答してより高い性能状態にエンターした後に、処理ノードは、プローブアクティビティの低下に応答してより低い性能状態に戻る。多重スレッショルドプローブアクティビティレベル及び関連する性能状態があってよい。
【選択図】図1
Description
(Prob_Act>PrbActM)であれば、P状態=Pm
それ以外の場合において、(Prob_Act>PrbActN)であれば、P状態=Pn
それ以外の場合において、(Prob_Act>PrbActK)であれば、P状態=Pk
(Prob_Act<(PrbActM−HystM)且つProb_ACT>PrbActN且つ当座のP状態<Pm)であれば、P状態=Pn
それ以外の場合において、(Prob_Act<(PrbActN−HystN)且つProb_ACT>PrbActK且つ当座のP状態<Pn)であれば、P状態=Pk
それ以外の場合において、(Prob_Act<(PrbActK−HystK)且つ当座のP状態<Pk)であれば、P状態=当座のP状態
Claims (14)
- 処理ノードにおけるプローブアクティビティレベルを追跡することと、
前記プローブアクティビティレベルを第1のスレッショルドプローブアクティビティレベルと比較することと、
前記プローブアクティビティレベルが前記第1のスレッショルドプローブアクティビティレベルを超えている場合に前記処理ノードの性能状態を当座の性能状態よりも高い第1の性能状態に上げることと、を備える方法。 - 前記プローブアクティビティレベルが前記スレッショルドプローブアクティビティレベルを超えていることに応答して前記第1の性能状態をエンターした後に、前記プローブアクティビティレベルが前記第1のスレッショルドプローブアクティビティよりも低い予め定められたレベルを下回る場合に前記第1の性能状態よりも低い第2の性能状態をエンターすることを更に備える請求項1に記載の方法。
- ヒステリシス因子を差し引いた前記第1のスレッショルドよりも前記プローブアクティビティレベルが低い場合に前記第2の性能状態をエンターすることを更に備える請求項2に記載の方法。
- 前記第2の性能状態は前記処理ノードが前記第1の性能状態をエンターした性能状態である請求項3に記載の方法。
- 前記第1及び第2の性能状態は電圧及び周波数の少なくとも1つによって定義される請求項1〜4のいずれかに記載の方法。
- 前記プローブアクティビティレベルが前記第1のスレッショルドプローブアクティビティレベルよりも高い第2のスレッショルドプローブアクティビティレベルを超えて増大することに応答して前記処理ノードの前記性能状態を前記第1の性能状態よりも高い第3の性能状態に上げることと、
前記プローブアクティビティレベルが前記第2のスレッショルドプローブアクティビティレベルを超えて増大することに応答して前記処理ノードの前記性能状態を前記第3の性能状態に上げた後に前記性能状態を下げることと、を更に備える請求項1〜4のいずれかに記載の方法。 - 前記処理ノードが前記第1の性能状態を下回る性能状態にある場合に前記プローブアクティビティレベルの前記追跡することを開始することを更に備える請求項1〜4のいずれかに記載の方法。
- 前記プローブアクティビティを追跡することは、
各プローブ要求をキュー内にエンターすること並びにデータ移動及び応答の少なくとも一方を伴うプローブ要求に前記処理ノードが応答した後に前記プローブ要求を前記キューからリタイヤさせることと、
前記キュー内のエントリの数を前記第1のスレッショルドプローブアクティビティレベルと比較して前記プローブアクティビティが前記第1のスレッショルドプローブアクティビティレベルを上回っているかどうかを決定することと、を更に備える請求項1〜4のいずれかに記載の方法。 - 前記プローブアクティビティを追跡することは、プローブアクティビティの発生に応答してプローブアクティビティのレベルを表すカウント値をインクリメントすることと、予め定められた時間の経過に基づいて前記カウント値をデクリメントすることと、を更に備える請求項1〜4のいずれかに記載の方法。
- 処理ノードにおけるプローブアクティビティレベルを追跡するプローブ追跡器を備える装置であって、
前記装置は前記プローブアクティビティレベルが第1のスレッショルドプローブアクティビティレベルを超えて増大する場合に前記処理ノードの性能状態を当座の性能状態から第1の性能状態に上げるように動作し、
前記装置は前記第1のスレッショルドプローブアクティビティレベルより低い予め定められたレベルまで前記プローブアクティビティレベルが下がることに応答して前記第1の性能状態よりも低い第2の性能状態に前記処理ノードをエンターさせ、
前記第1及び第2の性能状態は電圧及び周波数の少なくとも一方によって定義される装置。 - 前記装置は前記プローブアクティビティレベルが前記第1のスレッショルドプローブアクティビティレベルよりも高い第2のスレッショルドプローブアクティビティレベルを超えて増大することに応答して前記処理ノードの前記性能状態を前記第1の性能状態よりも高い第3の性能状態に上げるように更に動作可能である請求項10に記載の装置。
- 前記プローブ追跡器は前記ノードが前記第1の性能状態より低い性能状態にあることに応答して前記プローブアクティビティレベルの追跡を開始する請求項10に記載の装置。
- 前記プローブ追跡器はキューを更に備え、
前記キュー内にプローブ要求がエンターされ、データ移動及び応答の少なくとも一方を伴うプローブ要求に前記処理ノードが応答した後に前記キュー内の前記プローブ要求は前記キューからリタイヤさせられ、
前記装置は前記キュー内のエントリの数を前記第1のスレッショルドプローブアクティビティレベルと比較して前記プローブアクティビティが第1のスレッショルドプローブアクティビティレベルを上回っているかどうかを決定するように動作可能である請求項10〜12のいずれかに記載の装置。 - 前記プローブ追跡器は、プローブアクティビティに応答してプローブアクティビティのレベルを表すカウント値をインクリメントすると共に予め定められた時間の経過に応答して前記カウント値をデクリメントするカウンタを備える請求項10〜12のいずれかに記載の装置。
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US25879809P | 2009-11-06 | 2009-11-06 | |
US61/258,798 | 2009-11-06 | ||
US12/623,997 US20110112798A1 (en) | 2009-11-06 | 2009-11-23 | Controlling performance/power by frequency control of the responding node |
US12/623,997 | 2009-11-23 | ||
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EP2497001A1 (en) | 2012-09-12 |
US20110113202A1 (en) | 2011-05-12 |
US20110112798A1 (en) | 2011-05-12 |
WO2011057059A1 (en) | 2011-05-12 |
KR20120102629A (ko) | 2012-09-18 |
CN102667665A (zh) | 2012-09-12 |
US9021209B2 (en) | 2015-04-28 |
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