JP2013179325A - 半導体装置および半導体装置のヒューズ溶断方法 - Google Patents
半導体装置および半導体装置のヒューズ溶断方法 Download PDFInfo
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- JP2013179325A JP2013179325A JP2013087090A JP2013087090A JP2013179325A JP 2013179325 A JP2013179325 A JP 2013179325A JP 2013087090 A JP2013087090 A JP 2013087090A JP 2013087090 A JP2013087090 A JP 2013087090A JP 2013179325 A JP2013179325 A JP 2013179325A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Microelectronics & Electronic Packaging (AREA)
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- Semiconductor Integrated Circuits (AREA)
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Abstract
【解決手段】半導体装置は、コア回路形成領域およびバッファ形成領域を含む活性領域と、活性領域の角部に配置された電気的に溶断可能なヒューズ素子形成領域とを有する。活性領域角部にヒューズ素子形成領域を配置することにより、コア回路形成領域にヒューズを形成することなく、ヒューズ素子を配置することが可能となる。
【選択図】図1
Description
2 バッファ形成領域
3 パッド形成領域
4 ヒューズマクロ
5 ヒューズ
6 パッド列
7 ヒューズ用パッド
10 活性領域
21 ヒューズ断線用配線
100 半導体チップ
Claims (7)
- 半導体チップ上に、
活性領域と、
前記活性領域の角部に配置された電気的に溶断可能なヒューズ素子形成領域と、
を備え、
前記ヒューズ素子形成領域のヒューズに接続され、前記角部の上層における複数の配線層に形成されたヒューズ溶断用配線を有する
半導体装置。 - 前記半導体装置は、さらに、
前記ヒューズ素子形成領域のヒューズに電気的に接続された第1のパッドと第2のパッドとを備え、
前記第1のパッドは外部端子に電気的に接続され、前記第2のパッドは前記外部端子に対して電気的にオープンである
請求項1に記載の半導体装置。 - 前記第1のパッドはワイヤボンディングにより前記外部端子に電気的に接続された請求項2記載の半導体装置。
- 前記第2のパッドが、前記第1のパッドよりも、前記半導体チップの角に近いことを特徴とする請求項2または3に記載の半導体装置。
- 前記半導体装置は、さらに、
同一のヒューズに対して電圧を印加可能な3以上のパッドが設けられている、請求項2乃至4のいずれか1項に記載の半導体装置。 - 前記半導体装置は、さらに、
SRAMを備え、
前記SRAMは前記ヒューズ素子形成領域のヒューズと電気的に接続されている、請求項1乃至5のいずれか1項に記載の半導体装置。 - 前記ヒューズ素子形成領域のヒューズは前記SRAMの不良素子を冗長素子で救済する、請求項6に記載の半導体装置。
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JP2013087090A JP5592970B2 (ja) | 2013-04-18 | 2013-04-18 | 半導体装置および半導体装置のヒューズ溶断方法 |
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JP2013087090A JP5592970B2 (ja) | 2013-04-18 | 2013-04-18 | 半導体装置および半導体装置のヒューズ溶断方法 |
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JP2007135876A Division JP5254569B2 (ja) | 2007-05-22 | 2007-05-22 | 半導体装置および半導体装置のヒューズ溶断方法 |
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JP2013179325A true JP2013179325A (ja) | 2013-09-09 |
JP5592970B2 JP5592970B2 (ja) | 2014-09-17 |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH024245U (ja) * | 1988-06-21 | 1990-01-11 | ||
JPH02283051A (ja) * | 1989-04-25 | 1990-11-20 | Seiko Epson Corp | 半導体装置 |
JP2000091438A (ja) * | 1998-08-26 | 2000-03-31 | Siemens Ag | 半導体デバイスとその製造方法 |
JP2001085526A (ja) * | 1999-09-10 | 2001-03-30 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
JP2004214580A (ja) * | 2003-01-09 | 2004-07-29 | Oki Electric Ind Co Ltd | ヒューズレイアウト,及びトリミング方法 |
US20050167825A1 (en) * | 2004-01-30 | 2005-08-04 | Broadcom Corporation | Fuse corner pad for an integrated circuit |
JP2006040916A (ja) * | 2004-07-22 | 2006-02-09 | Seiko Epson Corp | 半導体装置及びその製造方法 |
-
2013
- 2013-04-18 JP JP2013087090A patent/JP5592970B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH024245U (ja) * | 1988-06-21 | 1990-01-11 | ||
JPH02283051A (ja) * | 1989-04-25 | 1990-11-20 | Seiko Epson Corp | 半導体装置 |
JP2000091438A (ja) * | 1998-08-26 | 2000-03-31 | Siemens Ag | 半導体デバイスとその製造方法 |
JP2001085526A (ja) * | 1999-09-10 | 2001-03-30 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
JP2004214580A (ja) * | 2003-01-09 | 2004-07-29 | Oki Electric Ind Co Ltd | ヒューズレイアウト,及びトリミング方法 |
US20050167825A1 (en) * | 2004-01-30 | 2005-08-04 | Broadcom Corporation | Fuse corner pad for an integrated circuit |
JP2006040916A (ja) * | 2004-07-22 | 2006-02-09 | Seiko Epson Corp | 半導体装置及びその製造方法 |
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