JP2013149650A - Photoelectric conversion device - Google Patents

Photoelectric conversion device Download PDF

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JP2013149650A
JP2013149650A JP2012006916A JP2012006916A JP2013149650A JP 2013149650 A JP2013149650 A JP 2013149650A JP 2012006916 A JP2012006916 A JP 2012006916A JP 2012006916 A JP2012006916 A JP 2012006916A JP 2013149650 A JP2013149650 A JP 2013149650A
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Hiroki Kan
紘己 韓
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Kyocera Corp
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
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    • Y02E10/541—CuInSe2 material PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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    • Y02E10/543—Solar cells from Group II-VI materials

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Abstract

PROBLEM TO BE SOLVED: To improve the photoelectric conversion efficiency of a photoelectric conversion device.SOLUTION: A photoelectric conversion device 11 includes, on a substrate 1, a sequential stack of a lower electrode layer 2, a first semiconductor layer 3, a second semiconductor layer 4 having a different conductivity type from that of the first semiconductor layer 3, a high resistance layer 6, and an upper electrode layer 5. The high resistance layer 6 includes a sequential stack of a first layer 6a having a higher electrical resistivity than that of the upper electrode layer 5, a second layer 6b having a lower electrical resistivity than that of the first layer 6a, and a third layer 6c having a higher electrical resistivity than those of the second layer 6b and the upper electrode layer 5, from the second semiconductor layer 4 side.

Description

本発明は、半導体層が積層されて成る光電変換装置に関する。   The present invention relates to a photoelectric conversion device in which semiconductor layers are stacked.

太陽光発電などに使用される光電変換装置として、基板の上に複数の半導体層が積層されたものがある。このような光電変換装置は、ガラスなどの基板の上に、下部電極層と、第１の半導体層と、第１の半導体層とは異なる導電型の第２の半導体層と、体積抵抗率が１０４Ω・ｃｍ以上の高抵抗層と、上部電極層とが、この順に積層されて構成されている（例えば、特許文献１など）。 As a photoelectric conversion device used for solar power generation or the like, there is one in which a plurality of semiconductor layers are stacked on a substrate. Such a photoelectric conversion device includes a lower electrode layer, a first semiconductor layer, a second semiconductor layer having a conductivity type different from the first semiconductor layer, and a volume resistivity on a substrate such as glass. A high resistance layer of 10 4 Ω · cm or more and an upper electrode layer are laminated in this order (for example, Patent Document 1).

特開２００５−１２３２７２号公報JP 2005-123272 A

上記光電変換装置において、高抵抗層は第２の半導体層の欠陥部におけるリーク電流を低減する機能を有する。光電変換装置の光電変換効率を高めるためには、この高抵抗層を厚くしてリーク電流をさらに抑制することが考えられる。しかしながら、高抵抗層を厚くすると電気抵抗が高くなり、光電変換効率を十分に高めることが困難である。   In the photoelectric conversion device, the high resistance layer has a function of reducing leakage current in a defect portion of the second semiconductor layer. In order to increase the photoelectric conversion efficiency of the photoelectric conversion device, it is conceivable to increase the thickness of the high resistance layer to further suppress the leakage current. However, increasing the thickness of the high resistance layer increases the electrical resistance, and it is difficult to sufficiently increase the photoelectric conversion efficiency.

本発明の目的は、光電変換装置の光電変換効率を向上させることにある。   An object of the present invention is to improve the photoelectric conversion efficiency of a photoelectric conversion device.

本発明の一実施形態に係る光電変換装置は、基板上に下部電極層、第１の半導体層、該第１の半導体層とは異なる導電型の第２の半導体層、高抵抗層および上部電極層が順に積層された光電変換装置であって、前記高抵抗層は、前記第２の半導体層側から、前記上部電極層よりも電気抵抗率の高い第１の層と、該第１の層よりも電気抵抗率の低い第２の層と、該第２の層および前記上部電極層よりも電気抵抗率の高い第３の層とが順に積層されている。   A photoelectric conversion device according to an embodiment of the present invention includes a lower electrode layer, a first semiconductor layer, a second semiconductor layer having a conductivity type different from that of the first semiconductor layer, a high resistance layer, and an upper electrode on a substrate. In the photoelectric conversion device in which layers are stacked in order, the high resistance layer includes a first layer having a higher electrical resistivity than the upper electrode layer, and the first layer, from the second semiconductor layer side. The second layer having a lower electrical resistivity than the second layer and the third layer having a higher electrical resistivity than the second layer and the upper electrode layer are sequentially stacked.

本発明によれば、光電変換装置の光電変換効率を向上させることができる。   ADVANTAGE OF THE INVENTION According to this invention, the photoelectric conversion efficiency of a photoelectric conversion apparatus can be improved.

光電変換装置の実施の形態の一例を示す斜視図である。It is a perspective view which shows an example of embodiment of a photoelectric conversion apparatus. 図１の光電変換装置の断面図である。It is sectional drawing of the photoelectric conversion apparatus of FIG. 図１の光電変換装置の要部拡大断面図である。It is a principal part expanded sectional view of the photoelectric conversion apparatus of FIG.

以下に本発明の一実施形態に係る光電変換装置について、図面を参照しながら詳細に説明する。   Hereinafter, a photoelectric conversion device according to an embodiment of the present invention will be described in detail with reference to the drawings.

図１は、本発明の一実施形態に係る光電変換装置の一例を示す斜視図であり、図２はその断面図である。また、図３は図２をさらに拡大した要部拡大断面図である。光電変換装置１１は、基板１上に複数の光電変換セル１０が並べられて互いに電気的に接続されている。なお、図１においては図示の都合上、２つの光電変換セル１０のみを示しているが、
実際の光電変換装置１１においては、図面左右方向、あるいはさらにこれに垂直な方向に、多数の光電変換セル１０が平面的に（二次元的に）配設されていてもよい。 FIG. 1 is a perspective view illustrating an example of a photoelectric conversion apparatus according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view thereof. FIG. 3 is an enlarged cross-sectional view of a main part, further expanding FIG. In the photoelectric conversion device 11, a plurality of photoelectric conversion cells 10 are arranged on the substrate 1 and are electrically connected to each other. In FIG. 1, only two photoelectric conversion cells 10 are shown for convenience of illustration.
In the actual photoelectric conversion device 11, a large number of photoelectric conversion cells 10 may be arranged in a plane (two-dimensionally) in the left-right direction of the drawing or in a direction perpendicular thereto.

図１、図２において、基板１上に複数の下部電極層２が平面配置されている。図１、図２において、複数の下部電極層２は、一方向に間隔をあけて並べられた下部電極層２ａ〜２ｃを具備している。この下部電極層２ａ上から基板１上を経て下部電極層２ｂ上にかけて、第１の半導体層３が設けられている。また、第１の半導体層３上には、第１の半導体層３とは異なる導電型の第２の半導体層４、高抵抗層６および上部電極層５がこの順に設けられている。さらに、下部電極層２ｂ上において、接続導体７が、第１の半導体層３および第２の半導体層４の側面に沿って、または第１の半導体層３および第２の半導体層４を貫通して設けられている。この接続導体７は、上部電極層５と下部電極層２ｂとを電気的に接続している。これら、下部電極層２、第１の半導体層３、第２の半導体層４、高抵抗層６、上部電極層５および接続導体７によって、１つの光電変換セル１０を構成している。   1 and 2, a plurality of lower electrode layers 2 are arranged in a plane on a substrate 1. 1 and 2, the plurality of lower electrode layers 2 include lower electrode layers 2 a to 2 c that are arranged at intervals in one direction. A first semiconductor layer 3 is provided from the lower electrode layer 2a through the substrate 1 to the lower electrode layer 2b. On the first semiconductor layer 3, a second semiconductor layer 4 having a conductivity type different from that of the first semiconductor layer 3, a high resistance layer 6, and an upper electrode layer 5 are provided in this order. Furthermore, on the lower electrode layer 2 b, the connection conductor 7 penetrates the first semiconductor layer 3 and the second semiconductor layer 4 along the side surfaces of the first semiconductor layer 3 and the second semiconductor layer 4. Is provided. The connection conductor 7 electrically connects the upper electrode layer 5 and the lower electrode layer 2b. The lower electrode layer 2, the first semiconductor layer 3, the second semiconductor layer 4, the high resistance layer 6, the upper electrode layer 5, and the connection conductor 7 constitute one photoelectric conversion cell 10.

このような構成によって、隣接する光電変換セル１０同士が直列接続された、高出力の光電変換装置１１となる。なお、本実施形態における光電変換装置１１は、上部電極層５側から光が入射されるものを想定しているが、これに限定されず、基板１側から光が入射されるものであってもよい。   With such a configuration, a high-output photoelectric conversion device 11 is formed in which adjacent photoelectric conversion cells 10 are connected in series. In addition, although the photoelectric conversion apparatus 11 in this embodiment assumes what injects light from the upper electrode layer 5 side, it is not limited to this, Light is incident from the board | substrate 1 side, Also good.

基板１は、光電変換セル１０を支持するためのものである。基板１に用いられる材料としては、例えば、ガラス、セラミックス、樹脂および金属等が挙げられる。基板１としては、例えば、厚さ１〜３ｍｍ程度の青板ガラス（ソーダライムガラス）を用いることができる。   The substrate 1 is for supporting the photoelectric conversion cell 10. Examples of the material used for the substrate 1 include glass, ceramics, resin, and metal. As the substrate 1, for example, blue plate glass (soda lime glass) having a thickness of about 1 to 3 mm can be used.

下部電極層２（下部電極層２ａ、２ｂ、２ｃ）は、基板１上に設けられた、Ｍｏ、Ａｌ、ＴｉまたはＡｕ等の導電体である。下部電極層２は、スパッタリング法または蒸着法などの公知の薄膜形成手法を用いて、０．２μｍ〜１μｍ程度の厚みに形成される。   The lower electrode layer 2 (lower electrode layers 2a, 2b and 2c) is a conductor such as Mo, Al, Ti or Au provided on the substrate 1. The lower electrode layer 2 is formed to a thickness of about 0.2 μm to 1 μm using a known thin film forming method such as sputtering or vapor deposition.

第１の半導体層３は第１導電型の半導体層であり、光吸収層として機能する。第１の半導体層３の材料は特に限定されないが、例えば１μｍ〜３μｍ程度の厚みでも良好な光電変換効率が得られるという観点からは、例えば、第II−VI族化合物、Ｉ−III−VI族化合
物およびＩ−II−IV−VI族化合物等の金属カルコゲナイドや、非晶質シリコン等が好適に用いられ得る。 The first semiconductor layer 3 is a first conductivity type semiconductor layer and functions as a light absorption layer. Although the material of the 1st semiconductor layer 3 is not specifically limited, For example, from a viewpoint that favorable photoelectric conversion efficiency is obtained even with the thickness of about 1 micrometer-3 micrometers, for example, a II-VI group compound, I-III-VI group Metal chalcogenides such as compounds and I-II-IV-VI group compounds, amorphous silicon, and the like can be suitably used.

II−VI族化合物とは、II−Ｂ族（１２族元素ともいう）とVI−Ｂ族元素（１６族元素ともいう）との化合物半導体である。II−VI族化合物としては、例えば、ＣｄＴｅ等が挙げられる。   The II-VI group compound is a compound semiconductor of a II-B group (also referred to as a group 12 element) and a VI-B group element (also referred to as a group 16 element). Examples of II-VI group compounds include CdTe.

Ｉ−III−VI族化合物とは、Ｉ−Ｂ族元素（１１族元素ともいう）とIII−Ｂ族元素（１３族元素ともいう）とVI-Ｂ族元素との化合物である。Ｉ−III−VI族化合物としては、例えば、ＣｕＩｎＳｅ２（二セレン化銅インジウム、ＣＩＳともいう）、Ｃｕ（Ｉｎ，Ｇａ）Ｓｅ２（二セレン化銅インジウム・ガリウム、ＣＩＧＳともいう）、Ｃｕ（Ｉｎ，Ｇａ）（Ｓｅ，Ｓ）２（二セレン・イオウ化銅インジウム・ガリウム、ＣＩＧＳＳともいう）が挙げられる。あるいは、第１の半導体層３は、薄膜の二セレン・イオウ化銅インジウム・ガリウム層を表面層として有する二セレン化銅インジウム・ガリウム等の多元化合物半導体薄膜にて構成されていてもよい。 The I-III-VI group compound is a compound of a group IB element (also referred to as a group 11 element), a group III-B element (also referred to as a group 13 element), and a group VI-B element. Examples of the I-III-VI group compound include CuInSe 2 (also referred to as copper indium selenide, CIS), Cu (In, Ga) Se 2 (also referred to as copper indium selenide / gallium, CIGS), Cu ( In, Ga) (Se, S) 2 (also referred to as diselene / copper indium / gallium / CIGSS). Alternatively, the first semiconductor layer 3 may be composed of a multi-component compound semiconductor thin film such as copper indium selenide / gallium having a thin film of selenite / copper indium sulfide / gallium layer as a surface layer.

Ｉ−II−IV−VI族化合物とは、Ｉ−Ｂ族元素とII−Ｂ族元素とIV−Ｂ族元素（１４族元素ともいう）とVI−Ｂ族元素との化合物である。Ｉ−II−IV−VI族化合物としては、例え
ば、Ｃｕ２ＺｎＳｎＳ４（ＣＺＴＳともいう）、Ｃｕ２ＺｎＳｎ（Ｓ，Ｓｅ）４（ＣＺＴＳＳｅともいう）、およびＣｕ２ＺｎＳｎＳｅ４（ＣＺＴＳｅともいう）が挙げられる。 The I-II-IV-VI group compound is a compound of a group IB element, a group II-B element, a group IV-B element (also referred to as a group 14 element), and a group VI-B element. Examples of the I-II-IV-VI group compound include Cu 2 ZnSnS 4 (also referred to as CZTS), Cu 2 ZnSn (S, Se) 4 (also referred to as CZTSSe), and Cu 2 ZnSnSe 4 (also referred to as CZTSe). Can be mentioned.

第１の半導体層３は、スパッタリング法、蒸着法などのいわゆる真空プロセスによって形成可能であるほか、いわゆる塗布法あるいは印刷法と称されるプロセスによって形成することもできる。塗布法あるいは印刷法と称されるプロセスは、第１の半導体層３の構成元素の錯体溶液を下部電極層２の上に塗布し、その後、乾燥・熱処理を行うプロセスである。   The first semiconductor layer 3 can be formed by a so-called vacuum process such as a sputtering method or an evaporation method, or can be formed by a process called a coating method or a printing method. A process referred to as a coating method or a printing method is a process in which a complex solution of constituent elements of the first semiconductor layer 3 is applied onto the lower electrode layer 2 and then dried and heat-treated.

第２の半導体層４は、第１の半導体層３とは異なる第２導電型を有する半導体層である。第１の半導体層３および第２の半導体層４が電気的に接合することにより、電荷を良好に取り出すことが可能な光電変換層が形成される。例えば、第１の半導体層３がｐ型であれば、第２の半導体層４はｎ型である。第１の半導体層３がｎ型で、第２の半導体層４がｐ型であってもよい。なお、第１の半導体層３と第２の半導体層４との間に高抵抗のバッファ層が介在していてもよい。   The second semiconductor layer 4 is a semiconductor layer having a second conductivity type different from that of the first semiconductor layer 3. When the first semiconductor layer 3 and the second semiconductor layer 4 are electrically joined to each other, a photoelectric conversion layer from which charges can be favorably extracted is formed. For example, if the first semiconductor layer 3 is p-type, the second semiconductor layer 4 is n-type. The first semiconductor layer 3 may be n-type and the second semiconductor layer 4 may be p-type. A high-resistance buffer layer may be interposed between the first semiconductor layer 3 and the second semiconductor layer 4.

第２の半導体層４は、第１の半導体層３とは異なる材料が第１の半導体層３上に積層されたものであってもよく、あるいは第１の半導体層３の表面部が他の元素のドーピングによって改質されたものであってもよい。   The second semiconductor layer 4 may be formed by stacking a material different from that of the first semiconductor layer 3 on the first semiconductor layer 3, or the surface portion of the first semiconductor layer 3 may be other than the first semiconductor layer 3. It may be modified by elemental doping.

第２の半導体層４としては、ＣｄＳ、ＺｎＳ、ＺｎＯ、Ｉｎ２Ｓ３、Ｉｎ２Ｓｅ３、Ｚｎ（ＯＨ，Ｓ）、Ｉｎ（ＯＨ，Ｓ）、（Ｚｎ，Ｉｎ）（Ｓｅ，ＯＨ）、および（Ｚｎ，Ｍｇ）Ｏ等が挙げられる。この場合、第２の半導体層４は例えば１０〜２００ｎｍの厚みで形成される。なお、Ｚｎ（ＯＨ，Ｓ）とは、Ｚｎ（ＯＨ）２とＺｎＳを含む混晶化合物をいう。Ｉｎ（ＯＨ，Ｓ）とは、Ｉｎ（ＯＨ）３とＩｎ２Ｓ３とを含む混晶化合物をいう。（Ｚｎ，Ｉｎ）（Ｓｅ，ＯＨ）は、Ｚｎ（ＯＨ）２、ＺｎＳ、Ｉｎ（ＯＨ）３およびＩｎ２Ｓ３を含む混晶化合物をいう。（Ｚｎ，Ｍｇ）Ｏは、ＺｎＯとＭｇＯとを含む混晶化合物をいう。第１の半導体層３と良好なヘテロ接合を形成するという観点からは、第２の半導体層４として、例えばＺｎ（ＯＨ，Ｓ）、Ｉｎ（ＯＨ，Ｓ）または（Ｚｎ，Ｉｎ）（Ｓｅ，ＯＨ）等のような、金属水酸化物および金属カルコゲナイドを含む混晶化合物が好適に用いられ得る。このような混晶化合物は、例えば水溶液中で半導体層を析出させる、いわゆるケミカルバスデポジション（ＣＢＤ）法等によって形成され得る。 As the second semiconductor layer 4, CdS, ZnS, ZnO, In 2 S 3 , In 2 Se 3 , Zn (OH, S), In (OH, S), (Zn, In) (Se, OH), And (Zn, Mg) O. In this case, the second semiconductor layer 4 is formed with a thickness of 10 to 200 nm, for example. Zn (OH, S) refers to a mixed crystal compound containing Zn (OH) 2 and ZnS. In (OH, S) refers to a mixed crystal compound containing In (OH) 3 and In 2 S 3 . (Zn, In) (Se, OH) refers to a mixed crystal compound containing Zn (OH) 2 , ZnS, In (OH) 3 and In 2 S 3 . (Zn, Mg) O refers to a mixed crystal compound containing ZnO and MgO. From the viewpoint of forming a good heterojunction with the first semiconductor layer 3, the second semiconductor layer 4 may be, for example, Zn (OH, S), In (OH, S) or (Zn, In) (Se, A mixed crystal compound containing a metal hydroxide and a metal chalcogenide, such as OH), can be preferably used. Such a mixed crystal compound can be formed by, for example, a so-called chemical bath deposition (CBD) method in which a semiconductor layer is deposited in an aqueous solution.

高抵抗層６は、第２の半導体層４側から、上部電極層５よりも電気抵抗率の高い第１の層６ａと、この第１の層６ａよりも電気抵抗率の低い第２の層６ｂと、この第２の層６ｂおよび上記上部電極層５よりも電気抵抗率の高い第３の層６ｃとが順に積層されている。なお、第１の層６ａ、第２の層６ｂおよび第３の層６ｃは、それぞれが単層であっても複数層から成るものであってもよい。このような構成により、高抵抗層６が第２の半導体層４の欠陥部におけるリーク電流を低減する機能を有するとともに、高抵抗層６中に電気抵抗率の比較的低い第２の層６ｂが存在することによって高抵抗層６の電気抵抗を低くすることができる。その結果、光電変換装置１１の光電変換効率が高められる。   The high resistance layer 6 includes, from the second semiconductor layer 4 side, a first layer 6a having a higher electrical resistivity than the upper electrode layer 5, and a second layer having a lower electrical resistivity than the first layer 6a. 6b and the second layer 6b and the third layer 6c having a higher electrical resistivity than the upper electrode layer 5 are laminated in this order. Each of the first layer 6a, the second layer 6b, and the third layer 6c may be a single layer or a plurality of layers. With such a configuration, the high resistance layer 6 has a function of reducing the leakage current in the defective portion of the second semiconductor layer 4, and the second layer 6 b having a relatively low electrical resistivity is included in the high resistance layer 6. By existing, the electric resistance of the high resistance layer 6 can be lowered. As a result, the photoelectric conversion efficiency of the photoelectric conversion device 11 is increased.

第１の層６ａの電気抵抗率は上部電極層５の電気抵抗率の１０４〜１０１２倍程度とされ得る。また、第２の層６ｂの電気抵抗率は第１の層６ａの電気抵抗率の１０−１２〜１０−４倍程度とされ得る。また、第３の層６ｃの電気抵抗率は上部電極層５の電気抵抗率の１０４〜１０１２倍程度とされ得る。 The electrical resistivity of the first layer 6 a can be about 10 4 to 10 12 times the electrical resistivity of the upper electrode layer 5. In addition, the electrical resistivity of the second layer 6b can be about 10 −12 to 10 −4 times the electrical resistivity of the first layer 6a. In addition, the electrical resistivity of the third layer 6 c can be about 10 4 to 10 12 times the electrical resistivity of the upper electrode layer 5.

また、第１の層６ａ、第２の層６ｂおよび第３の層６ｃの各層の厚みは５〜５０ｎｍ程度とされ得る。また、高抵抗層６の光透過率を高くして第１の半導体層３への光透過を良好にするという観点からは、第２の層６ｂは第１の層６ａおよび第３の層６ｃの各層より
も薄くてもよい。好適には、第２の層６ｂが、第１の層６ａまたは第３の層６ｃの厚みの０．２〜０．９倍程度とされ得る。 The thickness of each of the first layer 6a, the second layer 6b, and the third layer 6c can be about 5 to 50 nm. From the viewpoint of increasing the light transmittance of the high resistance layer 6 to improve the light transmission to the first semiconductor layer 3, the second layer 6b is composed of the first layer 6a and the third layer 6c. It may be thinner than each layer. Preferably, the second layer 6b can be about 0.2 to 0.9 times the thickness of the first layer 6a or the third layer 6c.

第１の層６ａ、第２の層６ｂおよび第３の層６ｃは、例えばＩＴＯ、ＺｎＯ等の金属酸化物等が用いられ、スパッタリング法、蒸着法、化学的気相成長（ＣＶＤ）法、スピンコート法、スプレー法等で形成され得る。各層の電気抵抗率は、例えば酸素含有率を調整したり、他の元素をドーピングしたりすることで所望の値に調整され得る。   For the first layer 6a, the second layer 6b, and the third layer 6c, for example, a metal oxide such as ITO or ZnO is used, and sputtering, vapor deposition, chemical vapor deposition (CVD), spin, and the like are used. It can be formed by a coating method, a spray method or the like. The electrical resistivity of each layer can be adjusted to a desired value, for example, by adjusting the oxygen content or doping with other elements.

また、第２の半導体層４および上部電極層５がＩｎ元素を含む場合、第２の層６ｂはＩｎ元素を含み、第１の層６ａおよび第３の層６ｃはＺｎ元素を含んでいてもよい。このような具体例としては、例えば、第２の半導体層４がＩｎ２Ｓ３を含み、上部電極層５および第２の層６ｂがＩＴＯを含み、第１の層６ａおよび第３の層６ｃがＺｎＯを含む構成が挙げられる。このような構成であれば、上部電極層５のＩｎ元素が第２の半導体層４中へ拡散するのを、Ｉｎを含む第２の層６ｂが介在された高抵抗層６によって有効に抑制することができる。その結果、第１の半導体層３と第２の半導体層４とのｐｎ接合を良好に維持することができ、光電変換装置１１の高い光電変換効率を安定に維持することができる。 Further, when the second semiconductor layer 4 and the upper electrode layer 5 contain an In element, the second layer 6b may contain an In element, and the first layer 6a and the third layer 6c may contain a Zn element. Good. As a specific example, for example, the second semiconductor layer 4 includes In 2 S 3 , the upper electrode layer 5 and the second layer 6b include ITO, and the first layer 6a and the third layer 6c. Include ZnO. With such a configuration, the In element in the upper electrode layer 5 is effectively prevented from diffusing into the second semiconductor layer 4 by the high resistance layer 6 in which the second layer 6b containing In is interposed. be able to. As a result, the pn junction between the first semiconductor layer 3 and the second semiconductor layer 4 can be favorably maintained, and the high photoelectric conversion efficiency of the photoelectric conversion device 11 can be stably maintained.

上部電極層５は、第２の半導体層４よりも電気抵抗率の低い層であり、第１の半導体層３および第２の半導体層４で生じた電荷を良好に取り出す機能を有する。光電変換効率をより高めるという観点からは、上部電極層５の抵抗率が１Ω・ｃｍ未満でシート抵抗が５０Ω／□以下であってもよい。   The upper electrode layer 5 is a layer having a lower electrical resistivity than the second semiconductor layer 4 and has a function of favorably extracting charges generated in the first semiconductor layer 3 and the second semiconductor layer 4. From the viewpoint of further increasing the photoelectric conversion efficiency, the resistivity of the upper electrode layer 5 may be less than 1 Ω · cm and the sheet resistance may be 50 Ω / □ or less.

上部電極層５は、例えばＩＴＯ、Ａｌ元素を含むＺｎＯ、Ｂ元素を含むＺｎＯ等の０．０５〜３μｍの透明導電膜である。透光性および導電性を高めるため、上部電極層５は第２の半導体層４と同じ導電型の半導体で構成されてもよい。上部電極層５は、スパッタリング法、蒸着法またはＣＶＤ法等で形成され得る。   The upper electrode layer 5 is a transparent conductive film having a thickness of 0.05 to 3 μm, such as ITO, ZnO containing an Al element, or ZnO containing a B element. In order to improve translucency and conductivity, the upper electrode layer 5 may be composed of a semiconductor having the same conductivity type as the second semiconductor layer 4. The upper electrode layer 5 can be formed by sputtering, vapor deposition, CVD, or the like.

また、図１〜図３に示すように、上部電極層５上にさらに集電電極８が形成されていてもよい。集電電極８は、第１の半導体層３および第２の半導体層４で生じた電荷をさらに良好に取り出すためのものである。集電電極８は、例えば、図１に示すように、光電変換セル１０の一端から接続導体７にかけて線状に形成されている。これにより、第１の半導体層３および第４の半導体層４で生じた電流が上部電極層５を介して集電電極８に集電され、接続導体７を介して隣接する光電変換セル１０に良好に通電される。   Further, as shown in FIGS. 1 to 3, a collecting electrode 8 may be further formed on the upper electrode layer 5. The current collecting electrode 8 is for taking out charges generated in the first semiconductor layer 3 and the second semiconductor layer 4 more satisfactorily. For example, as shown in FIG. 1, the collector electrode 8 is formed in a linear shape from one end of the photoelectric conversion cell 10 to the connection conductor 7. As a result, the current generated in the first semiconductor layer 3 and the fourth semiconductor layer 4 is collected to the current collecting electrode 8 via the upper electrode layer 5, and to the adjacent photoelectric conversion cell 10 via the connection conductor 7. It is energized well.

集電電極８は、第１の半導体層３への光透過率を高めるとともに良好な導電性を有するという観点から、５０〜４００μｍの幅を有していてもよい。また、集電電極８は、枝分かれした複数の分岐部を有していてもよい。   The collector electrode 8 may have a width of 50 to 400 μm from the viewpoint of increasing the light transmittance to the first semiconductor layer 3 and having good conductivity. The current collecting electrode 8 may have a plurality of branched portions.

集電電極８は、例えば、Ａｇ等の金属粉を樹脂バインダー等に分散させた金属ペーストがパターン状に印刷され、これが硬化されることによって形成される。   The collector electrode 8 is formed, for example, by printing a metal paste in which a metal powder such as Ag is dispersed in a resin binder or the like in a pattern and curing it.

図１〜図３において、接続導体７は、第１の半導体層３、第２の半導体層４、高抵抗層６および上部電極層５を貫通する溝内に設けられた導体である。接続導体７は、金属や導電ペースト等が用いられ得る。図１〜図３においては、集電電極８を延伸して接続導体７が形成されているが、これに限定されない。例えば、上部電極層５が延伸したものであってもよい。   1 to 3, the connection conductor 7 is a conductor provided in a groove that penetrates the first semiconductor layer 3, the second semiconductor layer 4, the high resistance layer 6, and the upper electrode layer 5. The connection conductor 7 can be made of metal, conductive paste, or the like. In FIG. 1 to FIG. 3, the collector electrode 8 is extended to form the connection conductor 7, but the present invention is not limited to this. For example, the upper electrode layer 5 may be stretched.

なお、本発明は上述の実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良などが可能である。   The present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the scope of the present invention.

１：基板
２、２ａ、２ｂ、２ｃ：下部電極層
３：第１の半導体層
４：第２の半導体層
５：上部電極層
６：高抵抗層
７：接続導体
１０：光電変換セル
１１：光電変換装置 1: substrate 2, 2a, 2b, 2c: lower electrode layer 3: first semiconductor layer 4: second semiconductor layer 5: upper electrode layer 6: high resistance layer 7: connection conductor 10: photoelectric conversion cell 11: photoelectric Conversion device

Claims (3)

基板上に下部電極層、第１の半導体層、該第１の半導体層とは異なる導電型の第２の半導体層、高抵抗層および上部電極層が順に積層された光電変換装置であって、
前記高抵抗層は、前記第２の半導体層側から、前記上部電極層よりも電気抵抗率の高い第１の層と、該第１の層よりも電気抵抗率の低い第２の層と、該第２の層および前記上部電極層よりも電気抵抗率の高い第３の層とが順に積層されていることを特徴とする光電変換装置。 A photoelectric conversion device in which a lower electrode layer, a first semiconductor layer, a second semiconductor layer having a conductivity type different from the first semiconductor layer, a high resistance layer, and an upper electrode layer are sequentially stacked on a substrate,
The high resistance layer includes, from the second semiconductor layer side, a first layer having a higher electrical resistivity than the upper electrode layer, a second layer having a lower electrical resistivity than the first layer, The photoelectric conversion device, wherein the second layer and a third layer having a higher electrical resistivity than the upper electrode layer are sequentially stacked. 前記第２の層は前記第１の層および前記第３の層よりも薄いことを特徴とする請求項１に記載の光電変換装置。   The photoelectric conversion device according to claim 1, wherein the second layer is thinner than the first layer and the third layer. 前記第２の半導体層、前記第２の層および前記上部電極層はインジウム元素を含み、前記第１の層および前記第３の層は亜鉛元素を含むことを特徴とする請求項１または２に記載の光電変換装置。   3. The device according to claim 1, wherein the second semiconductor layer, the second layer, and the upper electrode layer contain an indium element, and the first layer and the third layer contain a zinc element. The photoelectric conversion device described.
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