JP2013140935A - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 238000000407 epitaxy Methods 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 32
- 230000005669 field effect Effects 0.000 description 15
- 229910044991 metal oxide Inorganic materials 0.000 description 15
- 150000004706 metal oxides Chemical class 0.000 description 15
- 239000003989 dielectric material Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000012010 growth Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
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Abstract
【解決手段】半導体装置が提供される。装置は、基板、第一および第二エピタキシー、ゲート構造を含む。基板は、第一ドーピング領域とその上の第二ドーピング領域を含む。第一と第二ドーピング領域は、第一導電型を有する。第二ドーピング領域は、少なくとも一つの第一トレンチとそれに隣接する少なくとも一つの第二トレンチを含む。第一エピタキシー層は第一トレンチ内に設置され、第二導電型を有する。第二エピタキシー層は、第二トレンチ内に設置され、第一導電型を有する。第二エピタキシー層は、第二ドーピング領域より高く、第一ドーピング領域より低いドーピング濃度を有する。ゲート構造は、第二トレンチ上に設置される。半導体装置の製造方法も提供される。
【選択図】図2G
Description
100…N型エピタキシードリフト領域
102…P型ベース領域
104…ソース領域
106…ドレイン領域
108…ゲート電極層
110…ゲート電極
112…ソース電極
114…ドレイン電極
20〜半導体装置
200…基板
200a…第一ドーピング領域
200b…第二ドーピング領域
201〜界面
202、210、218…ハードマスク
202a、210a、218a…開口
204…第一トレンチ
206、214、222…絶縁ライナー層
208…第一エピタキシー層
209、217、226…誘電材料層
212…第二トレンチ
216…第二エピタキシー層
216a…延伸部
220…第三トレンチ
224…ドーピング工程
224a…第三ドーピング領域
228…ゲート誘電層
230…ゲート電極
232…ウェル領域
234…ソース領域
A…アクティブ領域
Claims (12)
- 半導体装置であって、
第一ドーピング領域およびその上に位置する第二ドーピング領域を有し、前記第一ドーピング領域及び前記第二ドーピング領域は第一導電型を有し、且つ、前記第二ドーピング領域内に、少なくとも一つの第一トレンチおよびそれと隣接する少なくとも一つの第二トレンチを有する基板と、
前記第一トレンチ内に設置され、且つ、第二導電型を有する第一エピタキシー層と、
前記第二トレンチ内に設置され、且つ、前記第一導電型を有し、前記第二ドーピング領域のドープ濃度より高く、且つ、前記第一ドーピング領域のドープ濃度より低いドープ濃度を有する第二エピタキシー層と、
前記第二トレンチ上方に設置されるゲート構造と、
を備えることを特徴とする半導体装置。 - 前記第二エピタキシー層は、
前記基板上に位置して、前記第二ドーピング領域を被覆する延伸部を含み、
前記延伸部は、
第三トレンチを有して、前記第一エピタキシー層を露出し、且つ、前記第三トレンチの一側壁に隣接する第三ドーピング領域を有し、
前記第三ドーピング領域は、前記第二導電型を有し、
前記第三ドーピング領域のドープ濃度は、
前記第二ドーピング領域のドープ濃度より高く、且つ、前記第一ドーピング領域のドープ濃度より低いことを特徴とする請求項1に記載の半導体装置。 - 前記第二ドーピング領域はエピタキシー層により構成されることを特徴とする請求項1に記載の半導体装置。
- 前記第一トレンチおよび前記第二トレンチは、前記第一ドーピング領域と前記第二ドーピング領域の間の界面を露出することを特徴とする請求項1に記載の半導体装置。
- 前記第一エピタキシー層は、前記第二ドーピング領域のドープ濃度より高く、且つ、前記第一ドーピング領域のドープ濃度より低いドープ濃度を有することを特徴とする請求項1に記載の半導体装置。
- 前記第一エピタキシー層は、前記第一トレンチの側壁および底部上に順応して設置され、且つ、前記第二エピタキシー層は、前記第二トレンチの側壁および底部上に順応して設置されることを特徴とする請求項1に記載の半導体装置。
- 半導体装置の製造方法であって、
第一ドーピング領域及びその上に位置する第二ドーピング領域を有し、前記第一および前記第二ドーピング領域は第一導電型を有する基板を提供する工程と、
前記第二ドーピング領域内に、少なくとも一つの第一トレンチを形成する工程と、
前記第一トレンチ内に、第一エピタキシー層を充填し、前記第一エピタキシー層が第二導電型を有するように形成する工程と、
前記第二ドーピング領域内に、前記第一トレンチと隣接する少なくとも一つの第二トレンチを形成する工程と、
前記第二トレンチ内に、第二エピタキシー層を充填し、前記第二エピタキシー層は第一導電型を有し、且つ、前記第二エピタキシー層は、前記第二ドーピング領域のドープ濃度より高く、且つ、前記第一ドーピング領域のドープ濃度より低いドープ濃度を有するように形成する工程と、
前記第二トレンチ上方にゲート構造を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第二トレンチ内から前記第二エピタキシー層に延伸して、前記基板上に位置し、前記第二ドーピング領域を被覆する工程と、
前記基板上の前記第二エピタキシー層内に、第三トレンチを形成して、前記第一エピタキシー層を露出する工程と、
前記第二エピタキシー層内に、第三ドーピング領域を形成する工程と、
をさらに含み、
前記第三ドーピング領域は前記第三トレンチの一側壁に隣接し、且つ、前記第二導電型を有し、且つ、前記第三ドーピング領域のドープ濃度は前記第二ドーピング領域のドープ濃度より高く、且つ、前記第一ドーピング領域のドープ濃度より低いことを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記第二ドーピング領域はエピタキシー層から構成されることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記第一トレンチおよび前記第二トレンチは、前記第一ドーピング領域と前記第二ドーピング領域の間の界面を露出することを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記第一エピタキシー層は、前記第二ドーピング領域のドープ濃度より高く、前記第一ドーピング領域のドープ濃度より低いドープ濃度を有することを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記第一エピタキシー層は、前記第一トレンチの側壁および底部上に順応して形成され、且つ、前記第二エピタキシー層は、前記第二トレンチの側壁および底部上に順応して形成されることを特徴とする請求項7に記載の半導体装置の製造方法。
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JP5607109B2 (ja) | 2014-10-15 |
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