JP2013120858A - Cu LAYER FORMATION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Google Patents

Cu LAYER FORMATION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Download PDF

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JP2013120858A
JP2013120858A JP2011268331A JP2011268331A JP2013120858A JP 2013120858 A JP2013120858 A JP 2013120858A JP 2011268331 A JP2011268331 A JP 2011268331A JP 2011268331 A JP2011268331 A JP 2011268331A JP 2013120858 A JP2013120858 A JP 2013120858A
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film
substrate
layer
groove
layer forming
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JP5965628B2 (en
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Shinya Nakamura
真也 中村
Junichi Hamaguchi
純一 濱口
Naoki Takeda
直樹 武田
Yuta Sakamoto
勇太 坂本
Yohei Endo
洋平 遠藤
Shuji Kodaira
周司 小平
Hiroaki Iwasawa
宏明 岩澤
Yohei Uchida
洋平 内田
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Ulvac Inc
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Abstract

PROBLEM TO BE SOLVED: To provide a Cu film formation method which can tightly bury conductive materials of Cu inside fine recesses and which is optimal for obtaining wiring excellent in conductivity with high productivity.SOLUTION: A Cu layer formation method of an embodiment in which Cu is buried in recesses 16 formed on a surface of a workpiece 11, comprises: a first step of forming a Cu film 17 on a surface of the workpiece including inner surfaces of the recesses 16; and a second step of burying Cu in the recesses by flowing the Cu film due to a reflow process. In the middle of the second step, Cu atoms and Cu ions are supplied to the surface of the workpiece.

Description

本発明は、Ｃｕ層形成方法及び半導体装置の製造方法に関し、より詳しくは、半導体基板の一方の面に形成された溝部（トレンチ）に効率よく微細なＣｕ配線層を形成するためのものに関する。   The present invention relates to a Cu layer forming method and a semiconductor device manufacturing method, and more particularly to a method for efficiently forming a fine Cu wiring layer in a groove (trench) formed on one surface of a semiconductor substrate.

近年では、融点が高く、しかも、耐マイグレーション性に優れる等の理由から、半導体装置の配線材料として、Ｃｕ（銅）が注目されている。従来、シリコンウエハ等の半導体基板の一方の面に有する絶縁膜中の溝部（トレンチ）内面（内壁面）にバリア膜を形成した後、当該溝部内にスパッタリング法にてＣｕを埋め込み、その後、溝部から上方にはみ出した余分なＣｕを除去してＣｕ配線層を得る方法は、例えば特許文献１で知られている。このものでは、溝部内に隙間無くＣｕを埋め込むことが困難であるという課題がある。つまり、スパッタリング法でＣｕ層を形成すると、溝部内までＣｕが付着して堆積せず、溝部内に、空洞（ボイド）のまま溝部の上側の開口端付近だけにＣｕが堆積してしまう（所謂、オーバーハング）。   In recent years, Cu (copper) has attracted attention as a wiring material for semiconductor devices because of its high melting point and excellent migration resistance. Conventionally, after forming a barrier film on the inner surface (inner wall surface) of a groove (trench) in an insulating film on one surface of a semiconductor substrate such as a silicon wafer, Cu is embedded in the groove by sputtering, and then the groove For example, Patent Document 1 discloses a method of obtaining a Cu wiring layer by removing excess Cu protruding upward from the surface. In this case, there is a problem that it is difficult to embed Cu without a gap in the groove. That is, when a Cu layer is formed by sputtering, Cu does not adhere to and accumulate in the groove, and Cu is deposited only in the vicinity of the opening end on the upper side of the groove with a void (void). ,Overhang).

他方、バリア膜で覆われた溝部内面を覆うようにスパッタリング法にてＣｕを付着、堆積させ、リフロー処理によりこの堆積させたＣｕを流動させて溝部内をＣｕで埋め込み、Ｃｕ配線層を得ることが知られている（例えば、特許文献２参照）。然し、この従来例の方法では、金属または金属化合物からなるバリア膜とＣｕとの濡れ性がよく、かつ、密着性が高いので、リフロー処理時、特にバリア膜側のＣｕが流動し難くなる。結果として、溝部内での流動性が異なることで埋め込み特性が悪化、つまり、トレンチ内部に空洞が生じた状態でＣｕが固化するという不具合が生じる。   On the other hand, Cu is deposited and deposited by a sputtering method so as to cover the inner surface of the trench covered with the barrier film, and the deposited Cu is flowed by reflow treatment to fill the trench with Cu to obtain a Cu wiring layer. Is known (see, for example, Patent Document 2). However, in this conventional method, since the wettability between the barrier film made of a metal or a metal compound and Cu is good and the adhesiveness is high, Cu on the barrier film side is difficult to flow particularly during the reflow process. As a result, the filling characteristics are deteriorated due to the difference in fluidity in the groove, that is, there is a problem that Cu is solidified in a state where a cavity is generated inside the trench.

このように溝部内に形成したＣｕ配線層に空洞が生じていると、銅配線の抵抗値が高くなり、断線の虞がある。そこで、溝部内に空洞が残らないように真空雰囲気内で上記処理を複数回繰り返することが考えられるが、これでは生産性が悪い。しかも、Ｃｕを流動させる際、４００℃以上に加熱することが必要であり、半導体基板に形成した素子が熱でダメージを受ける虞もある。   Thus, if a cavity is formed in the Cu wiring layer formed in the groove, the resistance value of the copper wiring becomes high and there is a risk of disconnection. Therefore, it is conceivable to repeat the above process a plurality of times in a vacuum atmosphere so that no cavity remains in the groove, but this is not productive. In addition, when Cu is flowed, it is necessary to heat to 400 ° C. or higher, and there is a possibility that an element formed on the semiconductor substrate is damaged by heat.

特公平６−１０３６８１号公報Japanese Examined Patent Publication No. 6-103681 特開２００８−７１８５０号公報JP 2008-71850 A

本発明は、以上の点に鑑み、微細な凹部の内部に、隙間無く導電材料たるＣｕを埋め込み形成でき、導電性に優れた配線層を生産性よく得ることに最適なＣｕ膜形成方法及び半導体装置の製造方法を提供することをその課題とするものである。   In view of the above points, the present invention provides a Cu film forming method and a semiconductor that are optimal for obtaining a wiring layer excellent in conductivity with good productivity by being able to embed and form Cu, which is a conductive material, in a minute recess without gaps. It is an object of the present invention to provide a device manufacturing method.

上記課題を解決するために、被処理物の表面に形成された凹部にＣｕを埋め込む本発明のＣｕ層形成方法は、前記凹部の内面を含む被処理物の表面にＣｕ膜を形成する第１工程と、このＣｕ膜をリフロー処理により流動させて凹部内をＣｕで埋め込む第２工程とを含み、前記第２工程の途中で前記Ｃｕ原子及びＣｕイオンの少なくとも一方を基材表面に供給することを特徴とする。   In order to solve the above problems, the Cu layer forming method of the present invention in which Cu is embedded in a recess formed on the surface of the object to be processed is a first method of forming a Cu film on the surface of the object to be processed including the inner surface of the recess. Including a step and a second step of causing the Cu film to flow by reflow treatment and filling the recess with Cu, and supplying at least one of the Cu atoms and Cu ions to the substrate surface during the second step. It is characterized by.

本発明によれば、リフロー処理時、凹部の内面でのＣｕの流動性が異なる場合でも、その途中で前記Ｃｕ原子及びＣｕイオンの少なくとも一方を供給するようにしたため、予め形成された被処理物から流動するＣｕに、Ｃｕ原子またはＣｕイオンが更に付着し、流動するＣｕと共に凹部内へと埋め込まれることで、一度のリフロー処理で、凹部内に空洞が生じることなくＣｕが埋め込まれていく。この場合、前記Ｃｕ原子及びＣｕイオンの少なくとも一方の被処理物表面への供給は、リフロー処理によりＣｕの流動が開始した後であれば、特に制限されないが、Ｃｕの流動開始直後に被処理物表面への供給を開始することが好ましい。これにより、凹部が高アスペクト比のものであっても、上記従来例のものと比較して低い温度で、Ｃｕが凹部の隅々まで空洞を生じることなく行き渡って、凹部に隙間無く導電材料たるＣｕを埋め込み形成でき、その結果、局所的な断線部分のない高精度なＣｕからなる導電体を得ることができる。   According to the present invention, at least one of the Cu atoms and Cu ions is supplied in the middle of reflow treatment even when the flowability of Cu on the inner surface of the recess is different. Cu atoms or Cu ions further adhere to the flowing Cu, and are embedded in the recesses together with the flowing Cu, so that Cu is embedded in the recesses without any cavities in one reflow process. In this case, the supply of at least one of the Cu atoms and the Cu ions to the surface of the object to be processed is not particularly limited as long as the flow of Cu is started by the reflow process, but the object to be processed immediately after the start of the flow of Cu. It is preferable to start the supply to the surface. As a result, even if the recesses have a high aspect ratio, Cu spreads to the corners of the recesses without causing cavities at a lower temperature than that of the conventional example, so that the recesses are conductive materials without gaps. Cu can be embedded and formed, and as a result, a highly accurate conductor made of Cu with no local disconnection portion can be obtained.

本発明において、Ｃｕが凹部の隅々まで空洞を生じることなく確実に行き渡さらせるには、前記前記Ｃｕ原子及びＣｕイオンの少なくとも一方の被処理物表面への供給速度を、前記Ｃｕ層のリフロー処理時の流動速度より遅くすることが好ましい。この場合、流動速度は、リフロー時間と凹部（トレンチ）の深さを考慮して適宜設定され、また、供給速度は、例えば、所定の基板にＣｕ原子またはＣｕイオンを供給して付着、堆積させたときの膜厚と成膜時間から定まるレートを基に決定すればよい。   In the present invention, in order to ensure that Cu spreads to every corner of the recess without causing cavities, the supply rate of the Cu atoms and Cu ions to the surface of the object to be processed is set to the reflow of the Cu layer. It is preferable to make it slower than the flow rate during processing. In this case, the flow rate is appropriately set in consideration of the reflow time and the depth of the recess (trench), and the supply rate is, for example, supplied and deposited by supplying Cu atoms or Cu ions to a predetermined substrate. It may be determined based on the rate determined from the film thickness and the film formation time.

また、本発明において、強い直進性を持ってＣｕ原子またはＣｕイオンを被処理物、ひいては、流動するＣｕに供給するために、前記Ｃｕ原子及びＣｕイオンの少なくとも一方を、Ｃｕをターゲットとするスパッタリング法にて行うことが好ましい。なお、前記第２工程を、１００℃〜３００℃の温度範囲で行えば、Ｃｕが凹部の隅々まで空洞を生じることなく確実に行き渡らせることが確認された。   Further, in the present invention, in order to supply Cu atoms or Cu ions to the object to be processed, and thus flowing Cu, with strong straightness, at least one of the Cu atoms and Cu ions is sputtered using Cu as a target. It is preferable to carry out by the method. In addition, if the said 2nd process was performed in the temperature range of 100 to 300 degreeC, it was confirmed that Cu spreads reliably without producing a cavity to every corner of a recessed part.

また、上記課題を解決するために、請求項１〜４のいずれか１項に記載のＣｕ層形成方法を利用した本発明の半導体装置の製造方法は、被処理物を半導体基板の一方の面側に有する絶縁膜中に形成した溝部とし、この被処理物を真空中で加熱する脱ガス工程と、前記被処理物を水素プラズマに曝して不純物を除去する不純物除去工程と、前記溝部内面にバリア層を形成するバリア層形成工程と、を含み、このバリア層が形成された溝部を凹部とし、上記Ｃｕ層形成方法を実施することを特徴とする。   Moreover, in order to solve the said subject, the manufacturing method of the semiconductor device of this invention using the Cu layer forming method of any one of Claims 1-4 WHEREIN: The to-be-processed object is one side of a semiconductor substrate. A degassing step of heating the object to be processed in vacuum; an impurity removing step of removing the impurity by exposing the object to be treated with hydrogen plasma; and an inner surface of the groove And a barrier layer forming step of forming a barrier layer, wherein the groove portion in which the barrier layer is formed is a recess, and the Cu layer forming method is performed.

これによれば、溝部内に、隙間無くかつ効率よく導電材料たるＣｕが埋め込まれ、導電性に優れた配線層を持つ半導体装置を得ることができる。この場合、バリア膜は、Ｔａ，Ｔｉ，Ｗ，Ｒｕ，Ｖ，Ｃｏ，Ｎｂのうち、少なくとも一種を含む材料からなるものとすればよい。   According to this, Cu, which is a conductive material, can be efficiently embedded in the groove portion without gaps, and a semiconductor device having a wiring layer with excellent conductivity can be obtained. In this case, the barrier film may be made of a material containing at least one of Ta, Ti, W, Ru, V, Co, and Nb.

本発明のＣｕ層形成方法を実施してＣｕ配線層が形成される半導体装置の一例を示す拡大断面図。The expanded sectional view which shows an example of the semiconductor device by which the Cu wiring layer is formed by implementing the Cu layer formation method of this invention. 本発明の半導体装置の製造方法を実施する真空処理装置の構成を模式的に説明する図。The figure which illustrates typically the structure of the vacuum processing apparatus which enforces the manufacturing method of the semiconductor device of this invention. リフロー処理が実施される真空処理室の内部構造を模式的に説明する断面図。Sectional drawing which illustrates typically the internal structure of the vacuum processing chamber in which a reflow process is implemented. 比較実験で得たＣｕ配線層を模式的に示す断面図。Sectional drawing which shows typically the Cu wiring layer obtained by the comparative experiment.

以下、図面を参照して、被処理物を、シリコンウエハ等の半導体基板であってその表面に形成した絶縁膜中に凹部たる溝部（トレンチ）を形成したものとし、この溝部内にＣｕ配線層を形成する場合を例に、本発明の実施形態のＣｕ層形成方法及びこれを利用した半導体装置の製造方法を説明する。   Hereinafter, with reference to the drawings, the object to be processed is a semiconductor substrate such as a silicon wafer, and a groove (trench) as a recess is formed in an insulating film formed on the surface thereof, and a Cu wiring layer is formed in the groove. As an example, a Cu layer forming method according to an embodiment of the present invention and a semiconductor device manufacturing method using the same will be described.

図１を参照して、Ｓは、本発明の実施形態の製造方法を実施してＣｕ層が埋め込み形成される半導体装置である。半導体装置Ｓは、トランジスタ等の素子が形成されたシリコンウエハからなる基板１１の素子形成面側に、例えばＳｉＯ２からなる層間絶縁膜１２を形成した後、基板１１に達する状態の接続孔１３が形成され、接続孔１３内に、例えばタングステンからなる配線層１４が埋め込み形成される。その後、層間絶縁膜１２上に、例えばＳｉＯ２からなる他の層間絶縁膜１５が形成される。そして、層間絶縁膜１５上に図示省略のレジストパターンが形成され、このレジストパターンをマスクとし、ドライエッチングにより層間絶縁膜１５に、配線用の溝部１６が形成される（図１（ａ）参照）。 Referring to FIG. 1, S is a semiconductor device in which a Cu layer is embedded by performing the manufacturing method of the embodiment of the present invention. In the semiconductor device S, after forming an interlayer insulating film 12 made of, for example, SiO 2 on the element forming surface side of the substrate 11 made of a silicon wafer on which elements such as transistors are formed, the connection holes 13 reaching the substrate 11 are formed. A wiring layer 14 made of, for example, tungsten is embedded in the connection hole 13. Thereafter, another interlayer insulating film 15 made of, for example, SiO 2 is formed on the interlayer insulating film 12. Then, a resist pattern (not shown) is formed on the interlayer insulating film 15, and a trench 16 for wiring is formed in the interlayer insulating film 15 by dry etching using this resist pattern as a mask (see FIG. 1A). .

ここで、溝部１６は、その底部の幅Ｗが例えば１０ｎｍ〜４０ｎｍ程度になるように形成され、その深さＤは、例えば８０ｎｍ〜１００ｎｍ程度になるように形成されたものである。そして、このような溝部１６の内部に、例えば半導体素子の配線材料となる導電体たるＣｕが埋め込み形成される。以下に、Ｃｕ層形成方法を具体的に説明する。   Here, the groove 16 is formed so that the width W of the bottom thereof is, for example, about 10 nm to 40 nm, and the depth D thereof is, for example, about 80 nm to 100 nm. Then, for example, Cu, which is a conductor serving as a wiring material of a semiconductor element, is embedded in such a groove 16. Below, the Cu layer formation method is demonstrated concretely.

図２を参照して、２は、Ｃｕ層形成方法を実施する真空処理装置を示している。真空処理装置２は、中央の搬送室２１を備え、搬送室２１には、上記基板１１を搬送する搬送ロボットＲが設置されている。搬送ロボットＲは、回転及び上下動自在な回転軸２２ａと、回転軸２２ａの上端に連結した水平方向に伸縮自在なフロッグレッグ式の一対のロボットアーム２２ｂと、両ロボットアーム２２ｂの先端に取り付けた、基板１１を支持するロボットハンド２２ｃとを備えている。   With reference to FIG. 2, reference numeral 2 denotes a vacuum processing apparatus for performing the Cu layer forming method. The vacuum processing apparatus 2 includes a central transfer chamber 21, and a transfer robot R that transfers the substrate 11 is installed in the transfer chamber 21. The transfer robot R is attached to the tip of both robot arms 22b, a rotary shaft 22a that can rotate and move up and down, a pair of frog-leg-type robot arms 22b that can be expanded and contracted in the horizontal direction. And a robot hand 22c for supporting the substrate 11.

搬送室２１の周囲前側（図２中、下側）には、２つのロードロック室Ｌ１，Ｌ２が左右対称に設けられている。そして、ロードロック室Ｌ１，Ｌ２を起点として反時計まわりに、脱ガス処理を行う第１真空処理室Ｆ１と、水素プラズマを用いたクリーニング処理を行う第２真空処理室Ｆ２と、基板１１を冷却する第３真空処理室Ｆ３と、バリア膜の形成を行う第４真空処理室Ｆ４と、Ｃｕシート層の形成を行う第５真空処理室Ｆ５と、リフロー処理を行う第６真空処理室Ｆ６とが配置されている。これら各ロードロック室Ｌ１，Ｌ２及び各処理室Ｆ１〜Ｆ６には、搬送ロボットＲによりゲートバルブＧＶを介して基板１１が搬入、搬出される。   Two load lock chambers L1 and L2 are provided symmetrically on the front side of the transfer chamber 21 (lower side in FIG. 2). Then, the first vacuum processing chamber F1 that performs degassing processing, the second vacuum processing chamber F2 that performs cleaning processing using hydrogen plasma, and the substrate 11 are cooled counterclockwise starting from the load lock chambers L1 and L2. A third vacuum processing chamber F3 for forming a barrier film, a fifth vacuum processing chamber F5 for forming a Cu sheet layer, and a sixth vacuum processing chamber F6 for performing a reflow process. Has been placed. The substrate 11 is carried into and out of the load lock chambers L1 and L2 and the processing chambers F1 to F6 via the gate valve GV by the transfer robot R.

ここで、第１真空処理室Ｆ１としては、特に図示して説明しないが、基板１１を保持するステージと、基板を所定温度に加熱する赤外線ランプ等を備えたものが利用され、第２真空処理室Ｆ２としては、例えば誘導結合型のプラズマを発生させる機構を備えるものが利用され、第３真空処理室Ｆ３としては、基板が載置されるステージに冷媒循環機構を内蔵して熱交換で基板１１を冷却するものが利用され、これらは、公知のものであるため、ここでは、詳細な説明を省略する。また、バリア膜の形成及びＣｕシード層の形成（第４及び第５の真空処理室）には、公知の構造のマグネトロンスパッタリング装置が利用でき、これらもまた公知のものであるため、ここでは、成膜条件を含め、詳細な説明を省略する。なお、バリア膜の形成及びＣｕシード層の形成方法を上記に限定されるものではなく、蒸着装置やＣＶＤ装置を用いることもできる。   Here, as the first vacuum processing chamber F1, although not particularly illustrated and described, a chamber provided with a stage for holding the substrate 11, an infrared lamp for heating the substrate to a predetermined temperature, and the like is used. As the chamber F2, for example, a chamber having a mechanism for generating inductively coupled plasma is used. As the third vacuum processing chamber F3, a substrate is formed by heat exchange by incorporating a refrigerant circulation mechanism in a stage on which the substrate is placed. Since the thing which cools 11 is utilized and these are well-known things, detailed description is abbreviate | omitted here. In addition, for the formation of the barrier film and the formation of the Cu seed layer (fourth and fifth vacuum processing chambers), a magnetron sputtering apparatus having a known structure can be used, and these are also known, so here, Detailed description including film forming conditions is omitted. The formation method of the barrier film and the formation method of the Cu seed layer is not limited to the above, and a vapor deposition apparatus or a CVD apparatus can also be used.

図３を参照して、３は、本実施形態の第２工程を実施する、第６真空処理室Ｆ６を構成するリフロー装置を示している。リフロー装置３は、第６真空処理室Ｆ６を画成する真空チャンバ３１を備え、その天井部にはカソードユニットが取付けられている。以下においては、図３中、真空チャンバ３１の天井部側を向く方向を「上」とし、その底部側を向く方向を「下」として説明する。   With reference to FIG. 3, 3 shows the reflow apparatus which comprises the 6th vacuum processing chamber F6 which implements the 2nd process of this embodiment. The reflow device 3 includes a vacuum chamber 31 that defines a sixth vacuum processing chamber F6, and a cathode unit is attached to a ceiling portion thereof. In the following, in FIG. 3, the direction facing the ceiling portion side of the vacuum chamber 31 is referred to as “up”, and the direction facing the bottom portion side is described as “down”.

カソードユニットは、ターゲットＴと、このターゲットＴの上方に配置された磁石ユニットＭｇとから構成されている。ターゲットＴは、Ｃｕ製で、基板１１の輪郭より大きな表面積でかつ公知の方法で平面視円形や矩形に形成されたものであり、バッキングプレートＢＰに装着した状態で、そのスパッタ面Ｔ１を下方にして絶縁体Ｉを介して真空チャンバ３１の上部に取り付けられる。また、ターゲットＴは、ＤＣ電源Ｅ１に接続され、Ｃｕ原子やＣｕイオンを供給する際にターゲットＴに負の電位を持った電力が投入される。   The cathode unit is composed of a target T and a magnet unit Mg disposed above the target T. The target T is made of Cu, has a surface area larger than the outline of the substrate 11 and is formed in a circular shape or a rectangular shape in a plan view by a known method, and with the sputter surface T1 facing downward when mounted on the backing plate BP. It is attached to the upper part of the vacuum chamber 31 through the insulator I. Further, the target T is connected to the DC power source E1, and power having a negative potential is supplied to the target T when Cu atoms and Cu ions are supplied.

ターゲットＴの上方に配置される磁石ユニットＭｇは、ターゲットＴのスパッタ面Ｔ１の下方空間に磁場を発生させ、スパッタ時にスパッタ面Ｔ１の下方でのプラズマ密度を高める公知の閉鎖磁場若しくはカスプ磁場構造を有するものであり、ここでは詳細な説明を省略する。なお、磁石ユニットＭｇは、一定のＴ−Ｓ間距離の下、未使用状態のターゲットＴにて、所定条件（圧力、ターゲットＴへの投入電力等）で基板１１に対して成膜したときに、基板１１表面における膜厚分布がその全面に亘って均等になるように設計されている。   The magnet unit Mg disposed above the target T generates a magnetic field in the space below the sputtering surface T1 of the target T, and has a known closed magnetic field or cusp magnetic field structure that increases the plasma density below the sputtering surface T1 during sputtering. The detailed description is omitted here. The magnet unit Mg is formed on the substrate 11 under a predetermined condition (pressure, input power to the target T, etc.) with an unused target T under a certain TS distance. The film thickness distribution on the surface of the substrate 11 is designed to be uniform over the entire surface.

第６真空処理室Ｆ６内には、導電性を有するアノードシールド３２ｄ，３２ｕが配置され、その底部には、ターゲットＴに対向させてステージ３３が絶縁体Ｉを介して設けられている。ステージ３３は、熱伝導のよい金属製の基台３３ａと、その上面に設けられた、正負のチャック電極Ｃｐ，Ｃｐを埋設したセラミックスプレート３３ｂとで構成され、正負のチャック電極Ｃｐ，Ｃｐに図外のチャック電源から所定の電圧を印加することで、セラミックスプレート３３ｂ表面に基板１１が吸着保持される。また、基台３３ａには、抵抗加熱式ヒータ等の加熱手段３４が内蔵され、ステージ３３に吸着された基板１１を所定温度（例えば、１００℃〜３００℃）に加熱保持できるようになっている。なお、特に図示して説明しないが、ステージ３３に高周波電源８を接続し、Ｃｕ原子やＣｕイオンを供給する際に基板１１にバイアス電圧を印加する構造にしてもよい。   Inside the sixth vacuum processing chamber F6, conductive anode shields 32d and 32u are disposed, and a stage 33 is provided on the bottom thereof via the insulator I so as to face the target T. The stage 33 is composed of a metal base 33a having good heat conductivity and a ceramic plate 33b embedded on the upper surface thereof with positive and negative chuck electrodes Cp and Cp embedded in the positive and negative chuck electrodes Cp and Cp. By applying a predetermined voltage from an external chuck power source, the substrate 11 is attracted and held on the surface of the ceramic plate 33b. Further, the base 33a incorporates a heating means 34 such as a resistance heater, so that the substrate 11 adsorbed on the stage 33 can be heated and held at a predetermined temperature (for example, 100 ° C. to 300 ° C.). . Although not specifically illustrated and described, the high frequency power supply 8 may be connected to the stage 33 so that a bias voltage is applied to the substrate 11 when supplying Cu atoms or Cu ions.

真空チャンバ３１の側壁には、所定のガスを導入するガス管３５が接続され、このガス管３５がマスフローコントローラ３５ａを介してガス源３５ｂに連通する。この場合、本実施形態では、アルゴンガスが導入されるようになっているが、窒素やヘリウム等の他の不活性ガスを用いることもできる。真空チャンバ３１の側壁にはまた、ターボ分子ポンプやロータリポンプなどからなる図示省略の真空排気装置に通じる排気管の接続口３６が形成されている。   A gas pipe 35 for introducing a predetermined gas is connected to the side wall of the vacuum chamber 31, and the gas pipe 35 communicates with a gas source 35b through a mass flow controller 35a. In this case, in this embodiment, argon gas is introduced, but other inert gases such as nitrogen and helium can also be used. Also formed on the side wall of the vacuum chamber 31 is an exhaust pipe connection port 36 leading to a vacuum exhaust apparatus (not shown) such as a turbo molecular pump or a rotary pump.

以下に、再び図１及び図２を参照して、本実施形態のＣｕ層形成を具体的に説明する。以下では、基板１１は、上記の如く、半導体装置Ｓとして層間絶縁膜１５中に配線用の溝部１６が形成されたものとし、基板１１は、各処理が施された後のものを指す場合があるものとする。先ず、搬送ロボットＲにより一方のロードロック室Ｌ１から第１真空処理室Ｆ１に未処理の基板１１を搬送し、第１真空処理室Ｆ１で脱ガス処理を施す。この場合、脱ガス処理では、基板１１を１００℃〜２００℃に所定時間（１ｍｉｎ）加熱保持する。そして、脱ガス処理済みの基板１１を第２真空処理室Ｆ２に搬送し、水素プラズマでクリーニング処理を施す。そして、第３真空処理室Ｆ３にクリーニング済みの基板１１を搬送し、基板１１を１００℃以下の温度まで冷却する。   Hereinafter, referring to FIGS. 1 and 2 again, the formation of the Cu layer of the present embodiment will be specifically described. In the following description, it is assumed that the substrate 11 is the semiconductor device S in which the wiring trench 16 is formed in the interlayer insulating film 15 as described above, and the substrate 11 is the one after each processing. It shall be. First, the unprocessed substrate 11 is transferred from one load lock chamber L1 to the first vacuum processing chamber F1 by the transfer robot R, and degassing processing is performed in the first vacuum processing chamber F1. In this case, in the degassing process, the substrate 11 is heated and held at 100 to 200 ° C. for a predetermined time (1 min). Then, the degassed substrate 11 is transferred to the second vacuum processing chamber F2 and subjected to a cleaning process with hydrogen plasma. Then, the cleaned substrate 11 is transferred to the third vacuum processing chamber F3, and the substrate 11 is cooled to a temperature of 100 ° C. or lower.

冷却完了後、第４真空処理室Ｆ４に基板１１を搬送し、溝部１６の内面をその全体に亘って覆うように、スパッタリング法によりバリア層（バリアメタル）１７が形成される（図１（ｂ）参照）。バリア層１７は、例えば、Ｔａ（タンタル）窒化物、Ｔａ珪化物、Ｔａ炭化物、Ｔｉ（チタン）窒化物、Ｔｉ珪化物、Ｔｉ炭化物、Ｗ（タングステン）窒化物、Ｗ珪化物、Ｗ炭化物、Ｒｕ（ルテニウム）、およびＲｕ酸化物、Ｖ（バナジウム）酸化物、Ｃｏ（コバルト）酸化物，Ｎｂ（ニオブ）酸化物などから構成される。この場合、バリア層１７をＴａで構成する場合、その厚みが２ｎｍ〜７ｎｍ程度になるように形成される。   After cooling is completed, the substrate 11 is transferred to the fourth vacuum processing chamber F4, and a barrier layer (barrier metal) 17 is formed by sputtering so as to cover the entire inner surface of the groove 16 (FIG. 1B). )reference). The barrier layer 17 is, for example, Ta (tantalum) nitride, Ta silicide, Ta carbide, Ti (titanium) nitride, Ti silicide, Ti carbide, W (tungsten) nitride, W silicide, W carbide, Ru. (Ruthenium), Ru oxide, V (vanadium) oxide, Co (cobalt) oxide, Nb (niobium) oxide, and the like. In this case, when the barrier layer 17 is made of Ta, the barrier layer 17 is formed to have a thickness of about 2 nm to 7 nm.

バリア層１７が形成されると、第５真空処理室Ｆ５にバリア層１７形成済みの基板１１を搬送し、バリア層１７を覆うように、スパッタリング法によりＣｕ膜（Ｃｕシード層）１８が形成される（図１（ｃ）参照）。この場合、スパッタリングによる成膜中、基板１１を、例えば室温以下の温度、好ましくは−２０℃に保持する。これにより、膜中のグレインサイズが小さいＣｕ膜を形成することができ、また、凝集を抑制できるという利点がある。Ｃｕ膜１８が形成されると、第６真空処理室Ｆ６にＣｕ膜形成済みの基板１１を搬送し、リフロー処理が施される。   When the barrier layer 17 is formed, a Cu film (Cu seed layer) 18 is formed by a sputtering method so that the substrate 11 on which the barrier layer 17 has been formed is transported to the fifth vacuum processing chamber F5 and the barrier layer 17 is covered. (See FIG. 1C). In this case, during film formation by sputtering, the substrate 11 is maintained at a temperature of, for example, room temperature or lower, preferably −20 ° C. Thereby, there is an advantage that a Cu film having a small grain size in the film can be formed and aggregation can be suppressed. When the Cu film 18 is formed, the substrate 11 on which the Cu film has been formed is transferred to the sixth vacuum processing chamber F6 and reflow processing is performed.

第６処理室Ｆ６では、先ず、基板１１をステージ３３上に吸着保持させた後、不活性ガス、好ましくはアルゴンガスを導入し、不活性ガス雰囲気中で加熱手段３４を稼働して基板１１を急速加熱する。この場合、第６真空処理室内の圧力が０．１Ｐａ〜０．２Ｐａの範囲に設定され、また、昇温速度は、２０℃〜４０℃／ｓｅｃの範囲、好ましくは４０℃／ｓｅｃに設定される。この場合、基板温度を１００℃〜３００℃の範囲、好ましくは基板１１の面内平均温度が３００℃となるように設定される。１００℃より低い温度ではＣｕの流動が起きず、また、３００℃より高い温度では、製品（素子）がダメージを受けるという問題が生じる。そして、基板１１が上記温度に達すると、Ｃｕ膜１８が流動し始める。   In the sixth processing chamber F6, first, after the substrate 11 is adsorbed and held on the stage 33, an inert gas, preferably an argon gas, is introduced, and the heating means 34 is operated in an inert gas atmosphere so that the substrate 11 is moved. Heat rapidly. In this case, the pressure in the sixth vacuum processing chamber is set in the range of 0.1 Pa to 0.2 Pa, and the temperature rising rate is set in the range of 20 ° C. to 40 ° C./sec, preferably 40 ° C./sec. The In this case, the substrate temperature is set in a range of 100 ° C. to 300 ° C., preferably the in-plane average temperature of the substrate 11 is 300 ° C. When the temperature is lower than 100 ° C., Cu does not flow, and when the temperature is higher than 300 ° C., the product (element) is damaged. Then, when the substrate 11 reaches the above temperature, the Cu film 18 starts to flow.

Ｃｕ膜１８が流動し始めると、ターゲットＴに所定電力（２ｋＷ〜５ｋＷ）を投入し、既に導入しているアルゴンガスのイオンでターゲットＴをスパッタリングする。これにより、ターゲットＴのスパッタリングで生じたＣｕ原子やＣｕ＋，Ｃｕ２＋といったＣｕイオンが、流動しているＣｕ膜１８に供給される（図１（ｄ）参照）。この場合、ターゲットＴのスパッタリングレートを、Ｃｕ膜の流動速度より低く設定する。基板温度を３００℃に設定する場合、スパッタリングレートは１ｎｍ／ｓｅｃ〜２ｎｍ／ｓｅｃに設定すればよい。これにより、溝部１６内にＣｕが隙間なく埋め込まれ、当該溝部１８内にＣｕ配線層１９が形成される（図１（ｅ）参照）。 When the Cu film 18 starts to flow, a predetermined power (2 kW to 5 kW) is applied to the target T, and the target T is sputtered with argon gas ions already introduced. Thereby, Cu ions such as Cu atoms and Cu + , Cu 2+ generated by sputtering of the target T are supplied to the flowing Cu film 18 (see FIG. 1D). In this case, the sputtering rate of the target T is set lower than the flow rate of the Cu film. When the substrate temperature is set to 300 ° C., the sputtering rate may be set to 1 nm / sec to 2 nm / sec. Thereby, Cu is embedded in the groove portion 16 without a gap, and a Cu wiring layer 19 is formed in the groove portion 18 (see FIG. 1E).

上記実施形態によれば、リフロー処理時、溝部１６の内面でのＣｕの流動性が異なる場合でも、その途中でスパッタリング法にて強い直進性を持ってＣｕ原子またはＣｕイオンを供給するようにしたため、被処理物から流動するＣｕ膜１８に、Ｃｕ原子またはＣｕイオンが更に付着しながら流動するＣｕ膜１８と共に溝部１６内へと埋め込まれることで、一度のリフロー処理で、凹部１６内に空洞が生じることなくＣｕが埋め込まれていく。これにより、溝部１６が高アスペクト比のものであっても、上記従来例のものと比較して低い温度で、Ｃｕが溝部１６の隅々まで空洞を生じることなく行き渡って、溝部１６に隙間無く導電材料たるＣｕを埋め込み形成でき、その結果、局所的な断線部分のない高精度なＣｕ配線層１９が得られ、導電性に優れた配線を持つ半導体装置Ｓとなる。   According to the above embodiment, even when the flowability of Cu on the inner surface of the groove portion 16 is different during the reflow process, Cu atoms or Cu ions are supplied with strong straightness by the sputtering method in the middle. Since the Cu film 18 flowing from the object to be processed is embedded in the groove 16 together with the Cu film 18 flowing while Cu atoms or Cu ions are further adhered, a cavity is formed in the recess 16 by one reflow process. Cu is embedded without being generated. Thereby, even if the groove portion 16 has a high aspect ratio, Cu spreads to the corners of the groove portion 16 without causing any cavities at a lower temperature than that of the conventional example, and there is no gap in the groove portion 16. Cu, which is a conductive material, can be embedded and formed. As a result, a highly accurate Cu wiring layer 19 without a local disconnection portion can be obtained, and the semiconductor device S having wiring with excellent conductivity can be obtained.

ところで、上記のような真空処理装置２を用いる場合、いずれかの真空処理室Ｆ１〜Ｆ６やロードロック室Ｌ１，Ｌ２でプロセス異常や搬送不良が生じた場合、異常のない各真空処理室Ｆ１〜Ｆ６での処理が終了した後、大気開放を適宜行い、復帰操作が行われる。このとき、上記従来の如く、Ｃｕシード層の形成とリフロー処理とを繰り返してＣｕを埋め込み形成するような場合には、最終的にＣｕが埋め込まれた基板１１のみが製品となり得るが、その他の基板１１は製品不良として扱われる。それに対して、上記実施形態では、一度の処理でＣｕの埋め込み形成が行われるので、第６真空処理室Ｆ６でプロセス異常が生じた場合のみ製品不良となるだけであり、製品歩留まりを高める上で有利である。   By the way, when using the vacuum processing apparatus 2 as described above, when a process abnormality or a conveyance failure occurs in any one of the vacuum processing chambers F1 to F6 and the load lock chambers L1 and L2, the vacuum processing chambers F1 to F1 having no abnormality are provided. After the process in F6 is completed, the atmosphere is appropriately released and a return operation is performed. At this time, as in the conventional case, when Cu is embedded and formed by repeating the formation of the Cu seed layer and the reflow process, only the substrate 11 in which Cu is finally embedded can be a product. The substrate 11 is treated as a product defect. On the other hand, in the above-described embodiment, Cu is embedded and formed in a single process, so that only when a process abnormality occurs in the sixth vacuum processing chamber F6, the product is defective, and the product yield is increased. It is advantageous.

次に、上記効果を確認するために次の実験を行った。被処理物を、厚み０．７７５ｍｍのシリコン酸化膜付シリコン基板１１の一方の面に、フォトリソグラフィーによるエッチング加工により、深さ１００ｎｍの溝部をパターニング形成し、当該溝部の内壁面含むシリコン基板１１表面に、スパッタリング法にて厚みの３ｎｍ〜５ｎｍのＴａからなるバリア層１７を形成したものとした。そして、公知のスパッタリング装置を用い、バリア層１７を覆うように厚み１５ｎｍのＣｕからなるＣｕ膜１８を形成した。このとき、シリコン基板１１の温度を−２０℃に制御した。   Next, in order to confirm the above effect, the following experiment was performed. The surface of the silicon substrate 11 including the inner wall surface of the groove is formed by patterning a groove having a depth of 100 nm on one surface of the silicon substrate 11 with a silicon oxide film having a thickness of 0.775 mm by etching using photolithography. In addition, a barrier layer 17 made of Ta having a thickness of 3 nm to 5 nm was formed by a sputtering method. Then, using a known sputtering apparatus, a Cu film 18 made of Cu having a thickness of 15 nm was formed so as to cover the barrier layer 17. At this time, the temperature of the silicon substrate 11 was controlled to −20 ° C.

以上の如く、溝部１６にバリア層１７及びＣｕ膜１８が形成されたシリコン基板１１に対して、上記リフロー装置３を用いてリフロー処理を行った。この場合、真空雰囲気内の第６真空処理室内Ｆ６で、正負の電極Ｃｐ，Ｃｐへの印加電圧を０．６ｋＶに設定してシリコン基板１１をセラミックスプレート３３ｂに吸着し、基板１１の加熱温度を２７５℃に設定して加熱した。この場合、昇温速度を４０℃／ｓｅｃとした。また、加熱開始と共に、第６真空処理室内にアルゴンガスを １５ｓｃｃｍの流量で導入し、圧力を０．１ａとした。そして、基板の加熱開始から基板温度が２７５℃に到達すると、ターゲットに２．５ｋＷの直流電力を投入し、ターゲットＴをスパッタリングすることとした。この場合のスパッタレートは、約１ｎｍ／ｓｅｃであった。そして、スパッタリング開始後、３０ｓｅｃ〜４０ｓｅｃ間、Ｃｕ原子やＣｕイオンを供給しながらシリコン基板１１に対してリフロー処理を施した（発明実験）。   As described above, the reflow process was performed on the silicon substrate 11 in which the barrier layer 17 and the Cu film 18 were formed in the groove 16 using the reflow apparatus 3. In this case, in the sixth vacuum processing chamber F6 in the vacuum atmosphere, the applied voltage to the positive and negative electrodes Cp, Cp is set to 0.6 kV, the silicon substrate 11 is adsorbed to the ceramic plate 33b, and the heating temperature of the substrate 11 is set. Heat was set at 275 ° C. In this case, the temperature rising rate was 40 ° C./sec. Further, at the start of heating, argon gas was introduced into the sixth vacuum processing chamber at a flow rate of 15 sccm, and the pressure was adjusted to 0.1a. When the substrate temperature reached 275 ° C. from the start of heating the substrate, DC power of 2.5 kW was input to the target and the target T was sputtered. In this case, the sputtering rate was about 1 nm / sec. Then, after the start of sputtering, the silicon substrate 11 was subjected to reflow treatment (invention experiment) while supplying Cu atoms and Cu ions for 30 sec to 40 sec.

比較実験として、溝部にバリア層及びＣｕシード層が形成されたシリコン基板に対して、上記リフロー装置を用いてリフロー処理を施した。この場合、基板の加熱温度を４００℃に設定し、リフロー時にＣｕ原子やＣｕイオンの供給は行わず、３０ｓｅｃ〜４０ｓｅｃの間熱処理を施した。   As a comparative experiment, a reflow process was performed on a silicon substrate having a barrier layer and a Cu seed layer formed in a groove using the above reflow apparatus. In this case, the heating temperature of the substrate was set to 400 ° C., and Cu atoms and Cu ions were not supplied during reflow, and heat treatment was performed for 30 sec to 40 sec.

以上の実験により夫々作製したものに対して、走査型電子顕微鏡（ＳＥＭ）を用いて、溝部１６の充填率（溝部がＣｕで充填されている割合、体積％）を確認したところ、比較実験のものは、一度の処理では、その充填率が８０％未満であり、また、ＳＥＭ像を模式的に示す図４の如く、溝部の中央領域にボイド（空洞）Ｖが発生しているものが多いことが確認された。それに対して、発明実験のものでは、一度の処理で、充填率が略１００％になり、ＳＥＭ像で確認すると、図１（ｅ）に示すように、基板全面に亘ってパターニングされた溝部１６にＣｕが埋め込まれていることが確認された。   When the filling rate of the groove portion 16 (ratio in which the groove portion is filled with Cu, volume%) was confirmed using a scanning electron microscope (SEM) for each of the devices manufactured by the above experiments, In the case of a single treatment, the filling rate is less than 80%, and many voids (cavities) V are generated in the central region of the groove as shown in FIG. 4 schematically showing the SEM image. It was confirmed. On the other hand, in the case of the inventive experiment, the filling rate becomes approximately 100% in one process, and when confirmed by the SEM image, as shown in FIG. 1 (e), the groove portion 16 patterned over the entire surface of the substrate. It was confirmed that Cu was embedded in.

以上、本発明の実施形態について説明したが、本発明は上記のものに限定されるものではない。上記実施形態では、半導体基板に形成した溝部にＣｕを埋め込み形成するものを例に説明したが、他の用途にもの本発明は適用できる。また、上記実施形態では、リフロー処理中のＣｕ原子またはＣｕイオンの供給をスパッタリング法を用いるものを例に説明したが、これに限定されるものではなく、蒸着法やＣＶＤ法等の他の方法を用いることができる。   As mentioned above, although embodiment of this invention was described, this invention is not limited to said thing. In the above embodiment, the case where Cu is embedded in a groove formed in a semiconductor substrate has been described as an example, but the present invention can be applied to other uses. In the above embodiment, the supply of Cu atoms or Cu ions during the reflow process has been described as an example using a sputtering method. However, the present invention is not limited to this, and other methods such as an evaporation method and a CVD method are used. Can be used.

Ｓ…半導体装置、１１…基板（被処理物）、１６…溝部（トレンチ：凹部）、１７…バリア層（バリアメタル）、１８…Ｃｕ膜（Ｃｕシード層）、１９…Ｃｕ配線層、３…リフロー装置、３３…ステージ、３４…加熱手段、Ｔ…Ｃｕ製ターゲット。
DESCRIPTION OF SYMBOLS S ... Semiconductor device, 11 ... Board | substrate (to-be-processed object), 16 ... Groove part (trench: recessed part), 17 ... Barrier layer (barrier metal), 18 ... Cu film | membrane (Cu seed layer), 19 ... Cu wiring layer, 3 ... Reflow device, 33 ... stage, 34 ... heating means, T ... target made of Cu.

Claims (6)

被処理物の表面に形成された凹部にＣｕを埋め込み形成するＣｕ層形成方法において、
前記凹部の内面を含む被処理物表面にＣｕ膜を形成する第１工程と、このＣｕ膜をリフロー処理により流動させて凹部内をＣｕで埋め込む第２工程とを含み、
前記第２工程の途中で前記Ｃｕ原子及びＣｕイオンの少なくとも一方を被処理物表面に供給することを特徴とするＣｕ層形成方法。 In a Cu layer forming method in which Cu is embedded in a recess formed on the surface of an object to be processed,
A first step of forming a Cu film on the surface of the object to be processed including the inner surface of the recess, and a second step of causing the Cu film to flow by reflow treatment and filling the recess with Cu.
A Cu layer forming method, wherein at least one of the Cu atoms and Cu ions is supplied to the surface of the workpiece during the second step. 前記Ｃｕ原子及びＣｕイオンの少なくとも一方の被処理物表面への供給速度を、前記Ｃｕ層のリフロー処理時の流動速度より遅くすることを特徴とする請求項１記載のＣｕ層形成方法。   2. The Cu layer forming method according to claim 1, wherein a supply rate of at least one of the Cu atoms and the Cu ions to the surface of the object to be processed is made slower than a flow rate during the reflow process of the Cu layer. 前記Ｃｕ原子及びＣｕイオンの少なくとも一方の被処理物表面への供給を、Ｃｕをターゲットとするスパッタリング法にて行うことを特徴とする請求項１または請求項２記載のＣｕ層形成方法   3. The Cu layer forming method according to claim 1, wherein supply of at least one of the Cu atoms and Cu ions to the surface of the workpiece is performed by a sputtering method using Cu as a target. 前記第２工程を、１００℃〜３００℃の温度範囲で行うことを特徴とする請求項１〜３のいずれか１項に記載のＣｕ層形成方法。   The Cu layer forming method according to any one of claims 1 to 3, wherein the second step is performed in a temperature range of 100C to 300C. 請求項１〜４のいずれか１項に記載のＣｕ層形成方法を利用した半導体装置の製造方法であって、
被処理物を半導体基板の一方の面側に有する絶縁膜中に形成した溝部とし、この被処理物を真空中で加熱する脱ガス工程と、
前記被処理物を水素プラズマに曝して不純物を除去する不純物除去工程と、
前記溝部内面にバリア層を形成するバリア層形成工程と、を含み、
このバリア層が形成された溝部を凹部とし、上記Ｃｕ層形成方法を実施することを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device using the Cu layer forming method according to claim 1,
A degassing step of heating the object to be processed in a vacuum with a groove formed in the insulating film having the object to be processed on one side of the semiconductor substrate;
An impurity removing step of exposing the object to be treated to hydrogen plasma to remove impurities;
A barrier layer forming step of forming a barrier layer on the inner surface of the groove,
A method for manufacturing a semiconductor device, wherein the groove layer in which the barrier layer is formed is a recess, and the Cu layer forming method is carried out. 前記バリア膜は、Ｔａ，Ｔｉ，Ｗ，Ｒｕ，Ｖ，Ｃｏ，Ｎｂのうち、少なくとも一種を含む材料で構成されることを特徴とする請求項５項記載の半導体装置の製造方法。
6. The method of manufacturing a semiconductor device according to claim 5, wherein the barrier film is made of a material containing at least one of Ta, Ti, W, Ru, V, Co, and Nb.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180105706A (en) 2016-07-06 2018-09-28 가부시키가이샤 아루박 Film forming apparatus, flattening ring

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264487A (en) * 1994-12-14 1996-10-11 Applied Materials Inc Accumulation process for coating or filling reentry shape contact hole
JPH11191556A (en) * 1997-12-26 1999-07-13 Sony Corp Manufacture of semiconductor device and forming method of copper or copper alloy pattern
JP2001007050A (en) * 1999-04-19 2001-01-12 Kobe Steel Ltd Formation of wiring film
JP2001007049A (en) * 1999-06-25 2001-01-12 Hitachi Ltd Apparatus and method for manufacturing semiconductor integrated circuit device
JP2003168738A (en) * 2001-11-27 2003-06-13 Hynix Semiconductor Inc Semiconductor element and method of manufacturing it
JP2008192684A (en) * 2007-02-01 2008-08-21 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device
JP2010165989A (en) * 2009-01-19 2010-07-29 Elpida Memory Inc Method of manufacturing semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264487A (en) * 1994-12-14 1996-10-11 Applied Materials Inc Accumulation process for coating or filling reentry shape contact hole
JPH11191556A (en) * 1997-12-26 1999-07-13 Sony Corp Manufacture of semiconductor device and forming method of copper or copper alloy pattern
JP2001007050A (en) * 1999-04-19 2001-01-12 Kobe Steel Ltd Formation of wiring film
JP2001007049A (en) * 1999-06-25 2001-01-12 Hitachi Ltd Apparatus and method for manufacturing semiconductor integrated circuit device
JP2003168738A (en) * 2001-11-27 2003-06-13 Hynix Semiconductor Inc Semiconductor element and method of manufacturing it
JP2008192684A (en) * 2007-02-01 2008-08-21 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device
JP2010165989A (en) * 2009-01-19 2010-07-29 Elpida Memory Inc Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180105706A (en) 2016-07-06 2018-09-28 가부시키가이샤 아루박 Film forming apparatus, flattening ring

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