JP2012526400A - 薄い半導体のためのパネル化裏面処理 - Google Patents
薄い半導体のためのパネル化裏面処理 Download PDFInfo
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- Manufacturing & Machinery (AREA)
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Abstract
Description
120 リモートユニット
130 リモートユニット
150 リモートユニット
140 基地局
125A ICデバイス
125B ICデバイス
125C ICデバイス
180 順方向リンク信号
190 逆方向リンク信号
200 設計ワークステーション
201 ハードディスク
203 ドライブ装置
204 記憶媒体
210 回路/回路設計
212 半導体部品
910 ウエハ
911 パッケージング接続部
912 シリコン貫通ビア
915 ウエハ
921 第1の層ダイ
922 第1の層ダイ
926 基板パネル
927 インターコネクト
931 モールド化合物
941 分離層
946 金属接続部
951 マイクロバンプ
952 第2の層ダイ
953 第2の層ダイ
961 モールド化合物
Claims (18)
- 半導体製造方法であって、
第1のダイを基板パネルに取り付けるステップと、
前記第1のダイを前記基板パネルに取り付けた後に、前記第1のダイおよび前記基板パネルにモールド化合物を適用するステップと、
前記モールド化合物を適用した後に、前記第1のダイおよび前記モールド化合物を薄くするステップと
を含む方法。 - 前記第1のダイを前記基板パネルに取り付ける前に、前記第1のダイを薄くするステップをさらに含む請求項1に記載の方法。
- 前記第1のダイを薄くするステップが、少なくとも1つのシリコン貫通ビアを露出させる、請求項1に記載の方法。
- 薄くするステップの後に、
分離層を前記第1のダイに堆積させるステップと、
前記分離層のインターコネクトをパターニングするステップと、
パッケージング接続部を前記第1のダイに堆積させるステップと
をさらに含む請求項3に記載の方法。 - 前記パッケージング接続部を、前記第1のダイの前記少なくとも1つのシリコン貫通ビアに結合するステップをさらに含む請求項4に記載の方法。
- 第2のダイを前記パッケージング接続部に取り付けるステップをさらに含む請求項5に記載の方法。
- 前記第2のダイに第2のモールド化合物を適用するステップをさらに含む請求項6に記載の方法。
- 前記第1のダイを前記基板パネルに取り付ける前に、ウエハを前記第1のダイにダイシングするステップをさらに含む請求項1に記載の方法。
- 前記第1のダイを、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、通信デバイス、携帯情報端末(PDA)、固定位置データユニット、およびコンピュータからなる群から選択されるデバイスの中に組み込むステップをさらに含む請求項1に記載の方法。
- 前記モールド化合物を適用するステップが、エポキシベースのモールドを適用するステップを含む、請求項1に記載の方法。
- 前記モールド化合物を適用するステップが、モールドチェースをモールド化合物で満たすステップと、前記モールドチェースを前記第1のダイに適用するステップとを含む、請求項1に記載の方法。
- 半導体製造方法であって、
ウエハを第1の層ダイにダイシングするステップと、
前記第1の層ダイを基板パネルに取り付けるステップと、
前記第1の層ダイおよび前記基板パネルに第1のモールド化合物を適用するステップと、
前記第1の層ダイおよび前記第1のモールド化合物を裏面研削するステップと、
第2の層ダイを前記第1の層ダイに取り付けるステップと、
前記第1の層ダイおよび前記第2の層ダイに第2のモールド化合物を適用するステップと
を含む方法。 - 前記ウエハをダイシングする前に、前記ウエハを裏面研削するステップをさらに含む請求項12に記載の方法。
- 基板パネルと、
前記基板パネルに取り付けられた第1のダイと、
前記第1のダイを部分的に取り囲み、前記基板パネルと同一平面上にあるモールド化合物と
を含む半導体デバイス。 - 前記第1のダイに結合された第2のダイをさらに含む請求項14に記載の半導体デバイス。
- 前記第2のダイを部分的に取り囲む第2のモールド化合物をさらに含む請求項15に記載の半導体デバイス。
- 前記モールド化合物および前記第1のダイと同一平面上に堆積された層をさらに含む請求項14に記載の半導体デバイス。
- 集積回路ダイと、
電子処理するための手段を所定の位置に固定するための手段と、
固定するための前記手段および電子処理するための前記手段と同一平面上にある、電子処理するための前記手段をパッケージングするための手段と
を含む半導体デバイス。
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