JP2012256935A - Resin sealing type semiconductor device - Google Patents

Resin sealing type semiconductor device Download PDF

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JP2012256935A
JP2012256935A JP2012190798A JP2012190798A JP2012256935A JP 2012256935 A JP2012256935 A JP 2012256935A JP 2012190798 A JP2012190798 A JP 2012190798A JP 2012190798 A JP2012190798 A JP 2012190798A JP 2012256935 A JP2012256935 A JP 2012256935A
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semiconductor device
semiconductor chip
resin
layer
substrate
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Shoji Yasunaga
尚司 安永
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a resin sealing type semiconductor device which improves heat radiation characteristics and thereby suppressing the deterioration of the reliability.SOLUTION: A BGA type semiconductor device (resin sealing type semiconductor device) includes: a wiring board 1 that a semiconductor chip 10 is mounted on a predetermined region; multiple metal bumps 30 formed in a region of the wiring board 1 which is different from a region where the semiconductor chip 10 is mounted and aligned so as to be spaced a predetermined distance away from each other; and a sealing resin layer 20 covering at least the semiconductor chip 10. Each of the multiple metal bumps 30 is formed so as to be covered by the sealing resin layer 20 and be partially exposed from an upper surface of the sealing resin layer 20.

Description

この発明は、樹脂封止型半導体装置に関し、特に、半導体チップが搭載される基板を備えた樹脂封止型半導体装置に関する。   The present invention relates to a resin-encapsulated semiconductor device, and more particularly to a resin-encapsulated semiconductor device including a substrate on which a semiconductor chip is mounted.

近年、半導体装置の高消費電力化および高集積化に伴い、半導体装置の動作時の発熱量が大きくなってきている。このような動作時における半導体装置の発熱量の増大は、半導体素子の誤動作や寿命低下などの原因となるため、半導体装置においては、放熱特性の向上が強く求められている。   In recent years, with the increase in power consumption and integration of semiconductor devices, the amount of heat generated during operation of the semiconductor devices has increased. An increase in the amount of heat generated by the semiconductor device during such operation causes a malfunction of the semiconductor element or a reduction in the life of the semiconductor device. Therefore, the semiconductor device is strongly required to improve heat dissipation characteristics.

そのため、従来、発生した熱を効率よく放熱することが可能な樹脂封止型半導体装置が知られている（たとえば、特許文献１参照）。   Therefore, conventionally, a resin-encapsulated semiconductor device that can efficiently dissipate generated heat is known (see, for example, Patent Document 1).

上記特許文献１には、樹脂封止型半導体装置の一例であるＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型半導体装置において、パッケージ（封止樹脂層）の上面に放熱用の凹凸形状が形成された半導体装置の構造が開示されている。この従来のＢＧＡ型半導体装置では、放熱用の凹凸形状をパッケージ（封止樹脂層）の上面に形成することによって、パッケージ（封止樹脂層）の表面積を大きくすることが可能となるので、その分、パッケージ（封止樹脂層）表面と空気との接触面積を大きくすることが可能となる。これにより、放熱用の凹凸形状が形成されていな場合に比べて、発生した熱を効率よく放熱することが可能となる。   In Patent Document 1, a BGA (Ball Grid Array) type semiconductor device, which is an example of a resin-encapsulated semiconductor device, includes a semiconductor device in which an uneven shape for heat dissipation is formed on the upper surface of a package (encapsulating resin layer). A structure is disclosed. In this conventional BGA type semiconductor device, it is possible to increase the surface area of the package (encapsulating resin layer) by forming the uneven shape for heat dissipation on the upper surface of the package (encapsulating resin layer). Therefore, the contact area between the surface of the package (sealing resin layer) and air can be increased. Thereby, compared with the case where the uneven | corrugated shape for heat radiation is not formed, it becomes possible to thermally radiate the generated heat efficiently.

特開平１１−２６６５８号公報JP-A-11-26658

しかしながら、上記特許文献１に開示された従来のＢＧＡ型半導体装置では、パッケージ（封止樹脂層）表面に凹凸形状を形成することによって、一定の放熱特性向上の効果は得られるものの、発熱量がより大きな半導体チップが搭載された場合には、半導体チップで発生した熱を十分に放熱することが困難になるという不都合がある。これにより、半導体素子の誤操作や寿命低下などの発生を抑制することが困難となるので、半導体装置の信頼性が低下するという問題点がある。   However, in the conventional BGA type semiconductor device disclosed in the above-mentioned Patent Document 1, by forming an uneven shape on the surface of the package (sealing resin layer), a certain effect of improving the heat dissipation characteristics can be obtained, but the amount of heat generation is small. When a larger semiconductor chip is mounted, there is an inconvenience that it is difficult to sufficiently dissipate the heat generated in the semiconductor chip. As a result, it becomes difficult to suppress the occurrence of erroneous operation of the semiconductor element or a decrease in the life of the semiconductor element, and there is a problem that the reliability of the semiconductor device is lowered.

この発明は、上記のような課題を解決するためになされたものであり、この発明の目的は、放熱特性をより向上させることにより、信頼性の低下を抑制することが可能な樹脂封止型半導体装置を提供することである。   This invention is made in order to solve the above subjects, and the objective of this invention is the resin-sealing type which can suppress the fall of reliability by improving a thermal radiation characteristic more. A semiconductor device is provided.

上記目的を達成するために、この発明の一の局面による樹脂封止型半導体装置は、半導体チップが所定領域上に搭載された基板と、この基板の半導体チップが搭載された領域とは異なる領域に形成され、互いに所定の間隔を隔てて配列された複数の放熱部材と、半導体チップと放熱部材の少なくとも一部とを覆う封止樹脂層とを備えている。   In order to achieve the above object, a resin-encapsulated semiconductor device according to one aspect of the present invention includes a substrate on which a semiconductor chip is mounted on a predetermined region, and a region different from the region on which the semiconductor chip is mounted. And a plurality of heat dissipating members arranged at predetermined intervals, and a sealing resin layer covering the semiconductor chip and at least a part of the heat dissipating member.

この一の局面による樹脂封止型半導体装置では、上記のように、基板における半導体チップが搭載された領域とは異なる領域に、互いに所定の間隔を隔てて配列 された複数の放熱部材を形成することによって、半導体チップで発生した熱を外部に放熱させ易くすることができる。このため、樹脂封止型半導体装置の放熱特性をより向上させることができるので、発熱量がより大きな半導体チップが搭載された場合でも、半導体チップで発生した熱を十分に放熱することができる。これにより、半導体装置の信頼性の低下を抑制することができる。   In the resin-encapsulated semiconductor device according to this one aspect, as described above, a plurality of heat dissipation members arranged at predetermined intervals are formed in a region different from the region where the semiconductor chip is mounted on the substrate. Thus, the heat generated in the semiconductor chip can be easily radiated to the outside. For this reason, since the heat dissipation characteristics of the resin-encapsulated semiconductor device can be further improved, the heat generated in the semiconductor chip can be sufficiently dissipated even when a semiconductor chip with a larger amount of heat generation is mounted. Thereby, a decrease in the reliability of the semiconductor device can be suppressed.

上記一の局面による樹脂封止型半導体装置において、好ましくは、複数の放熱部材の少なくとも一部は、封止樹脂層の上面から一部が露出するように形成されている。このように構成すれば、放熱部材の露出部分を介して、容易に、半導体チップで発生した熱を外部に放熱することができる。   In the resin-encapsulated semiconductor device according to the above aspect, preferably, at least a part of the plurality of heat dissipating members is formed so that a part is exposed from the upper surface of the encapsulating resin layer. If comprised in this way, the heat | fever generate | occur | produced in the semiconductor chip can be easily radiated outside via the exposed part of a heat radiating member.

上記一の局面による樹脂封止型半導体装置において、好ましくは、複数の放熱部材は、それぞれ、金属柱から構成されており、平面視において、半導体チップを 囲むように配列されている。このように構成すれば、より容易に、半導体チップで発生した熱を外部に放熱することができる。   In the resin-encapsulated semiconductor device according to the above aspect, preferably, the plurality of heat dissipation members are each composed of a metal column, and are arranged so as to surround the semiconductor chip in plan view. If comprised in this way, the heat | fever generate | occur | produced with the semiconductor chip can be thermally radiated outside more easily.

上記放熱部材の一部が封止樹脂層の上面から露出された構成において好ましくは、樹脂封止層の上面上に搭載されるヒートシンクをさらに備え、このヒートシンクと放熱部材とは、互いに熱的に接続されている。このように構成すれば、ヒートシンクを介して、半導体チップで発生した熱を効果的に外部に放熱することができる。   In the configuration in which a part of the heat radiating member is exposed from the upper surface of the sealing resin layer, it is preferable to further include a heat sink mounted on the upper surface of the resin sealing layer, and the heat sink and the heat radiating member are thermally connected to each other. It is connected. If comprised in this way, the heat | fever which generate | occur | produced in the semiconductor chip can be effectively thermally radiated outside via a heat sink.

上記放熱部材の一部が封止樹脂層の上面から露出された構成において、基板は、所定の配線パターンに形成された複数の配線層を含む配線基板であり、複数の放熱部材の各々は導電性材料から構成されているとともに、複数の放熱部材の少なくとも一部は、所定の配線層と電気的に接続されていてもよい。   In the configuration in which a part of the heat radiating member is exposed from the upper surface of the sealing resin layer, the substrate is a wiring substrate including a plurality of wiring layers formed in a predetermined wiring pattern, and each of the plurality of heat radiating members is electrically conductive. In addition to being made of a conductive material, at least some of the plurality of heat dissipation members may be electrically connected to a predetermined wiring layer.

上記一の局面による樹脂封止型半導体装置において、半導体チップが封止樹脂層で封止されることによって、樹脂封止型半導体装置をＢＧＡ型のパッケージ形態に構成することができる。   In the resin-encapsulated semiconductor device according to the above aspect, the resin-encapsulated semiconductor device can be configured in a BGA package by sealing the semiconductor chip with an encapsulating resin layer.

以上のように、本発明によれば、放熱特性をより向上させることにより、信頼性の低下を抑制することが可能な樹脂封止型半導体装置を容易に得ることができる。 As described above, according to the present invention, it is possible to easily obtain a resin-encapsulated semiconductor device capable of suppressing a decrease in reliability by further improving heat dissipation characteristics.

本発明の第１実施形態によるＢＧＡ型半導体装置の断面図である。1 is a cross-sectional view of a BGA type semiconductor device according to a first embodiment of the present invention. 本発明の第１実施形態によるＢＧＡ型半導体装置の平面図である。1 is a plan view of a BGA type semiconductor device according to a first embodiment of the present invention. 本発明の第１実施形態によるＢＧＡ型半導体装置の全体斜視図である。1 is an overall perspective view of a BGA type semiconductor device according to a first embodiment of the present invention. 第１実施形態の変形例によるＢＧＡ型半導体装置の平面図である。It is a top view of the BGA type semiconductor device by the modification of 1st Embodiment. 本発明の第２実施形態によるＢＧＡ型半導体装置の断面図である。It is sectional drawing of the BGA type semiconductor device by 2nd Embodiment of this invention. 本発明の第３実施形態によるＢＧＡ型半導体装置の断面図である。It is sectional drawing of the BGA type semiconductor device by 3rd Embodiment of this invention. 本発明の第４実施形態によるＢＧＡ型半導体装置の断面図である。It is sectional drawing of the BGA type semiconductor device by 4th Embodiment of this invention. 本発明の第５実施形態によるＢＧＡ型半導体装置の断面図である。FIG. 7 is a cross-sectional view of a BGA type semiconductor device according to a fifth embodiment of the present invention.

以下、本発明を具体化した実施形態を図面に基づいて詳細に説明する。なお、以下の実施形態では、樹脂封止型半導体装置の一例であるＢＧＡ型半導体装置に本発明を適用した場合について説明する。   DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments embodying the present invention will be described in detail with reference to the drawings. In the following embodiments, a case where the present invention is applied to a BGA type semiconductor device which is an example of a resin-encapsulated semiconductor device will be described.

（第１実施形態）
図１は、本発明の第１実施形態によるＢＧＡ型半導体装置の断面図である。図２は、本発明の第１実施形態によるＢＧＡ型半導体装置の平面図である。図３は、本発明の第１実施形態によるＢＧＡ型半導体装置の全体斜視図である。なお、図１は、図２の１００−１００線に沿った断面を示している。まず、図１〜図３を参照して、本発明の第１実施形態によるＢＧＡ型半導体装置の構造について説明する。 (First embodiment)
FIG. 1 is a cross-sectional view of a BGA type semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view of the BGA type semiconductor device according to the first embodiment of the present invention. FIG. 3 is an overall perspective view of the BGA type semiconductor device according to the first embodiment of the present invention. FIG. 1 shows a cross section taken along line 100-100 in FIG. First, the structure of the BGA type semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

第１実施形態によるＢＧＡ型半導体装置は、図１に示すように、少なくとも、配線基板１と、この配線基板１上に搭載される半導体チップ１０と、配線基板１の上面において半導体チップ１０を覆う封止樹脂層２０とを備えている。なお、配線基板１は、本発明の「基板」の一例である。   As shown in FIG. 1, the BGA type semiconductor device according to the first embodiment covers at least the wiring substrate 1, the semiconductor chip 10 mounted on the wiring substrate 1, and the semiconductor chip 10 on the upper surface of the wiring substrate 1. And a sealing resin layer 20. The wiring board 1 is an example of the “board” in the present invention.

配線基板１は、基材層２の上面上および下面上に、それぞれ、複数の配線層３および４が形成された両面基板から構成されている。この配線基板１の基材層２ は、たとえば、樹脂材料、有機高分子材料またはセラミクス材料などの絶縁性材料から構成されている。また、配線基板１の配線層３および４は、それぞれ、銅などの導電性材料から構成されている。さらに、基材層２の上面上に形成された複数の配線層３は、半導体チップ１０が搭載される搭載部３ａと接続電極層３ｂとを含んでおり、基材層２の下面上に形成された複数の配線層４は、接続電極層４ａを含んでいる。なお、配線基板１の配線層３および４は、それぞれ、所定のパターン形状に形成されている。   The wiring board 1 is composed of a double-sided board in which a plurality of wiring layers 3 and 4 are formed on the upper surface and the lower surface of the base material layer 2, respectively. The base material layer 2 of the wiring board 1 is made of, for example, an insulating material such as a resin material, an organic polymer material, or a ceramic material. The wiring layers 3 and 4 of the wiring board 1 are each made of a conductive material such as copper. Further, the plurality of wiring layers 3 formed on the upper surface of the base material layer 2 includes a mounting portion 3a on which the semiconductor chip 10 is mounted and a connection electrode layer 3b, and is formed on the lower surface of the base material layer 2. The plurality of wiring layers 4 include connection electrode layers 4a. The wiring layers 3 and 4 of the wiring board 1 are each formed in a predetermined pattern shape.

また、配線基板１（基材層２）には、上面から下面まで厚み方向に貫通する複数のスルーホール５が形成されている。このスルーホール５には、たとえば、金属 材料などからなるプラグ５ａが埋め込まれている。そして、上記したスルーホール５（プラグ５ａ）を介して、配線基板１の上面側の接続電極層３ｂと配線基板１の下面側の接続電極層４ａとが、互いに電気的に接続されている。なお、スルーホール５にプラグ５ａを埋め込む代わりに、スルーホール５の側壁に導体層を 形成してもよい。あるいは、スルーホール５の側壁に導体層を形成した後、スルーホール５の穴埋め処理を行ってもよい。   The wiring substrate 1 (base material layer 2) is formed with a plurality of through holes 5 penetrating in the thickness direction from the upper surface to the lower surface. In the through hole 5, a plug 5a made of, for example, a metal material is embedded. The connection electrode layer 3b on the upper surface side of the wiring board 1 and the connection electrode layer 4a on the lower surface side of the wiring board 1 are electrically connected to each other through the through hole 5 (plug 5a). Instead of embedding the plug 5 a in the through hole 5, a conductor layer may be formed on the side wall of the through hole 5. Alternatively, after the conductor layer is formed on the side wall of the through hole 5, the filling process of the through hole 5 may be performed.

半導体チップ１０は、たとえば、シリコン基板の一方主面（上面）に図示しない集積回路などが形成された構造を有している。この半導体チップ１０は、一方主 面（集積回路などが形成されている面）が上側（配線基板１と反対側）となるように配置された状態で、ハンダなどからなる接着層１１を介して、配線基板１の搭載部３ａ上に固定されている。そして、半導体チップ１０は、金細線などからなるボンディングワイヤ１２を介して、配線基板１の上面側の接続電極層３ｂと電気的に接続されている。   The semiconductor chip 10 has a structure in which, for example, an unillustrated integrated circuit is formed on one main surface (upper surface) of a silicon substrate. The semiconductor chip 10 is arranged with an adhesive layer 11 made of solder or the like in a state where one main surface (surface on which an integrated circuit or the like is formed) is on the upper side (opposite side of the wiring substrate 1). The wiring board 1 is fixed on the mounting portion 3a. The semiconductor chip 10 is electrically connected to the connection electrode layer 3b on the upper surface side of the wiring substrate 1 via bonding wires 12 made of fine gold wires or the like.

また、図１および図３に示すように、配線基板１の下面上には、外部端子として機能する半田ボール６が複数設けられている。この半田ボール６は、図１に示すように、配線基板１の下面側の接続電極層４ａ上に形成されている。すなわち、半田ボール６は、スルーホール５などを介して半導体チップ１０と電気的に接続されている。   As shown in FIGS. 1 and 3, a plurality of solder balls 6 functioning as external terminals are provided on the lower surface of the wiring board 1. As shown in FIG. 1, the solder balls 6 are formed on the connection electrode layer 4 a on the lower surface side of the wiring board 1. That is, the solder ball 6 is electrically connected to the semiconductor chip 10 through the through hole 5 or the like.

封止樹脂層２０は、たとえば、エポキシ樹脂などの熱硬化性樹脂から構成されており、半導体チップ１０やボンディングワイヤ１２などを樹脂封止するように、配線基板１の上面上に形成されている。この封止樹脂層２０は、半導体チップ１０やボンディングワイヤ１２などを樹脂封止することによって、ガスや水分などから半導体チップ１０やボンディングワイヤ１２などを保護する機能を有している。   The sealing resin layer 20 is made of, for example, a thermosetting resin such as an epoxy resin, and is formed on the upper surface of the wiring substrate 1 so as to resin-seal the semiconductor chip 10 and the bonding wires 12. . The sealing resin layer 20 has a function of protecting the semiconductor chip 10, the bonding wire 12, and the like from gas, moisture, and the like by resin-sealing the semiconductor chip 10, the bonding wire 12, and the like.

ここで、第１実施形態では、配線基板１上の所定領域（半導体チップ１０が搭載された領域とは異なる領域）に、銅からなる複数の金属バンプ３０が形成されている。この複数の金属バンプ３０は、図１および図２に示すように、半導体チップ１０を囲むように、互いに所定の間隔を隔てて配列されている。なお、金属バンプ３０は、本発明の「放熱部材」および「金属柱」の一例である。   Here, in the first embodiment, a plurality of metal bumps 30 made of copper are formed in a predetermined region on the wiring substrate 1 (a region different from the region where the semiconductor chip 10 is mounted). As shown in FIGS. 1 and 2, the plurality of metal bumps 30 are arranged at predetermined intervals so as to surround the semiconductor chip 10. The metal bump 30 is an example of the “heat dissipating member” and the “metal pillar” in the present invention.

また、第１実施形態では、図１〜図３に示すように、複数の金属バンプ３０の各々は、上記した封止樹脂層２０によって覆われている一方、その一部が封止樹脂層２０の上面から露出している。このような構成は、たとえば、金属バンプ３０を封止樹脂層２０で封止した後、封止樹脂層２０の上面を研磨等により所定量だけ除去することによって得られる。なお、この場合には、封止樹脂層２０の上面と金属バンプ３０の露出面とは同一面となる。   In the first embodiment, as shown in FIGS. 1 to 3, each of the plurality of metal bumps 30 is covered with the above-described sealing resin layer 20, while a part thereof is the sealing resin layer 20. It is exposed from the top surface. Such a configuration can be obtained, for example, by sealing the metal bump 30 with the sealing resin layer 20 and then removing the upper surface of the sealing resin layer 20 by a predetermined amount by polishing or the like. In this case, the upper surface of the sealing resin layer 20 and the exposed surface of the metal bump 30 are the same surface.

第１実施形態では、上記のように、配線基板１上の所定領域に、互いに所定の間隔を隔てて配列された複数の金属バンプ３０を設けることによって、半導体チップ１０で発生した熱を外部に放熱させ易くすることができる。このため、ＢＧＡ型半導体装置の放熱特性をより向上させることができるので、半導体チップ１０の発熱量が大きい場合でも、半導体チップ１０で発生した熱を十分に放熱することができる。これにより、ＢＧＡ型半導体装置の信頼性の低下を抑制することができる。   In the first embodiment, as described above, the heat generated in the semiconductor chip 10 is externally provided by providing the plurality of metal bumps 30 arranged at predetermined intervals in a predetermined region on the wiring board 1. Heat dissipation can be facilitated. For this reason, since the heat dissipation characteristics of the BGA type semiconductor device can be further improved, even when the heat generation amount of the semiconductor chip 10 is large, the heat generated in the semiconductor chip 10 can be sufficiently dissipated. Thereby, the fall of the reliability of a BGA type semiconductor device can be suppressed.

また、第１実施形態では、複数の金属バンプ３０の各々を、封止樹脂層２０の上面から一部が露出するように設けることによって、金属バンプ３０の露出部分を介して、容易に、半導体チップ１０で発生した熱を外部に放熱することができる。   Further, in the first embodiment, by providing each of the plurality of metal bumps 30 so that a part is exposed from the upper surface of the sealing resin layer 20, the semiconductor can be easily formed via the exposed portion of the metal bump 30. The heat generated in the chip 10 can be radiated to the outside.

図４は、第１実施形態の変形例によるＢＧＡ型半導体装置の平面図である。図１および図４を参照して、第１実施形態の変形例によるＢＧＡ型半導体装置では、基材層２（図１参照）の上面上に形成された複数の配線層３は、放熱用の導体層３ｃと、この放熱用の導体層３ｃと半導体チップ１０が搭載される搭載部３ａとを熱的に接続するための４つの接続部３ｄとをさらに含んでいる。   FIG. 4 is a plan view of a BGA type semiconductor device according to a modification of the first embodiment. With reference to FIGS. 1 and 4, in the BGA type semiconductor device according to the modification of the first embodiment, the plurality of wiring layers 3 formed on the upper surface of the base material layer 2 (see FIG. 1) It further includes a conductor layer 3c and four connection portions 3d for thermally connecting the heat radiation conductor layer 3c and the mounting portion 3a on which the semiconductor chip 10 is mounted.

放熱用の導体層３ｃは、配線基板１の外周部近傍の領域に、平面視において半導体チップ１０およびボンディングワイヤ１２を囲むように枠状に形成されている。また、４つの接続部３ｄは、搭載部３ａの４つの角部の各々に１つずつ配置されており、平面視において、放射状に広がるように形成されている。なお、放熱用の導体層３ｃ、４つの接続部３ｄおよび搭載部３ａは、一体的に連結されている。また、ボンディングワイヤ１２を介して半導体チップ１０と電気的に接続される接続電極層３ｂ（図１参照）は、搭載部３ａ、導体層３ｃおよび接続部３ｄに囲まれた領域１３にそれぞれ形成されている。また、放熱用の導体層３ｃの上面上には、上記した金属バンプ３０が形成されている。   The heat-dissipating conductor layer 3c is formed in a frame shape so as to surround the semiconductor chip 10 and the bonding wire 12 in a plan view in a region near the outer peripheral portion of the wiring substrate 1. The four connecting portions 3d are arranged one by one at each of the four corners of the mounting portion 3a, and are formed so as to spread radially in plan view. The heat-dissipating conductor layer 3c, the four connecting portions 3d, and the mounting portion 3a are integrally connected. The connection electrode layer 3b (see FIG. 1) that is electrically connected to the semiconductor chip 10 via the bonding wires 12 is formed in a region 13 surrounded by the mounting portion 3a, the conductor layer 3c, and the connection portion 3d, respectively. ing. Further, the above-described metal bumps 30 are formed on the upper surface of the heat-dissipating conductor layer 3c.

なお、第１実施形態の変形例のその他の構成は、上記第１実施形態と同様である。   The remaining configuration of the modification of the first embodiment is the same as that of the first embodiment.

第１実施形態の変形例では、上記のように、放熱用の導体層３ｃ上に複数の金属バンプ３０を形成するとともに、この放熱用の導体層３ｃと半導体チップ１０が 搭載される搭載部３ａとを接続部３ｄを介して熱的に接続することによって、半導体チップ１０で発生した熱を容易に金属バンプ３０に伝達させることができる ので、容易に、複数の金属バンプ３０を介して、半導体チップ１０で発生した熱を外部に放熱することができる。   In the modification of the first embodiment, as described above, a plurality of metal bumps 30 are formed on the heat-dissipating conductor layer 3c, and the heat-dissipating conductor layer 3c and the semiconductor chip 10 are mounted. Are thermally connected to each other through the connection portion 3d, so that the heat generated in the semiconductor chip 10 can be easily transferred to the metal bumps 30. The heat generated in the chip 10 can be radiated to the outside.

なお、第１実施形態の変形例のその他の効果は、上記第１実施形態と同様である。   The remaining effects of the modification of the first embodiment are similar to those of the aforementioned first embodiment.

（第２実施形態）
図５は、本発明の第２実施形態によるＢＧＡ型半導体装置の断面図である。次に、図５を参照して、この第２実施形態によるＢＧＡ型半導体装置では、上記した第１実施形態によるＢＧＡ型半導体装置において、さらに、ヒートシンク４０を備えている。このヒートシンク４０はアルミニウムなどの熱伝導性の優れた金属材料から構成されており、複数の放熱フィン４１を有している。そして、ヒートシンク ４０は、複数の金属バンプ３０の各々と熱的に接続された状態で、封止樹脂層２０の上面上に固定されている。 (Second Embodiment)
FIG. 5 is a cross-sectional view of a BGA type semiconductor device according to a second embodiment of the present invention. Next, referring to FIG. 5, the BGA type semiconductor device according to the second embodiment further includes a heat sink 40 in the BGA type semiconductor device according to the first embodiment. The heat sink 40 is made of a metal material having excellent thermal conductivity such as aluminum and has a plurality of heat radiation fins 41. The heat sink 40 is fixed on the upper surface of the sealing resin layer 20 while being thermally connected to each of the plurality of metal bumps 30.

なお、第２実施形態のその他の構成は、上記第１実施形態と同様である。   In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment.

第２実施形態では、上記のように、封止樹脂層２０の上面上に、金属バンプ３０と熱的に接続されたヒートシンク４０を備えることによって、このヒートシンク４０を介して、半導体チップ１０で発生した熱を効果的に外部に放熱することができる。   In the second embodiment, as described above, the heat sink 40 that is thermally connected to the metal bump 30 is provided on the upper surface of the sealing resin layer 20, and thus generated in the semiconductor chip 10 via the heat sink 40. Heat can be effectively dissipated to the outside.

なお、第２実施形態のその他の効果は、上記第１実施形態と同様である。   The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

（第３実施形態）
図６は、本発明の第３実施形態によるＢＧＡ型半導体装置の断面図である。次に、図６を参照して、この第３実施形態によるＢＧＡ型半導体装置では、複数の金属バンプ３０の少なくとも一部が、所定の接続電極層３ｂと電気的に接続するように形成されている。これにより、接続電極層３ｂと電気的に接続された金属バンプ３０を電気配線として機能させることができる。 (Third embodiment)
FIG. 6 is a cross-sectional view of a BGA type semiconductor device according to a third embodiment of the present invention. Next, referring to FIG. 6, in the BGA type semiconductor device according to the third embodiment, at least some of the plurality of metal bumps 30 are formed so as to be electrically connected to a predetermined connection electrode layer 3b. Yes. Thereby, the metal bump 30 electrically connected to the connection electrode layer 3b can function as an electrical wiring.

上記のように構成された第３実施形態によるＢＧＡ型半導体装置では、ＢＧＡ型半導体装置上に他の半導体装置５０を搭載することによってパッケージオンパッケージ（ＰｏＰ）構造に構成した際に、上側の半導体装置５０を下側のＢＧＡ型半導体装置に容易に電気的に接続することができる。そして、上側に配置された半導体装置５０に放熱対策が施されている場合には、ＢＧＡ型半導体装置からの熱を、半導体装置５０から放熱することが可能となる。   In the BGA type semiconductor device according to the third embodiment configured as described above, when the semiconductor device 50 is mounted on the BGA type semiconductor device to form a package on package (PoP) structure, the upper semiconductor The device 50 can be easily electrically connected to the lower BGA type semiconductor device. If the semiconductor device 50 disposed on the upper side is provided with a heat dissipation measure, the heat from the BGA type semiconductor device can be radiated from the semiconductor device 50.

なお、第３実施形態のその他の構成および効果は、上記第１実施形態と同様である。   The other configurations and effects of the third embodiment are the same as those of the first embodiment.

（第４実施形態）
図７は、本発明の第４実施形態によるＢＧＡ型半導体装置の断面図である。続いて、図１および図７を参照して、この第４実施形態によるＢＧＡ型半導体装置では、上記第１〜第３実施形態と異なり、配線基板１には、金属バンプ３０（図１参照）に代えて金属ピン１３０（図７参照）が設けられている。なお、金属ピン１３０は、本発明の「放熱部材」および「金属柱」の一例である。この金属ピン１３０は、熱伝導性の優れた銅から構成されており、半導体チップ１０の厚み方向に伸びるように、配線基板１に固定されている。具体的には、配線基板１の所定領域に、上面から厚み方向に所定の深さを有する凹部２ａが複数形成されており、この複数の凹部２ａの各々に、上記した金属ピン１３０が挿入されている。 (Fourth embodiment)
FIG. 7 is a cross-sectional view of a BGA type semiconductor device according to a fourth embodiment of the present invention. Subsequently, referring to FIG. 1 and FIG. 7, in the BGA type semiconductor device according to the fourth embodiment, unlike the first to third embodiments, the wiring board 1 has a metal bump 30 (see FIG. 1). Instead, a metal pin 130 (see FIG. 7) is provided. The metal pin 130 is an example of the “heat dissipating member” and the “metal pillar” in the present invention. The metal pin 130 is made of copper having excellent thermal conductivity, and is fixed to the wiring board 1 so as to extend in the thickness direction of the semiconductor chip 10. Specifically, a plurality of recesses 2a having a predetermined depth in the thickness direction from the upper surface are formed in a predetermined region of the wiring board 1, and the metal pin 130 is inserted into each of the plurality of recesses 2a. ing.

第４実施形態では、上記のように、配線基板１に複数の金属ピン１３０を設けることによって、上記した第１〜第３実施形態と同様、半導体チップ１０で発生した熱を外部に放熱させ易くすることができる。   In the fourth embodiment, by providing the plurality of metal pins 130 on the wiring board 1 as described above, it is easy to dissipate the heat generated in the semiconductor chip 10 to the outside as in the first to third embodiments. can do.

また、第４実施形態では、配線基板１に複数の金属ピン１３０を設けることによって、放熱特性向上の効果に加えて、半導体チップ１０の反りを抑制する効果も得られる。   In the fourth embodiment, by providing the plurality of metal pins 130 on the wiring board 1, the effect of suppressing warpage of the semiconductor chip 10 can be obtained in addition to the effect of improving the heat dissipation characteristics.

第４実施形態のその他の構成は、上記第１、第２または第３実施形態と同様である。また、第４実施形態の効果は、上記第１実施形態と同様である。   Other configurations of the fourth embodiment are the same as those of the first, second, or third embodiment. The effect of the fourth embodiment is the same as that of the first embodiment.

（第５実施形態）
図８は、本発明の第５実施形態によるＢＧＡ型半導体装置の断面図である。続いて、図８を参照して、本発明の第５実施形態によるＢＧＡ型半導体装置の構造について説明する。 (Fifth embodiment)
FIG. 8 is a cross-sectional view of a BGA type semiconductor device according to a fifth embodiment of the present invention. Subsequently, the structure of the BGA type semiconductor device according to the fifth embodiment of the present invention will be described with reference to FIG.

この第５実施形態によるＢＧＡ型半導体装置では、上記第１〜第４実施形態と異なり、配線基板１０１が多層基板から構成されている。具体的には、配線基板１０１は、基材層１０２が複数積層された構造を有している。この基材層１０２の上面上および下面上には、それぞれ、配線層３または配線層４が形成されている。なお、基材層１０２は、たとえば、樹脂材料、有機高分子材料またはセラミクス材料などの絶縁性材料から構成されている。また、配線基板１０１（基材層１０２）の配線層３および４は、それぞれ、銅などの導電性材料から構成されている。さらに、配線基板１０１（基材層１０２）の配線層３は、配線基板１０１の上面に形成されるとともに半導体チップ１０が搭載される搭載部３ａと、同じく上面に形成された接続電極層３ｂと、内層側に形成された内層配線層３ｃとを含んでいる。一方、配線基板１０１（基材層１０２）の配線層４は、配線基板１０１の下面に形成された接続電極層４ａを含んでいる。なお、配線基板１０１は、本発明の「基板」の一例である。   In the BGA type semiconductor device according to the fifth embodiment, unlike the first to fourth embodiments, the wiring board 101 is composed of a multilayer board. Specifically, the wiring substrate 101 has a structure in which a plurality of base material layers 102 are stacked. The wiring layer 3 or the wiring layer 4 is formed on the upper surface and the lower surface of the base material layer 102, respectively. The base material layer 102 is made of, for example, an insulating material such as a resin material, an organic polymer material, or a ceramic material. The wiring layers 3 and 4 of the wiring substrate 101 (base material layer 102) are each made of a conductive material such as copper. Further, the wiring layer 3 of the wiring substrate 101 (base material layer 102) is formed on the upper surface of the wiring substrate 101, and the mounting portion 3a on which the semiconductor chip 10 is mounted, and the connection electrode layer 3b also formed on the upper surface. And an inner wiring layer 3c formed on the inner layer side. On the other hand, the wiring layer 4 of the wiring substrate 101 (base material layer 102) includes a connection electrode layer 4 a formed on the lower surface of the wiring substrate 101. The wiring substrate 101 is an example of the “substrate” in the present invention.

また、配線基板１０１（基材層１０２）の所定部分には、上層側の配線層と下層側の配線層とを電気的に接続するためのスルーホール（ヴィアホール）５が形成されている。このスルーホール（ヴィアホール）５には、たとえば、金属材料などからなるプラグ５ａが埋め込まれている。なお、スルーホール（ヴィアホール）５にプラグ５ａを埋め込む代わりに、スルーホール５の側壁に導体層を形成してもよい。あるいは、スルーホール（ヴィアホール）５の側壁に導体層を形成した後、スルーホール（ヴィアホール）５の穴埋め処理を行ってもよい。   A through hole (via hole) 5 for electrically connecting the upper wiring layer and the lower wiring layer is formed in a predetermined portion of the wiring substrate 101 (base material layer 102). In the through hole (via hole) 5, for example, a plug 5a made of a metal material or the like is embedded. Instead of embedding the plug 5 a in the through hole (via hole) 5, a conductor layer may be formed on the side wall of the through hole 5. Alternatively, after the conductor layer is formed on the side wall of the through hole (via hole) 5, the through hole (via hole) 5 may be filled.

また、第５実施形態では、上記第４実施形態と同様、配線基板１０１には、複数の金属ピン１３０が設けられている。この金属ピン１３０は、熱伝導性の優れた銅から構成されており、半導体チップ１０の厚み方向に伸びるように、配線基板１０１に固定されている。具体的には、配線基板１０１の所定領域に、上面から厚み方向に所定の深さを有する凹部１０２ａが複数形成されており、この複数の凹部１０２ａの各々に、上記した金属ピン１３０が挿入されている。   In the fifth embodiment, the wiring board 101 is provided with a plurality of metal pins 130 as in the fourth embodiment. The metal pin 130 is made of copper having excellent thermal conductivity, and is fixed to the wiring board 101 so as to extend in the thickness direction of the semiconductor chip 10. Specifically, a plurality of recesses 102a having a predetermined depth in the thickness direction from the upper surface are formed in a predetermined region of the wiring board 101, and the metal pin 130 is inserted into each of the plurality of recesses 102a. ing.

ここで、第５実施形態では、複数の凹部１０２ａの少なくとも一部が内層配線層３ｃに対応する領域に形成されている。また、これらの凹部１０２ａは、内層配線層３ｃに達する深さに構成されている。これにより、内層配線層３ｃに対応する領域に形成された凹部１０２ａに挿入された金属ピン１３０は、配線基板１０１の内層配線層３ｃと電気的に接続された状態となっている。すなわち、複数の凹部１０２ａの各々に挿入された複数の金属ピン１３０の少なくとも一部は、配線基板１０１の内層配線層３ｃと電気的に接続された状態となっている。   Here, in the fifth embodiment, at least a part of the plurality of recesses 102a is formed in a region corresponding to the inner wiring layer 3c. These recesses 102a are formed to a depth reaching the inner wiring layer 3c. Thereby, the metal pin 130 inserted into the recess 102 a formed in the region corresponding to the inner wiring layer 3 c is in a state of being electrically connected to the inner wiring layer 3 c of the wiring board 101. That is, at least a part of the plurality of metal pins 130 inserted into each of the plurality of recesses 102 a is in a state of being electrically connected to the inner wiring layer 3 c of the wiring board 101.

上記のように構成された第５実施形態によるＢＧＡ型半導体装置では、複数の金属ピン１３０の少なくとも一部を、内層配線層３ｃと電気的に接続された状態にすることによって、内層配線層３ｃと電気的に接続された金属ピン１３０を電気配線として機能させることができる。   In the BGA type semiconductor device according to the fifth embodiment configured as described above, at least a part of the plurality of metal pins 130 is electrically connected to the inner wiring layer 3c, whereby the inner wiring layer 3c. The metal pins 130 electrically connected to each other can function as electrical wiring.

第５実施形態のその他の構成は、上記第４実施形態と同様である。また、第５実施形態のその他の効果は、上記第１〜第４実施形態と同様である。   Other configurations of the fifth embodiment are the same as those of the fourth embodiment. The remaining effects of the fifth embodiment are similar to those of the aforementioned first to fourth embodiments.

なお、今回開示された実施形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施形態の説明ではなく特許請求の範囲によって示され、さらに特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれる。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

たとえば、上記第１〜第５実施形態では、樹脂封止型半導体装置の一例であるＢＧＡ型半導体装置に本発明を適用した例を示したが、本発明はこれに限らず、ＢＧＡ型半導体装置以外の樹脂封止型半導体装置に本発明を適用してもよい。   For example, in the first to fifth embodiments, the example in which the present invention is applied to the BGA type semiconductor device which is an example of the resin-encapsulated semiconductor device has been described. However, the present invention is not limited thereto, and the BGA type semiconductor device is not limited thereto. The present invention may be applied to other resin-encapsulated semiconductor devices.

また、上記第１〜第５実施形態では、放熱部材（金属バンプ、金属ピン）の一部が封止樹脂層の上面から露出するように構成した例を示したが、本発明はこれに限らず、放熱部材（金属バンプ、金属ピン）の一部が封止樹脂層から露出しない構成にしてもよい。また、封止樹脂層の上面から露出するように構成される放熱部材は、複数の放熱部材のうちの一部であってもよい。   Moreover, although the said 1st-5th embodiment showed the example comprised so that a part of heat radiating member (metal bump, metal pin) might be exposed from the upper surface of a sealing resin layer, this invention is not limited to this. Alternatively, a part of the heat dissipation member (metal bump, metal pin) may not be exposed from the sealing resin layer. Further, the heat radiating member configured to be exposed from the upper surface of the sealing resin layer may be a part of the plurality of heat radiating members.

また、上記第１〜第５実施形態では、平面視において、半導体チップを囲むように複数の放熱部材（金属バンプ、金属ピン）を配置（配列）した例について示したが、本発明はこれに限らず、複数の放熱部材（金属バンプ、金属ピン）は、上記（第１〜第５実施形態）とは異なる配置（配列）となるように構成してもよい。   In the first to fifth embodiments, the example in which a plurality of heat dissipating members (metal bumps, metal pins) are arranged (arranged) so as to surround the semiconductor chip in a plan view is shown. Not limited to this, the plurality of heat dissipating members (metal bumps, metal pins) may be arranged (arranged) different from the above (first to fifth embodiments).

なお、上記第1〜第５実施形態では、放熱部材の一例として金属バンプまたは金属ピンを用いた例を示したが、本発明はこれに限らず、金属バンプまたは金属ピン以外の放熱部材を用いてもよい。また、金属柱以外の形状を有する放熱部材を用いても良い。   In the first to fifth embodiments, the metal bump or the metal pin is used as an example of the heat radiating member. However, the present invention is not limited to this, and a heat radiating member other than the metal bump or the metal pin is used. May be. Moreover, you may use the heat radiating member which has shapes other than a metal pillar.

また、上記第１〜第４実施形態では、両面基板からなる配線基板を用いてＢＧＡ型半導体装置（樹脂封止型半導体装置）を構成した例を示したが、本発明はこれに限らず、両面基板以外の例えば多層基板からなる配線基板を用いてＢＧＡ型半導体装置（樹脂封止型半導体装置）を構成してもよい。   Moreover, in the said 1st-4th embodiment, although the example which comprised the BGA type semiconductor device (resin sealing type semiconductor device) using the wiring board which consists of a double-sided board was shown, this invention is not restricted to this, A BGA type semiconductor device (resin-encapsulated semiconductor device) may be configured using a wiring board made of, for example, a multilayer board other than the double-sided board.

また、上記第１〜第３実施形態では、金属バンプを銅（Ｃｕ）から構成した例を示したが、本発明はこれに限らず、金属バンプを銅（Ｃｕ）以外の金属材料から構成してもよい。たとえば、金属バンプをアルミニウム（Ａｌ）から構成してもよい。   Moreover, although the example which comprised the metal bump from copper (Cu) was shown in the said 1st-3rd embodiment, this invention is not restricted to this, A metal bump is comprised from metal materials other than copper (Cu). May be. For example, the metal bump may be made of aluminum (Al).

また、上記第１実施形態の変形例では、放熱用の導体層を枠状に形成するとともに、搭載部から放射状に広がるように形成された４つの接続部を介して、放熱用の導体層と搭載部とを熱的に接続した構成例について説明したが、本発明はこれに限らず、放熱用の導体層および接続部の構成は、上記した構成（上記第１実施形態の変形例で示した構成）以外の構成であってもよい。   Further, in the modified example of the first embodiment, the heat-dissipating conductor layer is formed in a frame shape, and the heat-dissipating conductor layer and the heat-dissipating conductor layer are formed via four connecting portions formed so as to spread radially from the mounting portion. Although the configuration example in which the mounting portion is thermally connected has been described, the present invention is not limited to this, and the configuration of the conductive layer for heat dissipation and the connection portion is the above configuration (shown in the modification of the first embodiment). Other configurations) may be used.

また、上記第４および第５実施形態では、金属ピンを銅（Ｃｕ）から構成した例を示したが、本発明はこれに限らず、金属ピンを銅（Ｃｕ）以外の金属材料から構成してもよい。たとえば、金属ピンをアルミニウム（Ａｌ）から構成してもよい。   Moreover, although the example which comprised the metal pin from copper (Cu) was shown in the said 4th and 5th embodiment, this invention is not restricted to this, A metal pin is comprised from metal materials other than copper (Cu). May be. For example, the metal pin may be made of aluminum (Al).

１、１０１ 配線基板（基板）
２、１０２ 基材層
３ 配線層
３ａ 搭載部
３ｂ 接続電極層
３ｃ 放熱用の導体層
３ｄ 接続部
４ 配線層
４ａ 接続電極層
５ スルーホール
５ａ プラグ
６ 半田ボール
１０ 半導体チップ
１１ 接着層
１２ ボンディングワイヤ
２０ 封止樹脂層
３０ 金属バンプ（放熱部材、金属柱）
４０ ヒートシンク
４１ フィン
１３０ 金属ピン（放熱部材、金属柱） 1, 101 Wiring board (board)
DESCRIPTION OF SYMBOLS 2,102 Base material layer 3 Wiring layer 3a Mounting part 3b Connection electrode layer 3c Conductive layer 3d for heat dissipation 3d Connection part 4 Wiring layer 4a Connection electrode layer 5 Through hole 5a Plug 6 Solder ball 10 Semiconductor chip 11 Adhesion layer 12 Bonding wire 20 Sealing resin layer 30 Metal bump (heat dissipation member, metal pillar)
40 heat sink 41 fin 130 metal pin (heat radiating member, metal pillar)

Claims (6)

第１の半導体チップが搭載され、配線層を有する基板と、
前記基板に形成された外部接続電極と、
前記基板の前記第１の半導体チップが搭載された領域とは異なる領域において、前記外部接続電極が形成された面とは反対の面に形成され、導電性材料からなる複数の放熱部材と、
前記放熱部材の少なくとも一部が露出する露出部を備えるように前記第１の半導体チップを覆う封止樹脂層と、
を含み、
前記基板はその基板上に、前記放熱部材と、前記第１の半導体チップとを接続する接続部とを含む配線層を有し、
前記放熱部材の少なくとも一部は、所定の前記配線層と電気的に接続されており、前記複数の放熱部材はそれぞれが金属柱から形成されており、平面視において前記第１の半導体チップの周辺に配列されていることを特徴とする、樹脂封止型半導体装置。 A substrate on which a first semiconductor chip is mounted and having a wiring layer;
An external connection electrode formed on the substrate;
A plurality of heat dissipating members made of a conductive material formed on a surface opposite to the surface on which the external connection electrodes are formed in a region different from the region where the first semiconductor chip is mounted on the substrate;
A sealing resin layer covering the first semiconductor chip so as to have an exposed portion where at least a part of the heat dissipation member is exposed;
Including
The substrate has a wiring layer including a connection portion connecting the heat dissipation member and the first semiconductor chip on the substrate,
At least a part of the heat radiating member is electrically connected to the predetermined wiring layer, and each of the plurality of heat radiating members is formed of a metal column, and the periphery of the first semiconductor chip in a plan view A resin-encapsulated semiconductor device, wherein the resin-encapsulated semiconductor device is arranged in an array. 前記露出部は、４辺のそれぞれに少なくとも一つ配置されていることを特徴とする請求項１に記載の樹脂封止型半導体装置。   The resin-encapsulated semiconductor device according to claim 1, wherein at least one of the exposed portions is disposed on each of the four sides. 前記基板は複数の基材層が積層された多層基板であって、前記配線層は各基材層に配置されていることを特徴とする請求項１または請求項２に記載の樹脂封止型半導体装置。   The resin-sealed mold according to claim 1, wherein the substrate is a multilayer substrate in which a plurality of base material layers are laminated, and the wiring layer is disposed on each base material layer. Semiconductor device. 前記露出部の上部に接続電極が設けられていることを特徴とする請求項１〜３のいずれかに記載の樹脂封止型半導体装置。   The resin-encapsulated semiconductor device according to claim 1, wherein a connection electrode is provided on the exposed portion. 前記接続電極に第２の半導体チップが接続されていることを特徴とする請求項４に記載の樹脂封止型半導体装置。   The resin-encapsulated semiconductor device according to claim 4, wherein a second semiconductor chip is connected to the connection electrode. 前記第１の半導体チップと前記第２の半導体チップとは前記基板の前記配線層を経由して電気的に接続されていることを特徴とする請求項５に記載の樹脂封止型半導体装置。   6. The resin-encapsulated semiconductor device according to claim 5, wherein the first semiconductor chip and the second semiconductor chip are electrically connected via the wiring layer of the substrate.
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