JP2007281201A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007281201A
JP2007281201A JP2006105744A JP2006105744A JP2007281201A JP 2007281201 A JP2007281201 A JP 2007281201A JP 2006105744 A JP2006105744 A JP 2006105744A JP 2006105744 A JP2006105744 A JP 2006105744A JP 2007281201 A JP2007281201 A JP 2007281201A
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JP
Japan
Prior art keywords
spacer
wiring board
semiconductor device
chip
semiconductor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006105744A
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Japanese (ja)
Inventor
Yumiko Oshima
有美子 大島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Kioxia Advanced Package Corp
Original Assignee
Toshiba Corp
Toshiba LSI Package Solutions Corp
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Application filed by Toshiba Corp, Toshiba LSI Package Solutions Corp filed Critical Toshiba Corp
Priority to JP2006105744A priority Critical patent/JP2007281201A/en
Publication of JP2007281201A publication Critical patent/JP2007281201A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of a chip stack structure ensuring higher heat radiating effect. <P>SOLUTION: The semiconductor device includes a wiring substrate 100 having a first heat radiating means 135, a first semiconductor chip 105 mounted on the first heat radiating means 135 of the wiring substrate 100, a spacer 110 including a chip mounting part 111 and a supporting part 112 extended to the external side from the chip mounting part 111 and allowing the chip mounting part 111 to be mounted on the first semiconductor chip 105 and the supporting part 112 to be fixed to the wiring substrate 100, a second semiconductor ship 120 mounted on the chip mounting part 111 of the spacer 110, a connecting member 125 for electrically connecting the wiring substrate 100 and the first and second semiconductor chips 105, 120, and a sealing material 130 having the thermal conductivity lower than that of the spacer 110 for sealing the first semiconductor chip 105, spacer 110, second semiconductor chip 120 and connecting member 125 on the wiring substrate 100. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置、特に半導体チップを３次元的に積層して配置したチップスタック
構造のＳｉＰ（System in Package；以下ＳｉＰと記載する）に関する。 The present invention relates to a semiconductor device, and more particularly to a SiP (System in Package; hereinafter referred to as SiP) having a chip stack structure in which semiconductor chips are three-dimensionally stacked.

近年、半導体パッケージにおける構造の高密度化および複雑化が進展する中一つの半導
体パッケージ内部に、各種の機能を有する複数の半導体チップを配線基板上にスペーサを
介して３次元的に積層する、チップスタック構造のＳｉＰが注目を浴びている。 A chip in which a plurality of semiconductor chips having various functions are three-dimensionally stacked on a wiring substrate via a spacer in one of the semiconductor packages in which the density and complexity of the structure of the semiconductor package have been increasing in recent years. Stacked SiP is attracting attention.

通常、上述の構造を有するＳｉＰでは、一つのパッケージ内部において高密度に積層さ
れた複数の半導体チップが同時に動作することとなり、一つの半導体チップのみがパッケ
ージされたシングルチップ品に比べ、パッケージ内部の発熱量が大きくなる。半導体チッ
プから発生する熱がパッケージ内部で過剰に蓄積すると、チップの動作不良等の問題が生
じる恐れがある。従って、ＳｉＰの安定した動作を確保するためには、パッケージ内部で
発生した熱をその外部へ効率よく放熱する必要がある。 In general, in a SiP having the above-described structure, a plurality of semiconductor chips stacked at a high density inside one package operate simultaneously, and compared with a single chip product in which only one semiconductor chip is packaged, The calorific value increases. If heat generated from the semiconductor chip is excessively accumulated in the package, there is a possibility that problems such as chip malfunction may occur. Therefore, in order to ensure the stable operation of the SiP, it is necessary to efficiently dissipate the heat generated inside the package to the outside.

半導体チップで発生する熱をパッケージ外部へ効率的に逃がすための従来技術として、
半導体チップ直下の配線基板内部に放熱用ビアを形成したパッケージ構造が知られている
（例えば、特許文献１参照。）。 As a conventional technology for efficiently releasing heat generated in a semiconductor chip to the outside of the package,
A package structure in which a heat radiating via is formed inside a wiring board directly under a semiconductor chip is known (see, for example, Patent Document 1).

しかしながら、この従来技術では主要な放熱経路が半導体チップ直下の放熱用ビア一箇
所のみとなる構造であるため、発熱量の大きいＳｉＰにこの従来技術を適用しても、パッ
ケージ内部からその外部への放熱効果が不十分となり、パッケージ内部における過剰な発
熱に起因した半導体チップの動作不良等の問題が発生する恐れがある。
特開平０５−２５９６６９（図１） However, in this prior art, the main heat dissipation path is a structure with only one heat dissipating via directly under the semiconductor chip. Therefore, even if this prior art is applied to a SiP having a large amount of heat generation, the inside of the package to the outside thereof. The heat dissipation effect becomes insufficient, and problems such as malfunction of the semiconductor chip due to excessive heat generation inside the package may occur.
JP 05-259669 (FIG. 1)

本発明は、上記問題点を解決するためになされたもので、放熱効果の高いチップスタッ
ク構造の半導体装置を提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a chip stack structure semiconductor device having a high heat dissipation effect.

上記目的を達成するために、本発明の一態様の半導体装置は、配線基板と、前記配線基
板上に搭載された第一の半導体チップと、チップ搭載部と前記チップ搭載部より外方に延
びた支持部とを有し、前記チップ搭載部が前記第一の半導体チップ上に搭載され、前記支
持部が前記配線基板に固定されたスペーサと、前記スペーサの前記チップ搭載部上に搭載
された第二の半導体チップと、前記配線基板と前記第一及び第二の半導体チップとを電気
的に接続する接続部材と、前記配線基板上で前記第一の半導体チップ、前記スペーサ、前
記第二の半導体チップ及び前記接続部材を封止する、前記スペーサよりも熱伝導率の低い
封止体を備えたことを特徴とする。 In order to achieve the above object, a semiconductor device of one embodiment of the present invention includes a wiring board, a first semiconductor chip mounted on the wiring board, a chip mounting portion, and an outer side extending from the chip mounting portion. The chip mounting portion is mounted on the first semiconductor chip, the support portion is mounted on the wiring board, and the spacer is mounted on the chip mounting portion of the spacer. A second semiconductor chip; a connection member for electrically connecting the wiring board and the first and second semiconductor chips; and the first semiconductor chip, the spacer, and the second on the wiring board. A sealing body that seals a semiconductor chip and the connection member and has a lower thermal conductivity than the spacer is provided.

また、本発明の別の態様の半導体装置は、第一の放熱手段を有し、かつ前記第一の放熱手
段の外縁部に信号供給手段及び第二の放熱手段を有する配線基板と、前記配線基板の前記
第一の放熱手段上に搭載された、第一の電極を有する第一の半導体チップと、チップ搭載
部と前記チップ搭載部より外方に延びた支持部とを有し、前記チップ搭載部が前記第一の
半導体チップ上に搭載され、前記支持部の端部が前記配線基板の前記第二の放熱手段に固
定されたスペーサと、前記スペーサの前記チップ搭載部上に搭載された、第二の電極を有
する第二の半導体チップと、前記配線基板の前記信号供給手段と前記第一及び第二の半導
体チップの前記第一及び前記第二の電極とをそれぞれ電気的に接続する接続部材と、前記
配線基板上で前記第一の半導体チップ、前記スペーサ、前記第二の半導体チップ及び前記
接続部材を封止する、前記スペーサよりも熱伝導率の低い封止体を備えたことを特徴とす
る。 According to another aspect of the present invention, there is provided a semiconductor device having a first heat radiating means, a wiring board having a signal supply means and a second heat radiating means at an outer edge portion of the first heat radiating means, and the wiring A first semiconductor chip having a first electrode mounted on the first heat dissipation means of the substrate; a chip mounting portion; and a support portion extending outward from the chip mounting portion; A mounting portion is mounted on the first semiconductor chip, and an end portion of the support portion is mounted on the chip mounting portion of the spacer, and a spacer fixed to the second heat radiation means of the wiring board. Electrically connecting the second semiconductor chip having the second electrode, the signal supply means of the wiring board, and the first and second electrodes of the first and second semiconductor chips, respectively. A connecting member and the first semiconductor on the wiring board; Chip, the spacer, sealing the second semiconductor chip and the connecting member, characterized by comprising a lower sealing body thermal conductivity than said spacer.

本発明によれば、放熱効果の高いチップスタック構造の半導体装置を提供することがで
きる。 ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device of a chip stack structure with a high heat dissipation effect can be provided.

以下、本発明の実施形態に係る半導体装置およびその製造方法について図面を参照して
説明する。 A semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described below with reference to the drawings.

まず、図１乃至図３を参照して、本発明の実施例１に係るチップスタック構造の半導体
装置について説明する。図１は、本発明の実施例１に係る半導体装置において封止体を透
視した状態の上面図、図２は、本発明の実施例１に係る半導体装置の下面図、図３（ａ）
は、図１の一点鎖線Ａ−Ａ’における断面図、図３（ｂ）は、図１の一点鎖線Ｂ−Ｂ’に
おける断面図である。 First, a chip stack structure semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 is a top view of the semiconductor device according to the first embodiment of the present invention as seen through the sealing body, FIG. 2 is a bottom view of the semiconductor device according to the first embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view taken along one-dot chain line AA ′ in FIG. 1, and FIG. 3B is a cross-sectional view taken along one-dot chain line BB ′ in FIG.

図１乃至図３に示したように、本実施例に係る半導体装置では、配線基板１００上面の
中央部には、第一の電極１０６を有する第一の半導体チップ１０５が接着剤１０１を介し
て搭載され、第一の半導体チップ１０５上には接着剤１０２を介してスペーサ１１０が搭
載され、スペーサ１１０の端部が配線基板１００に固定部材１１５により固定されている
。このスペーサ１１０上には接着剤１０３を介して第二の電極１２１を有する第二の半導
体チップ１２０が搭載されており、また第一の半導体チップ１０５の第一の電極１０６及
び第二の半導体チップ１２０の第二の電極１２１がそれぞれ配線基板１００に接続部材１
２５によって電気的に接続されている。さらに配線基板１００上において、封止体１３０
により、第一の半導体チップ１０５、スペーサ１１０、第二の半導体チップ１２０、及び
接続部材１２５が封止されている。 As shown in FIGS. 1 to 3, in the semiconductor device according to the present embodiment, a first semiconductor chip 105 having a first electrode 106 is interposed via an adhesive 101 at the center of the upper surface of the wiring substrate 100. The spacer 110 is mounted on the first semiconductor chip 105 via the adhesive 102, and the end of the spacer 110 is fixed to the wiring substrate 100 by the fixing member 115. A second semiconductor chip 120 having a second electrode 121 is mounted on the spacer 110 via an adhesive 103, and the first electrode 106 and the second semiconductor chip of the first semiconductor chip 105 are mounted. Each of the second electrodes 121 of 120 is connected to the wiring board 100 by the connecting member 1.
25 is electrically connected. Further, on the wiring substrate 100, the sealing body 130.
Thus, the first semiconductor chip 105, the spacer 110, the second semiconductor chip 120, and the connection member 125 are sealed.

また、第一の半導体チップ１０５直下の配線基板１００部分及びスペーサ１１０の端部
直下の配線基板１００部分には、第一の放熱手段１３５及び第二の放熱手段１４５がそれ
ぞれ形成されている。また、接続部材１２５と配線基板１００との接続部分には、信号供
給手段１５５が形成されている。さらに、配線基板１００の下面には、マザーボード等（
図示せず）へ実装するための金属ボール１６０が取り付けられている。 Further, a first heat radiation means 135 and a second heat radiation means 145 are formed on the wiring substrate 100 portion immediately below the first semiconductor chip 105 and the wiring substrate 100 portion directly below the end of the spacer 110, respectively. Further, a signal supply means 155 is formed at a connection portion between the connection member 125 and the wiring board 100. Furthermore, a mother board or the like (
A metal ball 160 for mounting to a not-shown device is attached.

以下、上述した各構成部材等について、詳細に説明を行う。   Hereinafter, each of the above-described constituent members will be described in detail.

配線基板１００は、例えば、樹脂材料、有機高分子材料またはセラミック材料等からなる
絶縁性基材層（図示せず）とＣｕ、Ａｌ等からなる導電性配線層（図示せず）が積層され
た構造となっている。また、配線基板１００の形状は、例えば上下面が同一四角形状であ
る矩形平面形状となっている。 The wiring substrate 100 is formed by laminating an insulating base layer (not shown) made of, for example, a resin material, an organic polymer material, or a ceramic material, and a conductive wiring layer (not shown) made of Cu, Al, or the like. It has a structure. Moreover, the shape of the wiring board 100 is, for example, a rectangular planar shape whose upper and lower surfaces are the same rectangular shape.

第一の半導体チップ１０５は、例えば、Ｓｉ等の半導体基板に所定の回路機能素子等が
形成されたものであり、上面を上方に向けて配線基板１００上に、接着剤１０１を介して
搭載されている。第一の半導体チップ１０５で発生した熱の大部分は、第一の半導体チッ
プ１０５直下の配線基板１００に形成された第一の放熱手段１３５に伝達されて外部に放
出される。 The first semiconductor chip 105 is formed by, for example, a predetermined circuit function element or the like formed on a semiconductor substrate such as Si, and is mounted on the wiring substrate 100 with an adhesive 101 facing upward. ing. Most of the heat generated in the first semiconductor chip 105 is transmitted to the first heat radiating means 135 formed on the wiring board 100 immediately below the first semiconductor chip 105 and released to the outside.

また、第一の半導体チップ１０５は、上面の周縁部に回路機能素子等と電気的に接続さ
れた第一の電極１０６を有しており、第一の電極１０６は、金属材料、例えばＡｌやＣｕ
等によって形成されている。また、第一の電極１０６の少なくとも一部を残し、その他の
上面部分には、外部応力等からチップを保護するため、例えば、ＳｉＯ２、ＳｉＮ、ポリ
イミド樹脂等の構成材料からなるパッシベーション膜（図示せず）が形成されている。 Further, the first semiconductor chip 105 has a first electrode 106 electrically connected to a circuit functional element or the like at the periphery of the upper surface, and the first electrode 106 is made of a metal material such as Al or the like. Cu
Etc. are formed. In addition, a passivation film made of a constituent material such as SiO 2 , SiN, or polyimide resin is used for protecting the chip from external stress or the like on at least a part of the first electrode 106 and the other upper surface portion (see FIG. (Not shown) is formed.

接着剤１０１、１０２、１０３は、ここでは、例えば、エポキシ系樹脂等の樹脂材料が
用いられているが、第一の半導体チップ１０５から配線基板１００、または第二の半導体
チップ１２０からスペーサ１１０への熱伝導性を高めるためには、例えば、エポキシ樹脂
等にＡｇフィラーを含有したＡｇペーストや、アルミナ、窒化ボロン等のセラミックを含
有したシリコーンまたはゴム状材料等のような封止体１３０よりも熱伝導率の高いものを
用いることが好ましい。 Here, for example, a resin material such as an epoxy resin is used for the adhesives 101, 102, and 103, but from the first semiconductor chip 105 to the wiring substrate 100, or from the second semiconductor chip 120 to the spacer 110. In order to increase the thermal conductivity of the sealing body 130, for example, an Ag paste containing an Ag filler in an epoxy resin or the like, or a silicone or rubber-like material containing a ceramic such as alumina or boron nitride. It is preferable to use a material having high thermal conductivity.

スペーサ１１０は、第一の半導体チップ１０５と第二の半導体チップ１２０との間に介
在されることにより、第一の半導体チップ１０５の第一の電極１０６上方に一定のスペー
スを作り、この第一の電極１０６へのワイヤボンディングを可能にする機能に加え、端部
を配線基板１００に固定することにより、第二の半導体チップ１２０で発生した熱を効率
よく配線基板１００に伝達するための放熱経路としての機能を有している。つまり、図３
に示すように、第二の半導体チップ１２０で発生した熱及び第一の半導体チップ１０５で
発生した熱の一部は、スペーサ１１０の端部直下の配線基板１００部分に伝達され外部に
放出される。 The spacer 110 is interposed between the first semiconductor chip 105 and the second semiconductor chip 120, thereby creating a certain space above the first electrode 106 of the first semiconductor chip 105. In addition to the function of enabling the wire bonding to the electrode 106, the heat dissipation path for efficiently transferring the heat generated in the second semiconductor chip 120 to the wiring board 100 by fixing the end to the wiring board 100 As a function. That is, FIG.
As shown in FIG. 2, the heat generated in the second semiconductor chip 120 and a part of the heat generated in the first semiconductor chip 105 are transmitted to the wiring substrate 100 portion immediately below the end of the spacer 110 and released to the outside. .

スペーサ１１０は、第一及び第二の半導体チップ１０５、１２０で発生した熱を効果的
に伝達するために、封止体１３０の構成材料よりも熱伝導率の高い材料、特にＣｕ等の金
属材料で構成することが好ましい。 The spacer 110 is a material having a higher thermal conductivity than the constituent material of the sealing body 130, particularly a metal material such as Cu, in order to effectively transfer the heat generated in the first and second semiconductor chips 105 and 120. It is preferable to comprise.

ここでスペーサ１１０は、本実施例では、図１に示したように、第一の半導体チップ１
０５より大きな矩形平面形状のチップ搭載部１１１と、チップ搭載部１１１の各角部から
チップ搭載部１１１の対角線方向に沿って外方に伸びる支持部１１２とを有し、チップ搭
載部１１１が接着剤１０２を介して第一の半導体チップ１０５の上面に接着され、４本の
支持部１１２の端部が固定部材１１５により配線基板１００の四隅の第二の放熱手段１４
５に固定されている。 In this embodiment, the spacer 110 is the first semiconductor chip 1 as shown in FIG.
A chip mounting part 111 having a rectangular planar shape larger than 05, and a support part 112 extending outward from each corner of the chip mounting part 111 along the diagonal direction of the chip mounting part 111; Adhering to the upper surface of the first semiconductor chip 105 through the agent 102, the end portions of the four support portions 112 are fixed to the second heat radiation means 14 at the four corners of the wiring substrate 100 by the fixing member 115.
5 is fixed.

固定材料１１５は、スペーサ１１０と配線基板１００を固定するためのもので、スペー
サ１１０から配線基板１００への熱伝導を良好にするため、封止体１３０よりも熱伝導率
の高い、例えばＡｇペースト等の樹脂材料を用いるのが好ましい。また、この固定材料１
１５は、スペーサ１１０と封止体１３０の熱膨張係数の違いによってスペーサ１１０と配
線基板１００の固定部に生じる応力を緩和するために、封止体１３０よりも弾性率が低い
ことが好ましい。例えば、配線基板１００の絶縁性基材の弾性率が２０〜３０ＧＰａ、封
止体１３０の材料である封止樹脂の弾性率が常温で１０〜３０ＧＰａである場合、固定材
料１１５の弾性率が常温で１００ＭＰａであるようなものを選択する。 The fixing material 115 is for fixing the spacer 110 and the wiring substrate 100. In order to improve the heat conduction from the spacer 110 to the wiring substrate 100, for example, Ag paste having a higher thermal conductivity than the sealing body 130. It is preferable to use a resin material such as This fixing material 1
15 has a lower elastic modulus than that of the sealing body 130 in order to relieve stress generated in the fixing portion of the spacer 110 and the wiring board 100 due to a difference in thermal expansion coefficient between the spacer 110 and the sealing body 130. For example, when the elastic modulus of the insulating base material of the wiring substrate 100 is 20 to 30 GPa and the elastic modulus of the sealing resin that is the material of the sealing body 130 is 10 to 30 GPa at normal temperature, the elastic modulus of the fixing material 115 is normal temperature. The one that is 100 MPa is selected.

第二の半導体チップ１２０は、第一の半導体チップ１０５と同様に、回路機能素子が設
けられ、上面周縁部に回路機能素子と電気的に接続された第二の電極１２１が形成され、
第二の電極１２１の少なくとも一部を残し、その他の上面部分にパッシベーション膜（図
示せず）が形成されている。 Similarly to the first semiconductor chip 105, the second semiconductor chip 120 is provided with a circuit function element, and a second electrode 121 electrically connected to the circuit function element is formed on the upper surface periphery.
A passivation film (not shown) is formed on the other upper surface portion, leaving at least a part of the second electrode 121.

接続部材１２５は、例えばＡｕまたはＣｕ等の金属ワイヤからなり、第一の半導体チッ
プ１０５の第一の電極１０６及び第二の半導体チップ１２０の第二の電極１２１と配線基
板１００の信号供給手段１５５をそれぞれボンディングして電気的に接続している。この
接続部材１２５としては、金属ワイヤに限らずＴＡＢ（Tape Automated Bonding）テープ
等のようなものであってもよい。 The connection member 125 is made of, for example, a metal wire such as Au or Cu, and the first electrode 106 of the first semiconductor chip 105, the second electrode 121 of the second semiconductor chip 120, and the signal supply unit 155 of the wiring substrate 100. Are bonded and electrically connected. The connecting member 125 is not limited to a metal wire but may be a TAB (Tape Automated Bonding) tape or the like.

封止体１３０は、スペーサ１１０よりも熱伝導率の低い材料、例えば熱硬化性樹脂材料
等の樹脂材料やガラス類により構成され、第一の半導体チップ１０５、スペーサ１１０、
第二の半導体チップ１２０及び金属ワイヤ１２５を直接覆うように封止して、外部応力等
から半導体装置を保護する。また、封止体１３０の強度等を調整するため、封止体１３０
に絶縁性のフィラーを充填してもよい。例えば、封止体１３０にシリカをフィラーとして
充填したエポキシ樹脂を用いてもよい。 The sealing body 130 is made of a material having a lower thermal conductivity than the spacer 110, for example, a resin material such as a thermosetting resin material or glass, and includes the first semiconductor chip 105, the spacer 110,
Sealing is performed so as to directly cover the second semiconductor chip 120 and the metal wire 125 to protect the semiconductor device from external stress or the like. Further, in order to adjust the strength and the like of the sealing body 130, the sealing body 130.
May be filled with an insulating filler. For example, an epoxy resin in which the sealing body 130 is filled with silica as a filler may be used.

第一の放熱手段１３５は、主に第一の半導体チップ１０５から配線基板１００に伝達さ
れた熱を効率よく配線基板１００の外部に放出することができ、第一の半導体チップ１０
５直下の配線基板１００部分に設けられている。 The first heat radiating means 135 can efficiently release the heat transmitted from the first semiconductor chip 105 to the wiring substrate 100 to the outside of the wiring substrate 100, and the first semiconductor chip 10.
It is provided in the wiring board 100 portion immediately below five.

第二の放熱手段１４５は、主に第二の半導体チップ１２０からスペーサ１１０を介して
配線基板１００に伝達された熱を効率よく配線基板１００の外部に放出することができ、
配線基板１００の周縁部の四隅に固定されたスペーサの支持部１１２の端部の直下の配線
基板１００部分にそれぞれ設けられている。 The second heat dissipating means 145 can efficiently release the heat transmitted from the second semiconductor chip 120 to the wiring board 100 through the spacer 110 to the outside of the wiring board 100,
The wiring board 100 is provided on each of the wiring board 100 portions immediately below the end portions of the support portions 112 of the spacers fixed to the four corners of the peripheral edge of the wiring board 100.

一般的に、配線基板１００の四隅には、ワイヤボンディングのための信号供給手段１５
５が形成されないため、第二の放熱手段１４５はこの配線基板１００の四隅に容易に配置
することができる。つまり、ワイヤボンディングする信号供給手段１５５の位置、あるい
は信号供給手段１５５と第一及び第二の半導体チップ１０５、１２０との配線方法を、一
般的な半導体装置から特別に変更することなく、さらには、配線基板１００を特別に大き
くすることなく、第二の放熱手段１４５を容易に形成することができる。 Generally, signal supply means 15 for wire bonding is provided at four corners of the wiring board 100.
5 is not formed, the second heat dissipating means 145 can be easily disposed at the four corners of the wiring board 100. That is, the position of the signal supply means 155 for wire bonding or the wiring method between the signal supply means 155 and the first and second semiconductor chips 105 and 120 is not changed from a general semiconductor device, and further, The second heat dissipating means 145 can be easily formed without particularly increasing the size of the wiring board 100.

本実施例では、第一及び二の放熱手段１３５、１４５は、いずれも上部放熱用パッド１
３６、１４６と、この上部放熱用パッド１３６、１４６とそれぞれ対向して配線基板１０
０の下面に設けられた下部放熱用パッド１３７、１４７と、この上、下部放熱用パッド１
３６、１３７間及び１４６、１４７間の配線基板１００内に設けられた放熱用ビア１３８
、１４８とで構成されている。 In this embodiment, the first and second heat dissipating means 135 and 145 are both the upper heat dissipating pad 1.
36, 146 and the upper heat radiation pads 136, 146 respectively facing the wiring board 10
Lower heat radiation pads 137 and 147 provided on the lower surface of 0, and further, the lower heat radiation pad 1
36, 137 and 146, 147 between the heat dissipation vias 138 provided in the wiring board 100.
148.

上、下部放熱用パッド１３６、１４６、１３７、１４７は、いずれも、放熱性をより向
上するためのもので、例えば、ＡｌやＣｕ等の金属被膜で形成されている。なお、上、下
部放熱用パッド１３６、１４６、１３７、１４７は、必ずしも必要ではなく、上部放熱用
パッド１３６、１４６及び下部放熱用パッド１３７、１４７のドちらか一方あるいは両方
とも省略してもよい。 The upper and lower heat dissipation pads 136, 146, 137, and 147 are all for improving heat dissipation, and are formed of, for example, a metal film such as Al or Cu. The upper and lower heat radiating pads 136, 146, 137, and 147 are not necessarily required, and either one or both of the upper heat radiating pads 136 and 146 and the lower heat radiating pads 137 and 147 may be omitted. .

ビア１３８、１４８は、上、下部放熱用パッド１３６、１３７間及び１４６、１４７間
をそれぞれ熱的に接続して、第一及び第二の半導体チップ１０５、１２０からの熱をそれ
ぞれ配線基板１００外部へ放出するためのもので、配線基板１００を上下に貫通するビア
ホール１３９、１４９と、このビアホール１３９、１４９の内側面に設けられた、例えば
Ｃｕ、Ａｇ、Ａｕめっき等のめっき層１４０、１５０と、ビアホール１３９、１４９内に
埋め込まれた、配線基板１００の絶縁性基材層よりも高伝熱性の材料である、例えばＡｇ
ペースト、Ｃｕペースト等のプラグ１４１、１５１とで構成されている。 The vias 138 and 148 thermally connect the upper and lower heat radiation pads 136 and 137 and 146 and 147, respectively, to transfer heat from the first and second semiconductor chips 105 and 120 to the outside of the wiring board 100, respectively. Via holes 139 and 149 penetrating the wiring substrate 100 in the vertical direction, and plating layers 140 and 150 made of Cu, Ag, Au, or the like provided on the inner surfaces of the via holes 139 and 149, and , A material having higher heat conductivity than the insulating base material layer of the wiring substrate 100 embedded in the via holes 139 and 149, for example, Ag
It is composed of plugs 141 and 151 such as paste and Cu paste.

なお、本実施例では、ビア１３８、１４８の熱伝導性を高めるためにビアホール１３９
、１４９内部に、プラグ１４１、１５１を埋め込んでいるが、ビア１３８、１４８はめっ
き層１４０、１５０とプラグ１４１、１５１の両者を必ずしも備える必要はなく、めっき
層１４０、１５０またはプラグ１４１、１５１の一方のみ備えていてもよい。 In this embodiment, via holes 139 are used to increase the thermal conductivity of the vias 138 and 148.
149, plugs 141 and 151 are embedded, but the vias 138 and 148 do not necessarily include both the plating layers 140 and 150 and the plugs 141 and 151. The plating layers 140 and 150 or the plugs 141 and 151 are not necessarily provided. Only one may be provided.

信号供給手段１５５は、配線基板１００の隅部に形成された第二の放熱手段１４５間の
配線基板１００の周縁部にそれぞれ形成されている。この信号供給手段１５５は、第一及
び第二の放熱手段１３５、１４５と同様に、配線基板１００の上面に上部電極パッド１５
６、下面には上部電極パッド１５６と同等の大きさの下部電極パッド１５７が設けられ、
上、下部電極パッド１５６、１５７間の配線基板１００部分にはビア１６８が設けられて
いる。ビア１６８は、配線基板１００を上下に貫通するビアホール１６９と、ビアホール
１６９内側面に設けられためっき層１７０と、ビアホール１６９内に埋め込まれたプラグ
１７１とで構成されている。また、各信号供給手段１５５のビア１６８と配線基板１００
内の絶縁性基材層に設けられた所定配線層は、互いに電気的に接続されている。 The signal supply means 155 is formed at the peripheral edge of the wiring board 100 between the second heat radiation means 145 formed at the corners of the wiring board 100. The signal supply means 155 is formed on the upper surface of the wiring substrate 100 in the same manner as the first and second heat radiation means 135 and 145.
6. A lower electrode pad 157 having the same size as the upper electrode pad 156 is provided on the lower surface.
A via 168 is provided in the wiring substrate 100 portion between the upper and lower electrode pads 156 and 157. The via 168 includes a via hole 169 that vertically penetrates the wiring substrate 100, a plating layer 170 provided on the inner side surface of the via hole 169, and a plug 171 embedded in the via hole 169. Further, the via 168 of each signal supply means 155 and the wiring board 100.
The predetermined wiring layers provided on the inner insulating base layer are electrically connected to each other.

なお、第一の放熱手段１３５のビア１３８、第二の放熱手段１４５のビア１４８及び信
号供給手段１５５のビア１６８は、同一径に形成され、第一及び第二の放熱手段１３５、
１４５には複数個のビア１３８、１４８がそれぞれ形成されている。 The via 138 of the first heat radiating means 135, the via 148 of the second heat radiating means 145, and the via 168 of the signal supply means 155 are formed to have the same diameter, and the first and second heat radiating means 135,
A plurality of vias 138 and 148 are formed in 145, respectively.

金属ボール１６０は、例えばＳｎ−Ａｇ系、Ｓｎ−Ａｇ−Ｃｕ系のはんだにより形成さ
れ、第一及び第二の放熱手段１３５、１４５の下部放熱用パッド１３７、１４７にそれぞ
れ複数個設けられて外部への放熱端子として機能し、あるいは信号供給手段１５５の下部
電極パッド１５７にそれぞれ設けられて信号及び電源供給端子として機能する。 The metal balls 160 are formed of, for example, Sn-Ag-based or Sn-Ag-Cu-based solder, and a plurality of metal balls 160 are provided on the lower heat radiation pads 137 and 147 of the first and second heat radiation means 135 and 145, respectively. It functions as a heat radiating terminal, or is provided on the lower electrode pad 157 of the signal supply means 155 to function as a signal and power supply terminal.

次に、図４を参照して、本実施例に係る半導体装置の製造工程について説明する。図４
は本実施例に係る半導体装置の製造工程の概略を示す工程断面図であり、図中の左半分が
図１に示す一点破線Ａ−Ａ’、右半分が図１に示す一点破線Ｂ−Ｂ’における工程断面図
を示している。 Next, with reference to FIG. 4, the manufacturing process of the semiconductor device according to this example will be described. FIG.
These are process sectional drawings which show the outline of the manufacturing process of the semiconductor device which concerns on a present Example, the left half in a figure is the dashed-dotted line AA 'shown in FIG. 1, and the right half is the dashed-dotted line BB shown in FIG. The process sectional drawing in 'is shown.

まず、図４（ａ）に示すように、配線基板１００の中央部及び隅部に第一の放熱手段１
３５のビア１３８及び第二の放熱手段１４５のビア１４８をそれぞれ形成し、配線基板１
００を準備する。ビア１３８、１４８は、ドリルによって配線基板１００にビアホール１
３９、１４０を設け、例えばめっき法によりビアホール１３９、１４９の内側面にそれぞ
れＣｕめっき層１４０、１５０を形成し、さらにビアホール１３９、１４９内にそれぞれ
Ｃｕペースト等を埋め込んでプラグ１４１、１５１とすることで形成する。また同様にし
て、配線基板１００の周縁部に信号供給手段１５５のビア１６８を形成する。 First, as shown in FIG. 4A, the first heat dissipating means 1 is provided at the center and corners of the wiring board 100.
35 vias 138 and vias 148 of the second heat dissipating means 145 are formed, respectively.
Prepare 00. The vias 138 and 148 are formed in the via hole 1 in the wiring board 100 by a drill.
39, 140 are provided, Cu plating layers 140, 150 are formed on the inner side surfaces of the via holes 139, 149, for example, by plating, and Cu paste or the like is embedded in the via holes 139, 149, respectively, to form plugs 141, 151. Form with. Similarly, a via 168 of the signal supply means 155 is formed in the peripheral portion of the wiring board 100.

次に、第一の放熱手段１３５のビア１３８上方の配線基板１００上面に上部放熱用パッ
ド１３６、第二の放熱手段１４５のビア１４８上方の配線基板１００上面に上部放熱用パ
ッド１４６、及び信号供給手段１５５のビア１６８上方の配線基板１００上面に上部電極
パッド１５６をそれぞれ形成し、各ビア１３８、１４８の下方の配線基板１００下面に下
部放熱用パッド１３７、１４７をそれぞれ形成すると共に、信号供給手段１５５のビア１
６８の下方の配線基板１００下面に下部電極パッド１５７を形成する。 Next, the upper heat dissipating pad 136 is formed on the upper surface of the wiring board 100 above the via 138 of the first heat dissipating means 135, the upper heat dissipating pad 146 is formed on the upper surface of the wiring substrate 100 above the via 148 of the second heat dissipating means 145, and the signal supply. The upper electrode pad 156 is formed on the upper surface of the wiring board 100 above the via 168 of the means 155, the lower heat radiation pads 137 and 147 are formed on the lower surface of the wiring board 100 below the vias 138 and 148, respectively, and the signal supply means 155 via 1
A lower electrode pad 157 is formed on the lower surface of the wiring board 100 below 68.

次に、ダイボンディング工程において、まず、接着剤１０１を配線基板１００中央付近
の上部放熱用パッド１３６上に塗布した後、第一の半導体チップ１０５をこの接着剤１０
１を介して上部放熱用パッド１３６上に固着する。ここで、第一の半導体チップ１０５は
回路面を上にしてボンディングされる（フェースアップボンディング）。 Next, in the die bonding step, first, the adhesive 101 is applied on the upper heat radiation pad 136 near the center of the wiring substrate 100, and then the first semiconductor chip 105 is attached to the adhesive 10.
1 is fixed on the upper heat radiation pad 136 via the first heat radiation pad 136. Here, the first semiconductor chip 105 is bonded with the circuit surface facing upward (face-up bonding).

次に、ワイヤボンディング工程において、第一の半導体チップ１０５の第一の電極１０
６と配線基板１００に形成された信号供給手段１５５の上部電極パッド１５６に金属ワイ
ヤ（接続部材１２５）をワイヤボンディングすることにより、第一の半導体チップ１０５
の第一の電極１０６と配線基板１００の上部電極パッド１５６を電気的に接続する。 Next, in the wire bonding process, the first electrode 10 of the first semiconductor chip 105 is used.
6 and the upper electrode pad 156 of the signal supply means 155 formed on the wiring substrate 100, a metal wire (connecting member 125) is wire-bonded to form the first semiconductor chip 105.
The first electrode 106 and the upper electrode pad 156 of the wiring substrate 100 are electrically connected.

次に、図４（ｂ）に示すように、第一の半導体チップ１０５上に、スペーサ１１０のチ
ップ搭載部１１１を金属ワイヤ１２５と接触しないように接着剤１０２を介して固着する
。また同時に、スペーサ１１０の支持部１１２の端部を、固定部材１１５により配線基板
１００の隅部の上部放熱用パッド１４６に固定する。 Next, as shown in FIG. 4B, the chip mounting portion 111 of the spacer 110 is fixed on the first semiconductor chip 105 with an adhesive 102 so as not to contact the metal wire 125. At the same time, the end portion of the support portion 112 of the spacer 110 is fixed to the upper heat radiation pad 146 at the corner of the wiring substrate 100 by the fixing member 115.

続いて、ダイボンディング工程において、スペーサ１１０のチップ搭載部１１１上に接
着剤１０３を介して第二の半導体チップ１２０を搭載する。ここで、第二の半導体チップ
１２０は、第一の半導体チップ１０５と同様、フェースアップボンディングされる。 Subsequently, in the die bonding process, the second semiconductor chip 120 is mounted on the chip mounting portion 111 of the spacer 110 via the adhesive 103. Here, the second semiconductor chip 120 is face-up bonded in the same manner as the first semiconductor chip 105.

さらに、ワイヤボンディング工程において、金属ワイヤ１２５を第二の半導体チップ１
２０の第二の電極１２１と配線基板１００に形成された信号供給手段１５５の上部電極パ
ッド１５６にボンディングすることにより、第二の半導体チップ１２０の第二の電極１２
１と配線基板１００の上部電極パッド１５６を電気的に接続する。またこのとき金属ワイ
ヤ１２５は、スペーサ１１０と接触しないようにボンディングされる。 Further, in the wire bonding step, the metal wire 125 is connected to the second semiconductor chip 1.
The second electrode 121 of the second semiconductor chip 120 is bonded to the upper electrode pad 156 of the signal supply means 155 formed on the wiring substrate 100 and the second electrode 121 of the second semiconductor chip 120.
1 and the upper electrode pad 156 of the wiring substrate 100 are electrically connected. At this time, the metal wire 125 is bonded so as not to contact the spacer 110.

次に、図４（ｃ）に示すように、モールド工程において、配線基板１００上の第一の半
導体チップ１０５、第二の半導体チップ１２０、スペーサ１１０及び金属ワイヤ１２５を
絶縁性樹脂等の封止体１３０により封止する。続いて、配線基板１００下面の下部放熱用
パッド１３７、１４７、及び下部電極パッド１５７に、金属ボール１６０をそれぞれ取り
付ける。例えば、配線基板１００の下面を上方に向けた状態で、配線基板１００下面の下
部放熱用パッド１３７、１４７、及び下部電極パッド１５７上に金属ボール１６０を載せ
て、リフロー処理を行うことにより、金属ボール１６０をそれぞれ取り付ける。以上の工
程により、本実施例に係るチップスタック構造の半導体装置が製造される。 Next, as shown in FIG. 4C, in the molding process, the first semiconductor chip 105, the second semiconductor chip 120, the spacer 110, and the metal wire 125 on the wiring substrate 100 are sealed with an insulating resin or the like. Sealed with the body 130. Subsequently, the metal balls 160 are respectively attached to the lower heat radiation pads 137 and 147 and the lower electrode pad 157 on the lower surface of the wiring substrate 100. For example, the metal ball 160 is placed on the lower heat radiation pads 137 and 147 and the lower electrode pad 157 on the lower surface of the wiring substrate 100 with the lower surface of the wiring substrate 100 facing upward, and the reflow process is performed. Each ball 160 is attached. Through the above steps, the semiconductor device having the chip stack structure according to this embodiment is manufactured.

上述した本実施例に係る半導体装置では、第一及び第二の半導体チップ１０５、１２０
で発生した熱を、第一の半導体チップ１０５直下のみならず、スペーサ１１０を介して直
接配線基板１００へ逃がすことができるため、従来の半導体装置に比べ、高い放熱効果を
得ることができる。つまり、従来の半導体装置では、第一の半導体チップ１０５直下のみ
に放熱経路が形成されているのに対し、本実施例に係る半導体装置では、第一の半導体チ
ップ１０５直下のみならず、スペーサ１１０を経由して、直接配線基板１００に熱を伝達
する放熱経路が形成されているため、放熱経路の増加により放熱効果を向上させることが
できる。 In the semiconductor device according to this embodiment described above, the first and second semiconductor chips 105 and 120 are used.
Since the heat generated in step 1 can be released not only directly below the first semiconductor chip 105 but also directly to the wiring substrate 100 via the spacer 110, a higher heat dissipation effect can be obtained as compared with the conventional semiconductor device. That is, in the conventional semiconductor device, the heat dissipation path is formed only directly below the first semiconductor chip 105, whereas in the semiconductor device according to the present embodiment, not only the first semiconductor chip 105 but also the spacer 110 is formed. Since a heat dissipation path for directly transferring heat to the wiring substrate 100 is formed via the, a heat dissipation effect can be improved by increasing the heat dissipation path.

また、第一の半導体チップ１０５直下の配線基板１００部分に第一の放熱手段１３５を
形成し、さらにスペーサ１１０の支持部１１２と配線基板１００の固定部直下の配線基板
１００部分に第二の放熱手段１４５を設けることで、配線基板１００に伝達された熱を、
第一及び第二の放熱手段１３５、１４５を介して、効率よく配線基板１００の外部へ放出
することができる。 In addition, the first heat radiation means 135 is formed in the portion of the wiring substrate 100 immediately below the first semiconductor chip 105, and the second heat dissipation is performed in the portion of the wiring substrate 100 immediately below the support portion 112 of the spacer 110 and the fixing portion of the wiring substrate 100. By providing the means 145, the heat transferred to the wiring board 100 is
Through the first and second heat dissipating means 135 and 145, it can be efficiently discharged to the outside of the wiring board 100.

さらに、本実施例のように、第二の放熱手段１４５を配線基板１００の隅部に配置すれ
ば、信号供給手段１５５の位置、あるいは信号供給手段１５５と第一及び第二の半導体チ
ップ１０５、１２０との配線方法を特別に変更することなく、第二の放熱手段１４５を容
易に形成することができ、簡易な方法で放熱効果を向上することができる。 Further, if the second heat radiation means 145 is arranged at the corner of the wiring board 100 as in this embodiment, the position of the signal supply means 155 or the signal supply means 155 and the first and second semiconductor chips 105, The second heat dissipating means 145 can be easily formed without specially changing the wiring method with 120, and the heat dissipating effect can be improved by a simple method.

さらにまた、ビア１３８、１４８下方の配線基板１００部分の下面に下部放熱用パッド
１３７、１４７及び金属ボール１６０を設け、金属ボール１６０を、例えば配線基板１０
０等よりも熱容量の大きいマザーボード等へ接合することで、半導体装置内部で発生した
熱を効率的にマザーボード等の半導体装置外部へ放出することが可能になる。 Furthermore, lower heat radiation pads 137, 147 and metal balls 160 are provided on the lower surface of the wiring board 100 below the vias 138, 148.
By joining to a motherboard having a larger heat capacity than 0 or the like, it is possible to efficiently release the heat generated inside the semiconductor device to the outside of the semiconductor device such as the motherboard.

次に、図５乃至図７を参照して、本発明の実施例２に係るチップスタック構造の半導体
装置について説明する。図５は本発明の実施例２に係る半導体装置の上面図、図６は本発
明の実施例２に係る半導体装置の下面図、図７（ａ）は図５の一点鎖線Ｃ−Ｃ’における
断面図、図７（ｂ）は図５の一点鎖線Ｄ−Ｄ’における断面図である。 Next, a semiconductor device having a chip stack structure according to a second embodiment of the present invention will be described with reference to FIGS. 5 is a top view of the semiconductor device according to the second embodiment of the present invention, FIG. 6 is a bottom view of the semiconductor device according to the second embodiment of the present invention, and FIG. 7A is a one-dot chain line CC ′ in FIG. FIG. 7B is a cross-sectional view taken along one-dot chain line DD ′ in FIG.

本実施例に係る半導体装置は、上述した実施例１に係る半導体装置とはスペーサ２１０
及び第二の放熱手段２４５の構成が異なるが、他の構成については実施例１とほぼ同様で
あるため、同様の構成については同一符号を付して詳細な説明を省略する。また、本実施
例に係る半導体装置の製造方法に関しては、上記した実施例１に係る半導体装置の製造方
法とほぼ同一であるため説明は省略する。 The semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment described above with the spacer 210.
Although the configuration of the second heat dissipating means 245 is different, the other configurations are substantially the same as those of the first embodiment, and therefore the same configurations are denoted by the same reference numerals and detailed description thereof is omitted. Further, the manufacturing method of the semiconductor device according to the present embodiment is substantially the same as the manufacturing method of the semiconductor device according to the first embodiment described above, and therefore the description thereof is omitted.

本実施例に係る半導体装置では、配線基板１００中央部の第一の放熱手段１３５上には
、第一の電極１０６を有する第一の半導体チップ１０５が接着剤１０１を介して搭載され
ており、第一の半導体チップ１０５上には、接着剤１０２を介してスペーサ２１０が搭載
されており、スペーサ２１０上には、接着剤１０３を介して第二の電極１２１を有する第
二の半導体チップ１２０が搭載されている。 In the semiconductor device according to the present embodiment, the first semiconductor chip 105 having the first electrode 106 is mounted on the first heat dissipating means 135 in the center of the wiring substrate 100 via the adhesive 101, A spacer 210 is mounted on the first semiconductor chip 105 via an adhesive 102, and a second semiconductor chip 120 having a second electrode 121 via an adhesive 103 is mounted on the spacer 210. It is installed.

また、第一及び第二の半導体チップ１０５、１２０の第一及び第二の電極１０６、１２
１は、それぞれ矩形平面形状の配線基板１００の一方の相対する２辺に沿って設けられた
、実施例１と同様の信号供給手段１５５の上部電極パッド１５６に金属ワイヤ１２５によ
って電気的に接続され、さらに配線基板１００上で、封止体１３０により第一の半導体チ
ップ１０５、スペーサ２１０、第二の半導体チップ１２０及び金属ワイヤ１２５（接続部
材１２５）が封止され、また下部放熱用パッド１３７、２４７、下部電極パッド１５７に
それぞれ金属ボール１６０が設けられている。 The first and second electrodes 106 and 12 of the first and second semiconductor chips 105 and 120 are also shown.
1 is electrically connected by metal wires 125 to the upper electrode pads 156 of the signal supply means 155 similar to the first embodiment, which are provided along one opposite two sides of the wiring board 100 having a rectangular planar shape. Further, on the wiring substrate 100, the first semiconductor chip 105, the spacer 210, the second semiconductor chip 120, and the metal wire 125 (connection member 125) are sealed by the sealing body 130, and the lower heat radiation pad 137, 247 and the lower electrode pad 157 are provided with metal balls 160, respectively.

そして、本実施例では、図５に示したように、スペーサ２１０は、矩形平面形状のチッ
プ搭載部２１１とチップ搭載部２１１の相対する側面からそれぞれ外方に延びる支持部２
１２とを備えた形状を有している。支持部２１２は、外方に向かうに従って幅が拡がるよ
うに形成され、その端部は配線基板１００の他方の相対する２辺とほぼ同じ長さを有する
帯状に形成され、配線基板１００上面のこの相対する２辺に沿ってそれぞれ固定部材１１
５により固定されている。 In this embodiment, as shown in FIG. 5, the spacer 210 has a rectangular planar chip mounting portion 211 and a support portion 2 that extends outward from the opposing side surfaces of the chip mounting portion 211.
12. The support portion 212 is formed so that its width increases toward the outside, and its end portion is formed in a strip shape having substantially the same length as the other two opposite sides of the wiring substrate 100, Each of the fixing members 11 along two opposite sides
5 is fixed.

また、このスペーサ２１０の支持部２１２の端部直下の配線基板１００部分には、第二
の放熱手段２４５が設けられている。 A second heat radiating means 245 is provided on the portion of the wiring board 100 immediately below the end of the support portion 212 of the spacer 210.

この第二の放熱手段２４５は、帯状の上、下部放熱用パッド２４６、２４７と、この上
、下部放熱用パッド２４６、２４７間に設けられた複数のビア２４８とで構成され、各ビ
ア２４８は、実施例１と同様に、ビアホール２４９、めっき層２５０、プラグ２５１で構
成されている。 The second heat radiating means 245 includes a belt-like upper and lower heat radiating pads 246 and 247 and a plurality of vias 248 provided between the lower heat radiating pads 246 and 247. As in the first embodiment, the via hole 249, the plating layer 250, and the plug 251 are included.

上記した本実施例に係る半導体装置では、第一及び第二の半導体チップ１０５、１２０
で発生した熱を、第一の半導体チップ１０５直下の放熱経路のみならず、スペーサ２１０
からの放熱経路によっても、直接、配線基板１００へ伝達して逃がすことができるため、
従来の半導体装置に比べ放熱経路が増加することから、高い放熱効果を得ることができる
。 In the semiconductor device according to the above-described embodiment, the first and second semiconductor chips 105 and 120 are used.
In addition to the heat dissipation path directly below the first semiconductor chip 105, the heat generated in step S210 is not limited to the spacer 210.
Because it can be directly transmitted to the wiring board 100 through the heat dissipation path from the
Since the heat radiation path is increased as compared with the conventional semiconductor device, a high heat radiation effect can be obtained.

しかも、本実施例に係る半導体装置では、スペーサ２１０の支持部２１２が配線基板１
００の辺とほぼ同じ長さを有する帯状に形成されている。そのため、上述の実施例１に係
る半導体装置のスペーサ１１０の支持部１１２の端部と配線基板１００との固定部面積Ｓ
１（図１参照）に比べ、図５に示したように、本実施例に係る半導体装置のスペーサ２１
０の支持部２１２端部と配線基板１００との固定部面積Ｓ２は大きくなっている。スペー
サ１１０から配線基板１００への熱伝導性は、スペーサ１１０、２１０と配線基板１００
の固定部面積の大きさに大きく依存し、固定部面積が大きいほド高くなる。従って、本実
施例に係る半導体装置では、上述した実施例１に係る半導体装置よりも、スペーサ２１０
から配線基板１００への放熱効果をさらに向上することができる。 Moreover, in the semiconductor device according to this embodiment, the support portion 212 of the spacer 210 is the wiring board 1.
It is formed in a strip shape having substantially the same length as the 00 side. Therefore, the fixed portion area S between the end portion of the support portion 112 of the spacer 110 and the wiring substrate 100 of the semiconductor device according to the first embodiment described above.
1 (see FIG. 1), as shown in FIG. 5, the spacer 21 of the semiconductor device according to the present embodiment.
Fixing portion area S 2 of the support portion 212 ends and the wiring board 100 of 0 is larger. The thermal conductivity from the spacer 110 to the wiring board 100 is such that the spacers 110 and 210 and the wiring board 100
It largely depends on the size of the fixed portion area, and the larger the fixed portion area, the higher the height. Accordingly, in the semiconductor device according to the present embodiment, the spacer 210 is more than the semiconductor device according to the first embodiment described above.
The heat dissipation effect from the wiring to the wiring board 100 can be further improved.

次に、図８及び図９を参照して、本発明の実施例３に係るチップスタック構造の半導体
装置について説明する。図８は本発明の実施例３に係る半導体装置の上面図、図９は図８
の一点鎖線Ｅ−Ｅ’における断面図である。本実施例に係る半導体装置は、上記した実施
例に係る半導体装置とは、スペーサと第二の放熱手段との固定部分の構造が異なり、他の
構造については上記実施例とほぼ同様であるので、同様の構成については、同一符号を付
して詳細な説明は省略する。 Next, with reference to FIG. 8 and FIG. 9, a semiconductor device having a chip stack structure according to Embodiment 3 of the present invention will be described. FIG. 8 is a top view of the semiconductor device according to the third embodiment of the present invention, and FIG.
It is sectional drawing in dashed-dotted line EE '. The semiconductor device according to the present embodiment is different from the semiconductor device according to the above-described embodiment in the structure of the fixing portion between the spacer and the second heat radiation means, and the other structure is substantially the same as the above-described embodiment. The same components are denoted by the same reference numerals and detailed description thereof is omitted.

上記実施例１、２では、スペーサ１１０、２１０の支持部１１２、２１２の端部は、配
線基板１００の上面に形成された第二の放熱手段１４５、２４５の上部放熱用パッド１４
６、２４６に固定されているが、本実施例では、図８及び図９に示すように、第二の放熱
手段３４５は、複数のビア１４８と下部放熱用パッド１４７とで構成され、上部放熱用パ
ッドは備えていない。複数のビア１４８は、それぞれビアホール１４９、めっき層１５０
、プラグ１５１によって構成されているが、その上部にはプラグ１５１が埋め込まれてお
らず、開口部が配線基板１００の上面に露呈された構造となっている。 In the first and second embodiments, the end portions of the support portions 112 and 212 of the spacers 110 and 210 are the upper heat radiation pads 14 of the second heat radiation means 145 and 245 formed on the upper surface of the wiring substrate 100.
In this embodiment, as shown in FIGS. 8 and 9, the second heat radiation means 345 includes a plurality of vias 148 and a lower heat radiation pad 147. There is no pad for use. The plurality of vias 148 include a via hole 149 and a plating layer 150, respectively.
The plug 151 has a structure in which the plug 151 is not embedded in the upper portion of the plug 151 and the opening is exposed on the upper surface of the wiring substrate 100.

また本実施例に係るスペーサ３１０は、上記実施例1、２と同様の形状のチップ搭載部
３１１と支持部３１２を有するが、支持部３１２の端部には第二の放熱手段３４５の各ビ
ア１４８と同数の突出片３１３が設けられている。 The spacer 310 according to the present embodiment includes a chip mounting portion 311 and a support portion 312 having the same shape as those of the first and second embodiments, but each via of the second heat radiating means 345 is provided at the end of the support portion 312. As many projection pieces 313 as 148 are provided.

そして、スペーサ３１０は、支持部３１２の突出片３１３が各ビア１４８の開口部にそ
れぞれ挿入されて、突出片３１３を覆うように開口部に埋め込まれた固定材料１１５によ
り第二の放熱手段３４５に固定されている。 Then, the spacer 310 has the protruding piece 313 of the support portion 312 inserted into the opening of each via 148, and the second heat radiating means 345 is fixed by the fixing material 115 embedded in the opening so as to cover the protruding piece 313. It is fixed.

上記した本実施例の半導体装置においても、上記実施例１と同様に、第一及び第二の半
導体チップ１０５、１２０で発生した熱を、第一の半導体チップ１０５直下の放熱経路の
みならず、スペーサ３１０及びビア１４８による放熱経路を介して配線基板１００外部に
放出する。従って、従来の半導体装置に比べ放熱経路が増加することから、高い放熱効果
を得ることができる。 Also in the semiconductor device of the present embodiment described above, the heat generated in the first and second semiconductor chips 105, 120 is not limited to the heat dissipation path directly below the first semiconductor chip 105, as in the first embodiment. It is discharged to the outside of the wiring board 100 through a heat dissipation path by the spacer 310 and the via 148. Therefore, since the heat radiation path is increased as compared with the conventional semiconductor device, a high heat radiation effect can be obtained.

また、本実施例では、上部放熱用パッドを省略するため、上記実施例１、２に比べて半
導体装置の製造を簡略化することができる。 Further, in this embodiment, since the upper heat radiation pad is omitted, the manufacturing of the semiconductor device can be simplified as compared with the first and second embodiments.

次に、図１０を参照して、本発明の実施例４に係るチップスタック構造の半導体装置に
ついて説明する。図１０は本発明の実施例４に係る半導体装置のスペーサの支持部の要部
を示す側面図である。 Next, a semiconductor device having a chip stack structure according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a side view showing the main part of the support portion of the spacer of the semiconductor device according to the fourth embodiment of the present invention.

本実施例に係る半導体装置は、上述した実施例１乃至３に係る半導体装置において、ス
ペーサ１１０、２１０、３１０の支持部１１２、２１２、３１２にそれぞれ弾性部１１２
ａ、２１２ａ、３１２ａをそれぞれ設けたもので、他の構成については上記実施例１乃至
３とほぼ同様である。以下、説明に際しては、必要に応じて、図1乃至図９を用いて説明
する。 The semiconductor device according to the present embodiment is the same as the semiconductor device according to any of the first to third embodiments described above, but the elastic portions 112 are respectively provided to the support portions 112, 212, and 312 of the spacers 110, 210, and 310.
a, 212a and 312a are provided, and the other configurations are substantially the same as those of the first to third embodiments. Hereinafter, description will be made with reference to FIGS. 1 to 9 as necessary.

図１０に示すように、本実施例の半導体装置では、上記実施例１乃至３に係る半導体装
置において、スペーサ１１０、２１０、３１０の支持部１１２、２１２、３１２の一部、
すなわちスペーサ１１０、２１０、３１０のチップ搭載部１１１、２１１、３１１と支持
部１１２、２１２、３１２の端部との間の支持部１１２、２１２、３１２部分に弾性部１
１２ａ、２１２ａ、３１２ａが形成されている。 As shown in FIG. 10, in the semiconductor device of this example, in the semiconductor device according to Examples 1 to 3, a part of the support portions 112, 212, and 312 of the spacers 110, 210, and 310,
That is, the elastic portion 1 is formed on the support portions 112, 212, 312 between the chip mounting portions 111, 211, 311 of the spacers 110, 210, 310 and the end portions of the support portions 112, 212, 312.
12a, 212a, 312a are formed.

この弾性部１１２ａ、２１２ａ、３１２ａは、例えば、図１０（ａ）に示すように、ス
ペーサ１１０、２１０、３１０のチップ搭載部１１１、２１１、３１１と支持部１１２、
２１２、３１２の端部との間の支持部１１２、２１２、３１２部分を凹凸状に屈曲させる
ことにより形成される。また、図１０（ｂ）に示すように、弾性部１１２ａ、２１２ａ、
３１２ａは、支持部１１２、２１２、３１２部分の一部に切り込みを設け、厚さを薄くす
ることによって形成されてもよい。 For example, as shown in FIG. 10A, the elastic portions 112a, 212a, and 312a include chip mounting portions 111, 211, and 311 of the spacers 110, 210, and 310, and the support portion 112,
It is formed by bending the support portions 112, 212, 312 between the ends of 212, 312 in an uneven shape. Further, as shown in FIG. 10B, the elastic portions 112a, 212a,
312a may be formed by providing a cut in a part of the support portions 112, 212, 312 and reducing the thickness.

上記した本実施例の半導体装置では、スペーサ１１０、２１０、３１０の支持部１１２
、２１２、３１２の一部に弾性部１１２ａ、２１２ａ、３１２ａを設けているので、配線
基板１００とスペーサ１１０、２１０、３１０と封止体１３０との熱膨張差により発生す
るスペーサ１１０、２１０、３１０にかかる応力を緩和することが可能となる。 In the semiconductor device of this embodiment described above, the support portions 112 of the spacers 110, 210, and 310 are used.
, 212, 312 are provided with elastic portions 112 a, 212 a, 312 a, so that the spacers 110, 210, 310 generated by the difference in thermal expansion between the wiring substrate 100, the spacers 110, 210, 310, and the sealing body 130. It is possible to relieve the stress applied to the film.

従って、スペーサ１１０、２１０、３１０と配線基板１００の固定部を外部応力から保
護することができるため、スペーサ１１０、２１０、３１０から配線基板１００への安定
した放熱を確保することが可能となる。 Accordingly, since the fixing portions of the spacers 110, 210, 310 and the wiring board 100 can be protected from external stress, it is possible to ensure stable heat radiation from the spacers 110, 210, 310 to the wiring board 100.

本発明は上述した各実施例に限定されるものではなく、発明の要旨を逸脱しない範囲で
種々変更して、実施することができる。例えば、各実施例では、配線基板上方に第一の半
導体チップと第二の半導体チップの二つの半導体チップのみを搭載した半導体装置につい
て説明したが、各実施例に係る半導体装置において、積層される半導体チップ間にそれぞ
れスペーサを挟持させつつ、３以上の半導体チップを配線基板上方に搭載することもでき
る。このような３以上の半導体チップを積層する半導体装置においては、スペーサのうち
少なくとも一つを配線基板に固定させることにより、半導体装置の放熱効果を高めること
ができる。 The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention. For example, in each embodiment, the semiconductor device in which only two semiconductor chips, the first semiconductor chip and the second semiconductor chip, are mounted above the wiring board has been described. However, in the semiconductor device according to each embodiment, the semiconductor devices are stacked. It is also possible to mount three or more semiconductor chips above the wiring board while sandwiching spacers between the semiconductor chips. In such a semiconductor device in which three or more semiconductor chips are stacked, the heat dissipation effect of the semiconductor device can be enhanced by fixing at least one of the spacers to the wiring board.

また、各実施例に係る半導体装置では、スペーサと配線基板の固定部は、配線基板の隅
部または配線基板の対向する２辺に沿って設けたが、これに限定されることなく、半導体
装置に求められる放熱特性に合わせて、さらにボンディングされた金属ワイヤに接触しな
い範囲で、スペーサの形状またはスペーサと配線基板の固定部の位置を適宜変化させるこ
とにより、スペーサと配線基板の固定部の面積を変更してもよい。また、第一及び第二の
放熱手段の上、下部放熱用パッドの形状やビア径についても、スペーサと同様、半導体装
置に求められる放熱特性等に合わせて、適宜変えてもよい。 In the semiconductor device according to each embodiment, the spacer and the fixing portion of the wiring board are provided along the corner of the wiring board or the two opposite sides of the wiring board. However, the semiconductor device is not limited to this. The area of the spacer and the fixed part of the wiring board can be changed by appropriately changing the shape of the spacer or the position of the fixed part of the spacer and the wiring board within a range not contacting the bonded metal wire in accordance with the heat dissipation characteristics required for May be changed. Further, the shape and via diameter of the lower heat dissipating pad on the first and second heat dissipating means may be appropriately changed in accordance with the heat dissipating characteristics required for the semiconductor device as in the case of the spacer.

本発明の実施例１に係る半導体装置の封止体を透視した状態を示す上面図。The top view which shows the state which saw through the sealing body of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の下面図。1 is a bottom view of a semiconductor device according to Embodiment 1 of the present invention. 本発明の実施例１に係る半導体装置のＡ−Ａ’線、Ｂ−Ｂ’線における断面図。Sectional drawing in the A-A 'line | wire and B-B' line | wire of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体装置の製造方法を示す工程断面図。Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. 本発明の実施例２に係る半導体装置の封止体を透視した状態の構成を示す上面図。The top view which shows the structure of the state which saw through the sealing body of the semiconductor device which concerns on Example 2 of this invention. 本発明の実施例２に係る半導体装置の下面図。FIG. 6 is a bottom view of a semiconductor device according to Embodiment 2 of the present invention. 本発明の実施例３に係る半導体装置のＣ−Ｃ’線、Ｄ−Ｄ’線における断面図。Sectional drawing in the C-C 'line | wire and D-D' line | wire of the semiconductor device which concerns on Example 3 of this invention. 本発明の実施例３に係る半導体装置の封止体を透視した状態の構成を示す上面図。The top view which shows the structure of the state which saw through the sealing body of the semiconductor device which concerns on Example 3 of this invention. 本発明の実施例３に係る半導体装置のＥ−Ｅ’線における断面図。Sectional drawing in the E-E 'line of the semiconductor device which concerns on Example 3 of this invention. 本発明の実施例４に係る半導体装置におけるスペーサ支持部の形状を示す概略図。Schematic which shows the shape of the spacer support part in the semiconductor device which concerns on Example 4 of this invention.

符号の説明Explanation of symbols

１００・・・配線基板
１０５・・・第一の半導体チップ
１０６・・・第一の電極
１１０、２１０、３１０・・・スペーサ
１１１、２１１、３１１・・・スペーサのチップ搭載部
１１２、２１２、３１２・・・スペーサの支持部
１１２ａ、２１２ａ、３１２ａ・・・スペーサの弾性部
１１５・・・固定部材
１２０・・・第二の半導体チップ
１２１・・・第二の電極
１２５・・・接続部材（金属ワイヤ）
１３０・・・封止体
１３５・・・第一の放熱手段
１３８、１４８・・・放熱用ビア
１４５、２４５、３４５・・・第二の放熱手段
１５５・・・信号供給手段 DESCRIPTION OF SYMBOLS 100 ... Wiring board 105 ... 1st semiconductor chip 106 ... 1st electrode 110, 210, 310 ... Spacer 111, 211, 311 ... Spacer chip mounting part 112, 212, 312 ... spacer support parts 112a, 212a, 312a ... spacer elastic part 115 ... fixing member 120 ... second semiconductor chip 121 ... second electrode 125 ... connection member (metal Wire)
130 ... Sealing body 135 ... First heat radiation means 138, 148 ... Heat radiation vias 145, 245, 345 ... Second heat radiation means 155 ... Signal supply means

Claims (7)

配線基板と、
前記配線基板上に搭載された第一の半導体チップと、
チップ搭載部と前記チップ搭載部より外方に延びた支持部とを有し、前記チップ搭載部が
前記第一の半導体チップ上に搭載され、前記支持部が前記配線基板に固定されたスペーサ
と、
前記スペーサの前記チップ搭載部上に搭載された第二の半導体チップと、
前記配線基板と前記第一及び第二の半導体チップとを電気的に接続する接続部材と、
前記配線基板上で前記第一の半導体チップ、前記スペーサ、前記第二の半導体チップ及び
前記接続部材を封止する、前記スペーサよりも熱伝導率の低い封止体と、
を備えたことを特徴とする半導体装置。 A wiring board;
A first semiconductor chip mounted on the wiring board;
A spacer having a chip mounting portion and a support portion extending outward from the chip mounting portion, the chip mounting portion being mounted on the first semiconductor chip, and the support portion being fixed to the wiring board; ,
A second semiconductor chip mounted on the chip mounting portion of the spacer;
A connection member for electrically connecting the wiring board and the first and second semiconductor chips;
A sealing body that seals the first semiconductor chip, the spacer, the second semiconductor chip, and the connection member on the wiring board, and has a lower thermal conductivity than the spacer;
A semiconductor device comprising: 第一の放熱手段を有し、かつ前記第一の放熱手段の外縁部に信号供給手段及び第二の放熱
手段を有する配線基板と、
前記配線基板の前記第一の放熱手段上に搭載された、第一の電極を有する第一の半導体チ
ップと、
チップ搭載部と前記チップ搭載部より外方に延びた支持部とを有し、前記チップ搭載部が
前記第一の半導体チップ上に搭載され、前記支持部の端部が前記配線基板の前記第二の放
熱手段に固定されたスペーサと、
前記スペーサの前記チップ搭載部上に搭載された、第二の電極を有する第二の半導体チッ
プと、
前記配線基板の前記信号供給手段と前記第一及び第二の半導体チップの前記第一及び前記
第二の電極とをそれぞれ電気的に接続する接続部材と、
前記配線基板上で前記第一の半導体チップ、前記スペーサ、前記第二の半導体チップ及び
前記接続部材を封止する、前記スペーサよりも熱伝導率の低い封止体と、
を備えたことを特徴とする半導体装置。 A wiring board having a first heat dissipating means and having a signal supplying means and a second heat dissipating means at the outer edge of the first heat dissipating means;
A first semiconductor chip having a first electrode mounted on the first heat dissipation means of the wiring board;
A chip mounting portion and a support portion extending outward from the chip mounting portion, wherein the chip mounting portion is mounted on the first semiconductor chip, and an end portion of the support portion is the first portion of the wiring board. A spacer fixed to the second heat dissipation means;
A second semiconductor chip having a second electrode mounted on the chip mounting portion of the spacer;
A connection member for electrically connecting the signal supply means of the wiring board and the first and second electrodes of the first and second semiconductor chips, respectively.
A sealing body that seals the first semiconductor chip, the spacer, the second semiconductor chip, and the connection member on the wiring board, and has a lower thermal conductivity than the spacer;
A semiconductor device comprising: 前記第一及び第二の放熱手段は、前記配線基板を上下に貫通するビアを有することを特徴
とする請求項２記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the first and second heat radiating means have vias that vertically penetrate the wiring board. 前記配線基板及び前記スペーサの前記チップ搭載部は矩形平面形状であり、前記スペーサ
の前記支持部は、前記チップ搭載部の角部から前記チップ搭載部の外方に延びており、前
記配線基板の隅部に固定されることを特徴とする請求項１乃至３のいずれか一項記載の半
導体装置。 The chip mounting portion of the wiring substrate and the spacer has a rectangular planar shape, and the support portion of the spacer extends outward from the chip mounting portion from a corner portion of the chip mounting portion. 4. The semiconductor device according to claim 1, wherein the semiconductor device is fixed to a corner. 前記配線基板及び前記スペーサの前記チップ搭載部は矩形平面形状であり、前記スペーサ
の前記支持部は、前記チップ搭載部の相対する側面から前記チップ搭載部の外方に延びて
おり、前記配線基板上面の相対する２辺に沿って固定部が帯状になるように前記配線基板
に固定されることを特徴とする請求項１乃至３のいずれか一項記載の半導体装置。 The chip mounting portion of the wiring substrate and the spacer has a rectangular planar shape, and the support portion of the spacer extends outward from the chip mounting portion from an opposite side surface of the chip mounting portion. 4. The semiconductor device according to claim 1, wherein the semiconductor device is fixed to the wiring substrate so that the fixing portion has a strip shape along two opposite sides of the upper surface. 5. 前記スペーサは、前記封止体よりも弾性率の低い固定部材によって、前記配線基板に固定
されていることを特徴とする請求項１乃至５のいずれか一項記載の半導体装置。 The semiconductor device according to claim 1, wherein the spacer is fixed to the wiring board by a fixing member having a lower elastic modulus than the sealing body. 前記スペーサは、前記支持部の少なくとも一部に弾性部を有することを特徴とする請求項
１乃至６のいずれか一項記載の半導体装置。 The semiconductor device according to claim 1, wherein the spacer includes an elastic portion in at least a part of the support portion.
JP2006105744A 2006-04-06 2006-04-06 Semiconductor device Pending JP2007281201A (en)

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Publication Number Publication Date
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011122228A1 (en) * 2010-03-31 2011-10-06 日本電気株式会社 Substrate with built-in semiconductor
JP2013219183A (en) * 2012-04-09 2013-10-24 Canon Inc Lamination type semiconductor device, printed circuit board, and manufacturing method of lamination type semiconductor device
JP2015012170A (en) * 2013-06-28 2015-01-19 キヤノン株式会社 Stacked-type semiconductor device, printed circuit board, and method of manufacturing stacked-type semiconductor device
JP2015135875A (en) * 2014-01-16 2015-07-27 株式会社東芝 Semiconductor package, and electronic apparatus
CN107359150A (en) * 2016-05-09 2017-11-17 艾马克科技公司 Semiconductor packages and its manufacture method
JP2018093230A (en) * 2018-03-05 2018-06-14 東芝メモリ株式会社 Storage device and electronic apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011122228A1 (en) * 2010-03-31 2011-10-06 日本電気株式会社 Substrate with built-in semiconductor
JP2013219183A (en) * 2012-04-09 2013-10-24 Canon Inc Lamination type semiconductor device, printed circuit board, and manufacturing method of lamination type semiconductor device
EP2650917A3 (en) * 2012-04-09 2016-10-12 Canon Kabushiki Kaisha Multilayered semiconductor device, printed circuit board, and method of manufacturing multilayered semiconductor device
JP2015012170A (en) * 2013-06-28 2015-01-19 キヤノン株式会社 Stacked-type semiconductor device, printed circuit board, and method of manufacturing stacked-type semiconductor device
JP2015135875A (en) * 2014-01-16 2015-07-27 株式会社東芝 Semiconductor package, and electronic apparatus
CN107359150A (en) * 2016-05-09 2017-11-17 艾马克科技公司 Semiconductor packages and its manufacture method
CN107359150B (en) * 2016-05-09 2023-09-01 艾马克科技公司 Semiconductor package and method of manufacturing the same
JP2018093230A (en) * 2018-03-05 2018-06-14 東芝メモリ株式会社 Storage device and electronic apparatus

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