JP2012231165A - Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates - Google Patents

Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates Download PDF

Info

Publication number
JP2012231165A
JP2012231165A JP2012153053A JP2012153053A JP2012231165A JP 2012231165 A JP2012231165 A JP 2012231165A JP 2012153053 A JP2012153053 A JP 2012153053A JP 2012153053 A JP2012153053 A JP 2012153053A JP 2012231165 A JP2012231165 A JP 2012231165A
Authority
JP
Japan
Prior art keywords
layer
sige
sige layer
silicon
amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012153053A
Other languages
Japanese (ja)
Other versions
JP5601595B2 (en
Inventor
Bauer Matthias
マティアス バウアー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASM America Inc
Original Assignee
ASM America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASM America Inc filed Critical ASM America Inc
Publication of JP2012231165A publication Critical patent/JP2012231165A/en
Application granted granted Critical
Publication of JP5601595B2 publication Critical patent/JP5601595B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02499—Monolayers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide methods for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects.SOLUTION: Amorphous SiGe layers 600 are deposited on at least one monolayer of a dopant by CVD from trisilane and GeH. The amorphous SiGe layers 600 are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also cause diffusion of germanium to dilute the overall germanium content and essentially consume silicon 500 overlying an insulator. The SPE process can be conducted with or without diffusion of germanium into the underlying silicon 500, and so is applicable to SOI as well as conventional semiconductor substrates.

Description

発明の分野
本発明は、一般に、集積回路製造における、シリコンゲルマニウム−オン−インシュレーター（ｓｉｌｉｃｏｎ−ｇｅｒｍａｎｉｕｍ−ｏｎ−ｉｎｓｕｌａｔｏｒ）（「ＳＧＯＩ」）技術を含む、歪み緩和（ｓｔｒａｉｎ ｒｅｌａｘｅｄ）シリコンゲルマニウム上のストレインドシリコン（ｓｔｒａｉｎｅｄ ｓｉｌｉｃｏｎ）に関する。 FIELD OF THE INVENTION The present invention generally relates to a strain relaxed on strain relaxed silicon germanium, including silicon-germanium-on-insulator (“SGOI”) technology in integrated circuit manufacturing. It relates to silicon (strained silicon).

発明の背景技術
デバイスパフォーマンスを改善するために、従来の「バルク」シリコンウエハを、いわゆるシリコン−オン−インシュレーター（「ＳＯＩ」）ウエハに置換することが開発される傾向にある。ＳＯＩ技術の利点は、トランジスタが作られるシリコンがウエハの残りの部分と電気的接触しておらず、その結果、トランジスタ間でのクロストーク（ｃｒｏｓｓ−ｔａｌｋ）がウエハバルクを通して生じないことである。これらのトランジスタは、互いからより有効に電気的に絶縁される。 Background of the Invention In order to improve device performance, there is a trend towards replacing conventional “bulk” silicon wafers with so-called silicon-on-insulator (“SOI”) wafers. The advantage of SOI technology is that the silicon from which the transistors are made is not in electrical contact with the rest of the wafer so that cross-talk between the transistors does not occur through the wafer bulk. These transistors are more effectively electrically isolated from each other.

ＳＯＩ技術は、代表的には、アクティブ半導体層とウエハとの間の、ウエハの全体を横切った、または少なくともアクティブデバイスが半導体層中で形成されるエリアにおいて、薄い（例えば、約１００ｎｍ）絶縁層を使用する。酸化ケイ素、窒化ケイ素またはこれら２つのコンビネーションは、絶縁層として典型的に使用される。これらの材料はアモルファスであり、優れた電気的な特性を有し、そして窒化ケイ素及び／または酸化ケイ素を集積するための技術は非常によく開発されている。   SOI technology typically involves a thin (eg, about 100 nm) insulating layer between the active semiconductor layer and the wafer, across the entire wafer, or at least in areas where active devices are formed in the semiconductor layer. Is used. Silicon oxide, silicon nitride or a combination of the two are typically used as the insulating layer. These materials are amorphous, have excellent electrical properties, and techniques for integrating silicon nitride and / or silicon oxide are very well developed.

ＳＯＩ構造を形成する２つの従来技術が開発されている。ＳＩＭＯＸとして知られている１つの技術は、シリコンウエハのような半導体構造を用いて開始し、そして酸素原子の高エネルギー注入を使用して、シリコンウエハ表面下に、約１００ｎｍより大きな酸化被膜を形成する。次いで、高温のアニーリングによって、内部に（ｂｕｒｉｅｄ）酸化ケイ素が形成され、そして同時に注入により作製された表面のシリコン中の結晶欠陥を修復する。表面のシリコンは、半導体材料のままであり、そしてその結晶構造はアニーリングプロセスによって回復する。しかし、これらのステップは、幾分高価であり、そして絶縁層及びその上のアクティブシリコンの品質は幾分か悪い。   Two prior art techniques for forming SOI structures have been developed. One technique, known as SIMOX, starts with a semiconductor structure such as a silicon wafer, and uses high energy implantation of oxygen atoms to form an oxide film larger than about 100 nm below the silicon wafer surface. To do. High temperature annealing then forms a buried silicon oxide and simultaneously repairs the crystal defects in the surface silicon produced by implantation. The surface silicon remains a semiconductor material and its crystal structure is recovered by the annealing process. However, these steps are somewhat expensive and the quality of the insulating layer and the active silicon on it is somewhat poor.

ＳＯＩ構造を形成するための別の方法は、酸化したシリコンウエハ上に犠牲シリコンウエハ（ｓａｃｒｉｆｉｃｉａｌ ｓｉｌｉｃｏｎ ｗａｆｅｒ）をボンディングすることに基づく。研削または他のシンニングプロセス（ｔｈｉｎｎｉｎｇ ｐｒｏｃｅｓｓ）によって、犠牲シリコンウエハが薄くされて、他方の基板の酸化物上の、非常に薄いアクティブ半導体層となる。しかし、アクティブ半導体層の最終的に所望される厚さの均一性が５ｎｍ±０．１ｎｍであるので、シンニングプロセスは、ＳＯＩ構造における高品質を達成するのに決定的に重要である。さらに、ボンディング及びシンニングのプロセスは複雑であり、やや高価である。   Another method for forming an SOI structure is based on bonding a sacrificial silicon wafer onto an oxidized silicon wafer. By grinding or other thinning process, the sacrificial silicon wafer is thinned into a very thin active semiconductor layer on the oxide of the other substrate. However, since the final desired thickness uniformity of the active semiconductor layer is 5 nm ± 0.1 nm, the thinning process is critical to achieving high quality in the SOI structure. Furthermore, the bonding and thinning processes are complex and somewhat expensive.

ストレインドシリコンは、キャリア移動度、ひいてはトランジスタの演算速度を増加させるために利用される。代表的には、シリコンゲルマニウム（ＳｉＧｅ）の薄層が基板上に形成され、そしてシリコンの非常に薄い層がＳｉＧｅ上に堆積される。シリコンはゲルマニウムより小さな格子定数を有し、そしてシリコン層が緩和ＳｉＧｅ上で成長する場合、ケイ素原子は、下地層においてより広く原子間隔を置いて整列する傾向がある。その結果、最上部のシリコン層は伸ばされるか、または歪んで、電気的キャリアがより少ない抵抗で流れること可能にしている。   Strained silicon is used to increase the carrier mobility and thus the computational speed of the transistor. Typically, a thin layer of silicon germanium (SiGe) is formed on the substrate and a very thin layer of silicon is deposited on the SiGe. Silicon has a smaller lattice constant than germanium, and when the silicon layer is grown on relaxed SiGe, the silicon atoms tend to align more widely apart in the underlying layer. As a result, the top silicon layer is stretched or distorted to allow electrical carriers to flow with less resistance.

ストレインドシリコン及びＳＯＩは相補的な技術であり、そしてＳｉＧｅ−オン−インシュレーター（ＳＧＯＩ）基板を作り上げるためのいくつかの試みがなされている。   Strained silicon and SOI are complementary technologies and several attempts have been made to create SiGe-on-insulator (SGOI) substrates.

発明の要旨
発明の１つの局面に従って、歪み緩和ＳｉＧｅ−オン−インシュレーター構造上にストレインドシリコンを形成するための方法は、ＣＶＤによってＳＯＩ基板上にアモルファスＳｉＧｅ層を形成すること、及びＳｉＧｅ層の融解を引き起こす温度で基板をアニーリングする工程を含んでいる。ＳｉＧｅ層由来のＧｅは、アニーリング温度で、下地のＳｉ層中に拡散し、酸化物上に緩和ＳｉＧｅ層をもたらす。 SUMMARY OF THE INVENTION In accordance with one aspect of the invention, a method for forming strained silicon on a strain relaxed SiGe-on-insulator structure includes forming an amorphous SiGe layer on an SOI substrate by CVD, and melting the SiGe layer. Annealing the substrate at a temperature that causes the. Ge from the SiGe layer diffuses into the underlying Si layer at the annealing temperature, resulting in a relaxed SiGe layer on the oxide.

本発明の別の局面に従って、基板上に歪み緩和ＳｉＧｅ層を形成するための方法は、前駆物質としてトリシランを用いるＣＶＤによって、シリコン層上に、アモルファスＳｉＧｅ層を堆積することを含む。固相エピタキシーは、シリコン層上にＳｉＧｅ層を結晶化させるために実施される。アモルファスのＳｉＧｅ層を堆積する前に、シリコン層は、幾分かの結晶シリコン領域を露出しながら、酸化物の１未満のモノレイヤーで覆われる。   In accordance with another aspect of the present invention, a method for forming a strain relaxation SiGe layer on a substrate includes depositing an amorphous SiGe layer on a silicon layer by CVD using trisilane as a precursor. Solid phase epitaxy is performed to crystallize the SiGe layer on the silicon layer. Prior to depositing the amorphous SiGe layer, the silicon layer is covered with less than one monolayer of oxide, exposing some crystalline silicon regions.

本発明のさらなる局面において、基板上のシリコン層上に歪み緩和ＳｉＧｅ層を形成する方法は、低温でのＳｉＧｅのヘテロエピタキシーを含む。好ましくは、ストレインドＳｉＧｅ層は、トリシラン及びゲルマニウム前駆物質からのＣＶＤによって堆積される。発泡剤（例えば、ＨまたはＨｅ）がＳｉ／ＳｉＧｅの界面または界面下に注入され、そしてＳｉＧｅ層がアニールされる。アニーリングの間、ＳｉＧｅ層は緩和する。ストレインドシリコン層は、引き続き、緩和したＳｉＧｅ層上に堆積することができる。   In a further aspect of the present invention, a method of forming a strain relaxed SiGe layer on a silicon layer on a substrate includes SiGe heteroepitaxy at low temperatures. Preferably, the strained SiGe layer is deposited by CVD from trisilane and germanium precursors. A blowing agent (eg, H or He) is injected at or below the Si / SiGe interface and the SiGe layer is annealed. During annealing, the SiGe layer relaxes. A strained silicon layer can subsequently be deposited on the relaxed SiGe layer.

本発明のこれら及び他の局面は、以下の詳細な説明及び添付の図面（これらは本発明を例示し、そして限定しないことを意味する）から容易に明らかになる。   These and other aspects of the invention will be readily apparent from the following detailed description and the accompanying drawings, which are meant to illustrate and not limit the invention.

図１は、シリコン−オン−インシュレーター（ＳＯＩ）ウエハ上へのアモルファスシリコンゲルマニウム（α−ＳｉＧｅ）層の堆積を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing the deposition of an amorphous silicon germanium (α-SiGe) layer on a silicon-on-insulator (SOI) wafer. 図２は、図１のα−ＳｉＧｅ層上へのアモルファスシリコン（αＳｉ）層の堆積を例示する。FIG. 2 illustrates the deposition of an amorphous silicon (αSi) layer on the α-SiGe layer of FIG. 図３は、図２のα−Ｓｉ層の酸化、または図１のα−ＳｉＧｅ層上へのＳｉＯ２の別個の堆積のいずれかによる、図１のα−ＳｉＧｅ層上へのシリコン酸化物の形成を例示する。FIG. 3 illustrates the formation of silicon oxide on the α-SiGe layer of FIG. 1 by either oxidation of the α-Si layer of FIG. 2 or separate deposition of SiO 2 on the α-SiGe layer of FIG. Is illustrated. 図４は、本発明の好ましい実施形態に従う融解／拡散プロセスを例示する。FIG. 4 illustrates a melting / diffusion process according to a preferred embodiment of the present invention. 図５は、融解／拡散プロセスの結果として緩和したＳｉＧｅ層を例示する。FIG. 5 illustrates a relaxed SiGe layer as a result of the melting / diffusion process. 図６は、ＳｉＧｅ層中のゲルマニウムの種々の異なる濃度について、固相エピタキシーの結晶化速度を例示するチャートである。FIG. 6 is a chart illustrating the crystallization rate of solid phase epitaxy for various different concentrations of germanium in the SiGe layer. 図７は、従来のエピタキシー及び好ましい実施形態に従う緩和ＳｉＧｅ層の形成を用いる欠陥密度対ゲルマニウム含量を例示する。FIG. 7 illustrates defect density versus germanium content using conventional epitaxy and the formation of a relaxed SiGe layer according to a preferred embodiment. 図８は、ＳｉＧｅ層の中のゲルマニウム濃度に対する融解及び凝固温度を例示する。FIG. 8 illustrates melting and solidification temperatures versus germanium concentration in the SiGe layer. 図９は、歪み緩和ＳｉＧｅ層上にストレインドシリコンを形成するための方法を例示するフローチャートである。FIG. 9 is a flowchart illustrating a method for forming strained silicon on a strain relaxed SiGe layer. 図１０は、歪み緩和ＳｉＧｅ層上にストレインドシリコンを形成するための別の方法を例示するフローチャートである。FIG. 10 is a flowchart illustrating another method for forming strained silicon on a strain relaxed SiGe layer. 図１１は、歪み緩和ＳｉＧｅ層上にストレインドシリコンを形成するためのさらなる方法を例示するフローチャートである。FIG. 11 is a flowchart illustrating a further method for forming strained silicon on a strain relaxed SiGe layer.

好ましい実施形態の詳細な説明
好ましいプロセス
本明細書中に用いられる場合、「単結晶」または、「エピタキシャル」は、主とする大きな結晶構造（その中に許容される数の欠陥を有していてもよい）を記述するために用いられる。当業者は、層の結晶度がアモルファスから多結晶、そして単結晶へと連続的に落ちることを理解している；当業者は、低密度の欠陥が存在していても、結晶構造が単結晶またはエピタキシャルと考えられ得る場合を容易に決定することができる。 Detailed Description of the Preferred Embodiment
Preferred Process As used herein, “single crystal” or “epitaxial” is used to describe a predominantly large crystal structure that may have an acceptable number of defects therein. Used for. The person skilled in the art understands that the crystallinity of the layer falls continuously from amorphous to polycrystalline and single crystal; the person skilled in the art knows that the crystal structure is single crystal even in the presence of low density defects. Or it can be easily determined when it can be considered epitaxial.

用語「アモルファス」は、例えば、本明細書中に記載される固相エピタキシー（ＳＰＥ）または融解プロセスによって、容易に再分配され得る小粒多結晶構造を包含する。   The term “amorphous” encompasses small grain polycrystalline structures that can be readily redistributed, for example, by solid phase epitaxy (SPE) or melting processes described herein.

エピタキシーとは、堆積層が下地層の結晶構造の延長としての役割を果たす堆積を示す。ヘテロエピタキシーは、下地層及び上層の堆積層が異なる材料のものである一種のエピタキシーである。   Epitaxy refers to deposition in which the deposited layer serves as an extension of the crystal structure of the underlying layer. Heteroepitaxy is a type of epitaxy in which the underlying layer and the upper deposited layer are of different materials.

ヘテロエピタキシー堆積技術は、当該分野において周知であり、実際、下地層と上層との間の格子の不整合によって結晶の歪みを形成することにおいて有利であると考えられている。典型的には、そのようなヘテロエピタキシャル層は、２つの層の格子定数が正確に整合しないように、単結晶シリコン構造上にシリコンゲルマニウムをエピタキシャリーに堆積することにより形成される。この歪みは、半導体構造内の電気的キャリア移動度を増加させ、それによりトランジスタの性能を増強するので、有利であると考えられている。ＳｉＧｅ障壁に基づく相補型金属酸化膜半導体電界効果トランジスタ（ＣＭＯＳ）について、価電子帯と伝導帯とのバンド不連続性が必要である。伸長方向に（ｔｅｎｓｉｌｙ）歪んだＳｉ及び圧縮方向に歪んだＳｉＧｅは、互い違いの（ｓｔａｇｇｅｒｅｄ）バンドオフセット（ｂａｎｄ ｏｆｆｓｅｔ）（タイプＩＩ ヘテロインターフェース）をもたらすが、Ｓｉ上のストレインドＳｉＧｅに関する伝導帯オフセットは無視できる。主要な挑戦の１つは、滑らかな表面形態及びより少ない欠陥を有する緩和ＳｉＧｅ構造の利用可能性である。   Heteroepitaxy deposition techniques are well known in the art and are indeed believed to be advantageous in forming crystal distortions due to lattice mismatch between the underlayer and the top layer. Typically, such heteroepitaxial layers are formed by epitaxially depositing silicon germanium on a single crystal silicon structure such that the lattice constants of the two layers do not match exactly. This distortion is considered advantageous because it increases the electrical carrier mobility in the semiconductor structure, thereby enhancing the performance of the transistor. For complementary metal oxide semiconductor field effect transistors (CMOS) based on SiGe barriers, a band discontinuity between the valence band and the conduction band is required. Tensilely strained Si and compressively strained SiGe result in a staggered band offset (type II heterointerface), while the conduction band offset for strained SiGe on Si is Can be ignored. One of the major challenges is the availability of relaxed SiGe structures with smooth surface morphology and fewer defects.

歪み緩和ＳｉＧｅを形成するための融解凝固プロセス（図９）
完全な歪み緩和ＳｉＧｅ層は、融解凝固プロセスを使用することによりＳＯＩ基板上に形成され得る。（その開示が本明細書中に参考として援用される、Ｓｕｇｉｉら、Ｊ．Ｖａｃ．Ｓｃｉ．Ｔｅｃｈｎｏｌ．Ｂ２０（５）：１８９１−１８９６（２００２）；Ｋｕｔｓｕｋａｋｅら、Ｊｐｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．４２：Ｌ２３２−Ｌ２３４（２００３）を参照のこと） ）。薄いＳｉＧｅ及びシリコン層が従来のＳＯＩウエハ上で成長し、最上部のシリコン層が酸化し、そして高温アニーリングが実施されて、ＳｉＧｅ層を部分的に融解する。凝固により歪み緩和ＳｉＧｅ層が製造される。この層は、ＳＯＩ基板上の最上部のシリコン層中へのゲルマニウムの拡散の結果として、均一な組成を有する。従って、緩和ＳｉＧｅ層は、ＳＯＩウエハの酸化物の直接上に残留する。得られる層は、好ましくは、約１×１０５ｃｍ−２未満、より好ましくは約１×１０３ｃｍ−２未満、そしてなおより好ましくは約１０００ｃｍ−２未満の欠陥密度を有する。不運にも、Ｋｕｔｓｕｋａｋｅ及びＳｕｇｉｉにより開示されるような分子線エピタキシー（ＭＢＥ）も従来の前駆物質を使用するＣＶＤも、この文脈におけるα−ＳｉＧｅの商業的に満足な堆積をすることができない。 Melt solidification process to form strain relaxed SiGe (Figure 9)
A complete strain relaxation SiGe layer can be formed on the SOI substrate by using a melt solidification process. (Sugii et al., J. Vac. Sci. Technol. B20 (5): 1891-1896 (2002), the disclosure of which is incorporated herein by reference; Kutsukake et al., Jpn. J. Appl. Phys. : See L232-L234 (2003)))). Thin SiGe and silicon layers are grown on a conventional SOI wafer, the top silicon layer is oxidized, and high temperature annealing is performed to partially melt the SiGe layer. A strain relaxation SiGe layer is produced by solidification. This layer has a uniform composition as a result of the diffusion of germanium into the top silicon layer on the SOI substrate. Thus, the relaxed SiGe layer remains directly on the oxide of the SOI wafer. The resulting layer preferably has a defect density of less than about 1 × 10 5 cm −2 , more preferably less than about 1 × 10 3 cm −2 , and even more preferably less than about 1000 cm −2 . Unfortunately, neither molecular beam epitaxy (MBE) as disclosed by Kutsukake and Sugii nor CVD using conventional precursors can produce commercially satisfactory deposition of α-SiGe in this context.

ここで、図１−５を参照して、好ましい実施形態に従う一般的方法が例示される。最初に、アモルファスまたは小粒状の多結晶ＳｉＧｅ層２００が、シリコン−オン−インシュレーター（ＳＯＩ）基板１００（図１）上に堆積される。ＳＯＩ基板は、例えば、ＳＯＩＴＥＣ（Ｂｅｒｎｉｎ，Ｆｒａｎｃｅ）から市販されている。アモルファスまたは小粒状多結晶ＳｉＧｅ層を堆積することによって、下地のシリコン層における欠陥の形成が回避される。   Referring now to FIGS. 1-5, a general method according to a preferred embodiment is illustrated. Initially, an amorphous or small granular polycrystalline SiGe layer 200 is deposited on a silicon-on-insulator (SOI) substrate 100 (FIG. 1). The SOI substrate is commercially available from, for example, SOITEC (Bernin, France). By depositing an amorphous or small granular polycrystalline SiGe layer, the formation of defects in the underlying silicon layer is avoided.

アモルファスまたは小粒状の多結晶のＳｉＧｅ層２００の堆積は、例えば、ＡＳＭ Ａｍｅｒｉｃａから入手可能なＥｐｓｉｌｏｎＴＭ ＣＶＤリアクタのようなリアクタ中で化学気相成長法（ＣＶＤ）によって実施される。好ましくは、堆積は、約３５０℃〜約７００℃、より好ましくは約４００℃〜約６００℃の温度で、そして約１Ｔｏｒｒ〜ほぼ大気圧、より好ましくは５０Ｔｏｒｒから７６０Ｔｏｒｒ、最も好ましくは７６０Ｔｏｒｒの圧力で、トリシラン（Ｓｉ３Ｈ８）及びＧｅＨ４（または他のゲルマニウム前駆物質）を原料とする。好ましくは、主なキャリアは、約２〜約１００ｓｌｍのフローレートのＨ２である。堆積されたＳｉＧｅ層のアモルファスまたは小粒状の多結晶の性質は、多数の異なる方法によって実現することができる。有利には、これらの条件（例えば、７６０Ｔｏｒｒ）の下での堆積は、５００℃で４０％［Ｇｅ］に関して３００Å／分より高く、または４７５℃で５０％［Ｇｅ］に関して２００Å／分より高く、より好ましくは３００Å／分より高い速度でα−ＳｉＧｅを製造することができる。 The deposition of the amorphous or small granular polycrystalline SiGe layer 200 is performed by chemical vapor deposition (CVD) in a reactor such as, for example, an Epsilon ™ CVD reactor available from ASM America. Preferably, the deposition is at a temperature from about 350 ° C. to about 700 ° C., more preferably from about 400 ° C. to about 600 ° C., and at a pressure from about 1 Torr to about atmospheric pressure, more preferably from 50 Torr to 760 Torr, most preferably 760 Torr. , Trisilane (Si 3 H 8 ) and GeH 4 (or other germanium precursors). Preferably, the main carrier is H2 with a flow rate of about 2 to about 100 slm. The amorphous or small granular polycrystalline nature of the deposited SiGe layer can be achieved in a number of different ways. Advantageously, the deposition under these conditions (eg 760 Torr) is higher than 300 Å / min for 40% [Ge] at 500 ° C. or higher than 200 Å / min for 50% [Ge] at 475 ° C. More preferably, α-SiGe can be produced at a rate higher than 300 Å / min.

１つの実施形態において、堆積条件は、ＳｉＧｅの堆積速度がＳｉＧｅ層の再結晶の速度より速いように選択される。固相エピタキシー（ＳＰＥ）またはランダムヌクリエーショングロース（ｒａｎｄｏｍ ｎｕｃｌｅａｔｉｏｎ ｇｒｏｗｔｈ）（ＲＮＧ）は、ＳｉＧｅ層を堆積させるとともに、その再結晶を導く。再結晶、または再成長の速度は、図６において示されるように、温度及びゲルマニウム濃度に依存する。再結晶の速度が堆積の速度より大きな場合、アモルファスまたは小粒状の多結晶の層は達成されない。従って、堆積速度より低いＳＰＥまたはＲＮＧの速度を維持し、そしてアモルファス層を達成するために、約５０％のゲルマニウム濃度について、堆積温度は、好ましくは、約５００℃以下、より好ましくは約４７５℃以下である。圧力及びキャリアガスフロー（例えば、Ｈ２フロー）は、所望の温度で堆積速度を最適化するように、ＣＶＤプロセスで調整される。 In one embodiment, the deposition conditions are selected such that the deposition rate of SiGe is faster than the rate of recrystallization of the SiGe layer. Solid phase epitaxy (SPE) or random nucleation growth (RNG) deposits a SiGe layer and leads to its recrystallization. The rate of recrystallization or regrowth depends on temperature and germanium concentration, as shown in FIG. If the recrystallization rate is greater than the deposition rate, an amorphous or small granular polycrystalline layer is not achieved. Thus, to maintain a SPE or RNG rate below the deposition rate and achieve an amorphous layer, for a germanium concentration of about 50%, the deposition temperature is preferably about 500 ° C. or less, more preferably about 475 ° C. It is as follows. Pressure and carrier gas flow (eg, H 2 flow) are adjusted in the CVD process to optimize the deposition rate at the desired temperature.

アモルファスまたは小粒状の多結晶ＳｉＧｅは、酸化物で少なくとも部分的に覆われているシリコン層上へのＣＶＤによるＳｉＧｅの堆積によっても実現され得る。
例えば、ＳｉＧｅ層は、ＳＯＩ基板上の自然酸化膜（ｎａｔｉｖｅ ｏｘｉｄｅ）に対して堆積され得る。好ましくは、酸化物は、シリコン表面上のモノレイヤーの少なくとも約４分の１、より好ましくはモノレイヤーの少なくとも約半分である。一方、完全なモノレイヤー未満（ｌｅｓｓ ｔｈａｎ ａ ｆｕｌｌ ｍｏｎｏｌａｙｅｒ）が、好ましくは、幾分かの単結晶Ｓｉを露出させておくために、シリコン表面上に形成される。特定の実施形態において、モノレイヤーの半分の酸化物は、酸素環境中で、堆積温度で加熱することによって、ＳＯＩ基板上に形成される。下記のようなＳｉＧｅ層を融解するための高温処理の際、酸化物が還元され、凝固の際、均一なＳｉＧｅ層の形成が導かれる。 Amorphous or small granular polycrystalline SiGe can also be realized by deposition of SiGe by CVD on a silicon layer that is at least partially covered with oxide.
For example, a SiGe layer can be deposited against a native oxide on an SOI substrate. Preferably, the oxide is at least about one quarter of the monolayer on the silicon surface, more preferably at least about half of the monolayer. On the other hand, less than a full monolayer is preferably formed on the silicon surface to keep some single crystal Si exposed. In certain embodiments, the monolayer half oxide is formed on an SOI substrate by heating at a deposition temperature in an oxygen environment. During the high-temperature treatment for melting the SiGe layer as described below, the oxide is reduced, and a uniform SiGe layer is formed upon solidification.

あるいは、より厚い化学酸化膜が、例えば、従来のＳＣ１ソリューションによって、ＳｉＧｅ層の堆積前に、ＳＯＩウエハのＳｉ表面上で形成され得る。この場合、堆積中のＳｉＧｅ層の再成長は、下地の結晶シリコン層との接触の欠如に起因して可能ではない。その結果、ＳｉＧｅの堆積のためのＣＶＤ条件は、再結晶及び結果としての欠陥を回避するためではなく、堆積速度及び前駆物質消費を最適化するために調整され得る。部分的な酸化被膜と同様に、ＳｉＧｅ層を融解するための高温処理が酸化物を還元し、均一な組成の歪み緩和ＳｉＧｅ層の形成を可能にする。   Alternatively, a thicker chemical oxide can be formed on the Si surface of the SOI wafer prior to the deposition of the SiGe layer, for example by a conventional SC1 solution. In this case, regrowth of the SiGe layer during deposition is not possible due to the lack of contact with the underlying crystalline silicon layer. As a result, the CVD conditions for SiGe deposition can be adjusted to optimize deposition rate and precursor consumption rather than to avoid recrystallization and resulting defects. Similar to the partial oxide film, the high temperature treatment to melt the SiGe layer reduces the oxide and allows the formation of a strain relaxed SiGe layer of uniform composition.

さらなる実施形態において、ホウ素、ヒ素、燐、ＳｂまたはＣのようなドーパントのほぼ１層までのモノレイヤーが、ＳｉＧｅ層の堆積前に基板表面上に形成される。この薄層は、ＳｉＧｅ層が堆積される際の、再成長を防ぐ。好ましくは、ドーパント前駆物質を含むガスの短いスパイクが、シリコン表面上にほぼ１層までのドーパントのモノレイヤーを製造するために、ＳｉＧｅ堆積プロセスの開始前に導入される。高温融解の際、この中間ドーパント層が拡散し、凝固の際の均一な歪み緩和ＳｉＧｅ層の形成をもたらす。   In further embodiments, up to approximately one monolayer of a dopant such as boron, arsenic, phosphorous, Sb or C is formed on the substrate surface prior to the deposition of the SiGe layer. This thin layer prevents regrowth as the SiGe layer is deposited. Preferably, a short spike of gas containing the dopant precursor is introduced before the start of the SiGe deposition process to produce up to approximately one dopant monolayer on the silicon surface. During high temperature melting, this intermediate dopant layer diffuses, resulting in the formation of a uniform strain relaxed SiGe layer upon solidification.

堆積されるＳｉＧｅ層２００の厚さは、高温融解から生じる歪み緩和ＳｉＧｅ層中のゲルマニウムの所望の濃度に基づいて決定される。特定の最終ゲルマニウム濃度を達成するのに必要な厚さは、堆積された層のゲルマニウム濃度及びＳＯＩウエハ上の下地シリコン層（それはＧｅ拡散によって消費される）の厚さに基づいて容易に計算することができる。   The thickness of the deposited SiGe layer 200 is determined based on the desired concentration of germanium in the strain relaxed SiGe layer resulting from high temperature melting. The thickness required to achieve a particular final germanium concentration is easily calculated based on the germanium concentration of the deposited layer and the thickness of the underlying silicon layer on the SOI wafer (which is consumed by Ge diffusion) be able to.

下地のシリコン層３００は、好ましくは、約５０Å〜約５００Åの厚さを有する。それがより薄いＳｉＧｅ層の使用及び／または堆積されたＳｉＧｅ層におけるより低い初期ゲルマニウム濃度を可能にするので、より薄いシリコン層が好ましい。例えば、約２０％のゲルマニウムを含む緩和ＳｉＧｅ層が、現在、工業において所望されている。従って、５０Åのシリコン層がＳＯＩウエハ上に存在する場合、４０％のゲルマニウム濃度を有する５０ÅのＳｉＧｅ層が堆積され得る。融解及び凝固の際、ゲルマニウムは、下記のように、ＳｉＧｅ層からシリコン層へと拡散する。その結果、約２０％のゲルマニウム濃度を有する１００ÅのＳｉＧｅ層になる。   The underlying silicon layer 300 preferably has a thickness of about 50 cm to about 500 mm. A thinner silicon layer is preferred because it allows the use of a thinner SiGe layer and / or a lower initial germanium concentration in the deposited SiGe layer. For example, a relaxed SiGe layer containing about 20% germanium is currently desired in the industry. Thus, if a 50Å silicon layer is present on the SOI wafer, a 50Å SiGe layer having a 40% germanium concentration can be deposited. During melting and solidification, germanium diffuses from the SiGe layer to the silicon layer as follows. The result is a 100Å SiGe layer with a germanium concentration of about 20%.

好ましくは、堆積された層において得られるゲルマニウム濃度は、欠陥密度を最小限にするために約６０％以下に、より好ましくは約５０％以下である。図７において見出されるように、約６０％ゲルマニウムの濃度より上では、欠陥密度は、ＳＰＥの間に有意に増加する。本明細書中に参考として援用される米国特許第６，３４６，７３２号を参照のこと。下記のように、高温融解が使用されるが、温度はＳＰＥのための範囲を通して動き、従って、ＳＰＥの間の欠陥の形成が考えられる。   Preferably, the germanium concentration obtained in the deposited layer is about 60% or less, more preferably about 50% or less to minimize defect density. As can be seen in FIG. 7, above the concentration of about 60% germanium, the defect density increases significantly during SPE. See US Pat. No. 6,346,732, incorporated herein by reference. As described below, high temperature melting is used, but the temperature moves through the range for the SPE, and therefore the formation of defects during the SPE is considered.

ＳｉＧｅ層の堆積に続いて、キャップ層４００が形成される（図２）。好ましくは、キャップ層は、ＳｉＧｅ層２００上に直接形成される。キャップ層は、下記の、引き続く高温融解の間に、下地のＳｉＧｅ層２００からのＧｅの蒸発を防ぐ。平滑な界面を有するＳｉＯ２−キャップ層は、ＳｉＧｅ界面が粗くなるのを防ぐ。好ましくは、アモルファスシリコン層４００は、ＳｉＧｅ層上に堆積される。アモルファスシリコン層４００は、典型的には、ＣＶＤによって、好ましくはＳｉＧｅ層２００と同じ反応スペースにおいて堆積される。例えば、アモルファスＳｉＧｅ堆積の後、ＧｅＨ４のフローは止めることができ、そしてアモルファスシリコンの層は、同じ堆積温度でトリシランから成長することができる。 Following the deposition of the SiGe layer, a cap layer 400 is formed (FIG. 2). Preferably, the cap layer is formed directly on the SiGe layer 200. The cap layer prevents evaporation of Ge from the underlying SiGe layer 200 during the subsequent high temperature melting described below. The SiO 2 -cap layer having a smooth interface prevents the SiGe interface from becoming rough. Preferably, the amorphous silicon layer 400 is deposited on the SiGe layer. The amorphous silicon layer 400 is typically deposited by CVD, preferably in the same reaction space as the SiGe layer 200. For example, after amorphous SiGe deposition, the GeH 4 flow can be stopped and the layer of amorphous silicon can be grown from trisilane at the same deposition temperature.

堆積に続いて、アモルファスシリコン層は、好ましくは、酸化して、ＳｉＯ２キャップ層６００（図３）を形成する。好ましくは、酸化は、酸化環境に基板を曝露することにより実施される。当該分野において公知の任意の酸化剤、好ましくは、水または酸素を用いることができる。１つの実施形態において、乾燥酸素が用いられる。別の実施形態において、α−Ｓｉ層４００は湿式酸化される。酸化温度は、好ましくは、約８００℃〜約９００℃の間にある。１つの実施形態において、酸化は、高温アニールの間の酸化種（ｏｘｉｇｅｎａｔｅｄ ｓｐｅｃｉｅｓ）の一時的添加による高温融解処理と組み合わせられる。酸素雰囲気は、好ましくは、高温融解のために取り除かれる。あるいは、酸化物（好ましくはＳｉＯ２）は、エキソサイチュ（ｅｘ−ｓｉｔｕ）で堆積され得る。１つの実施形態において、酸化物は、ＳｉＧｅ層のＳＰＥを回避するのに十分低い温度で、エキソサイチュで堆積される。 Following deposition, the amorphous silicon layer is preferably oxidized to form a SiO 2 cap layer 600 (FIG. 3). Preferably, the oxidation is performed by exposing the substrate to an oxidizing environment. Any oxidant known in the art can be used, preferably water or oxygen. In one embodiment, dry oxygen is used. In another embodiment, the α-Si layer 400 is wet oxidized. The oxidation temperature is preferably between about 800 ° C and about 900 ° C. In one embodiment, the oxidation is combined with a high temperature melting process by the temporary addition of oxidized species during high temperature annealing. The oxygen atmosphere is preferably removed for high temperature melting. Alternatively, an oxide (preferably SiO 2) can be deposited by Ekisosaichu (ex-situ). In one embodiment, the oxide is deposited ex-situ at a temperature low enough to avoid SPE of the SiGe layer.

次いで、基板は、好ましくは、例えば、Ｎ２またはＡｒ雰囲気中のような非反応性環境中で高温融解に供される。高温で、ＳｉＧｅ層は、少なくとも部分的に融解する。融解プロセスの間、ゲルマニウムは、図４における矢印によって例示されるように、ＳｉＧｅ層２００から下地のシリコン層３００へと拡散する。図５において示されるように、凝固の際、均一の組成の歪み緩和ＳｉＧｅ層が製造される。有利には、垂直または貫通転位は、このプロセスによって最小限にされる。貫通転位は、好ましくは１０７ｃｍ−２未満、より好ましくは１０５ｃｍ−２未満、そして最も好ましくは１０００ｃｍ−２である。 The substrate is then preferably subjected to high temperature melting in a non-reactive environment such as, for example, in an N 2 or Ar atmosphere. At high temperatures, the SiGe layer melts at least partially. During the melting process, germanium diffuses from the SiGe layer 200 to the underlying silicon layer 300, as illustrated by the arrows in FIG. As shown in FIG. 5, a strain-relaxed SiGe layer of uniform composition is produced during solidification. Advantageously, vertical or threading dislocations are minimized by this process. The threading dislocation is preferably less than 10 7 cm −2 , more preferably less than 10 5 cm −2 , and most preferably 1000 cm −2 .

高温アニーリングは、好ましくは、約９５０℃〜約１４２５℃の間で実施され、より好ましくはその温度は、約１０００℃より高く約１４２５℃未満である。融解温度は、均一な歪み緩和ＳｉＧｅ層を形成するのに決定的に重要なパラメーターである。２つのＳｉＯ２層６００、７００の間のＳｉＧｅ層５００全体（Ｇｅが拡散したＳｉ層を含む）が融解される場合、全ての結晶情報が失われ、そして得られる層は多結晶であり、歪み緩和エピタキシャル層ではない。上記のＳｕｇｉｉらを参照のこと。図８は、温度及びゲルマニウム濃度の関数としての固相及び液相曲線のグラフを示す。高温融解のための温度は、好ましくは、得られるＳｉＧｅ層５００における所定の最終ゲルマニウム濃度についての固相曲線のちょうど左側にある温度が選択される。例えば、堆積されたＳｉＧｅ層２００（図４）が６０％のゲルマニウムを含み、得られるＳｉＧｅ層５００（図５）が４０％のゲルマニウムを含む状況においては、初期ＳｉＧｅ層は、１１５０℃で融解する。しかし、得られるＳｉＧｅ層は、その温度で固体である。従って、両方の層の完全な融解はなく、そして均一な歪み緩和エピタキシャルＳｉＧｅ層５００の形成を可能にするのに十分な結晶構造が維持される。しかし、１２００℃の温度（４０％Ｇｅ濃度について固相線のちょうど右端）が用いられる場合、最初のＳｉＧｅ層２００及び得られるＳｉＧｅ層５００の両方が融解する。結晶構造は残らず、そして結晶化は生じない。 High temperature annealing is preferably performed between about 950 ° C. and about 1425 ° C., more preferably the temperature is greater than about 1000 ° C. and less than about 1425 ° C. The melting temperature is a critical parameter for forming a uniform strain relaxation SiGe layer. When the entire SiGe layer 500 between the two SiO 2 layers 600, 700 is melted (including the Si diffused Si layer), all crystal information is lost and the resulting layer is polycrystalline and strained It is not a relaxed epitaxial layer. See Sugiii et al. Above. FIG. 8 shows a graph of solid and liquid phase curves as a function of temperature and germanium concentration. The temperature for high temperature melting is preferably selected to be just to the left of the solid phase curve for a given final germanium concentration in the resulting SiGe layer 500. For example, in a situation where the deposited SiGe layer 200 (FIG. 4) contains 60% germanium and the resulting SiGe layer 500 (FIG. 5) contains 40% germanium, the initial SiGe layer melts at 1150 ° C. . However, the resulting SiGe layer is solid at that temperature. Thus, there is no complete melting of both layers and a sufficient crystal structure is maintained to allow the formation of a uniform strain relaxation epitaxial SiGe layer 500. However, if a temperature of 1200 ° C. (just the right end of the solidus for 40% Ge concentration) is used, both the initial SiGe layer 200 and the resulting SiGe layer 500 will melt. No crystal structure remains and no crystallization occurs.

高温は、好ましくは、下地のシリコン層３００の全体にわたってゲルマニウムが拡散するのに十分な長さの時間の間、維持され、均一なＳｉＧｅ層５００が生じる。従って、高温融解に適する時間は、下地のＳｉ層の厚さ、堆積されたＳｉＧｅ層の厚さ、堆積されたＳｉＧｅ層のゲルマニウム濃度及び選択された温度でのシリコン中のゲルマニウムの拡散係数に基づいて決定することができる（Ｓｕｇｉｉらを参照のこと）。好ましくは、融解温度は、最終［Ｇｅ］含有量に依存して、約１０５０℃−１３００℃の融解温度で、１分〜１２時間、より好ましくは１〜２時間維持される。従って、冷却することにより凝固させるよりも、得られるシリコンゲルマニウム層濃度が、選択されたアニール温度での固相曲線より下に下がるまでゲルマニウムの拡散をもたらすように、単一の温度が選択される。   The high temperature is preferably maintained for a length of time sufficient for germanium to diffuse throughout the underlying silicon layer 300, resulting in a uniform SiGe layer 500. Thus, a suitable time for high temperature melting is based on the thickness of the underlying Si layer, the thickness of the deposited SiGe layer, the germanium concentration of the deposited SiGe layer and the diffusion coefficient of germanium in silicon at the selected temperature. (See Sugii et al.). Preferably, the melting temperature is maintained at a melting temperature of about 1050 ° C.-1300 ° C. for 1 minute to 12 hours, more preferably 1-2 hours, depending on the final [Ge] content. Thus, rather than solidifying by cooling, a single temperature is selected to result in germanium diffusion until the resulting silicon germanium layer concentration falls below the solid phase curve at the selected annealing temperature. .

凝固に続いて、基板は、特定の用途のために所望されるようなさらなる処理に供され得る。典型的には、ＳｉＯ２キャップ層４００は、ケミカルエッチにより除去される。次いで、ストレインドシリコン層が、歪み緩和ＳｉＧｅ層上に、ヘテロエピタキシャリーに堆積される。 Following solidification, the substrate can be subjected to further processing as desired for a particular application. Typically, the SiO 2 cap layer 400 is removed by chemical etching. A strained silicon layer is then deposited heteroepitaxially on the strain relaxed SiGe layer.

低い欠陥密度を有する歪み緩和ＳｉＧｅを形成するためのＳＰＥプロセス（図１０）
発明の別の局面において、歪み緩和ＳｉＧｅ層は、固相エピタキシーによって形成される。この実施形態において、エピタキシャル成長はＳＰＥプロセスの間にＳｉＧｅ／Ｓｉ界面で分断（ｄｉｓｒｕｐｔ）される。好ましくは、エピタキシャル成長は、ＳｉＧｅ／Ｓｉ界面に結晶構造が介在することにより分断される。この分断は、例えば、Ｓｉ層自体の欠陥によって、またはＳｉ層上に形成または堆積された物質によって引き起こされ得るが、これらに限定されない。 SPE process for forming strain relaxed SiGe with low defect density (FIG. 10)
In another aspect of the invention, the strain relaxation SiGe layer is formed by solid phase epitaxy. In this embodiment, the epitaxial growth is disrupted at the SiGe / Si interface during the SPE process. Preferably, the epitaxial growth is interrupted by the presence of a crystal structure at the SiGe / Si interface. This disruption can be caused by, for example, but not limited to, defects in the Si layer itself, or by materials formed or deposited on the Si layer.

ＳＰＥが分断されるので、基板とエピタキシャル成長層との間の歪みが緩和される。その結果、融解プロセスに関して上記されるように、歪み緩和ＳｉＧｅ層が製造され、そして貫通欠陥形成が最小限にされる。   Since SPE is divided, strain between the substrate and the epitaxial growth layer is relaxed. As a result, as described above with respect to the melting process, a strain relaxed SiGe layer is produced and through defect formation is minimized.

ＳｉＧｅは、好ましくは、基板上に、アモルファス状または小粒多結晶形態で堆積される。この基板は、例えば、ブランケットシリコンウエハまたはＳＯＩウエハであり得る。   SiGe is preferably deposited on the substrate in an amorphous or small polycrystalline form. This substrate can be, for example, a blanket silicon wafer or an SOI wafer.

ＳｉＧｅの堆積は、好ましくは、ＣＶＤによる。好ましくは、ＳｉＧｅは、トリシラン及びＧｅＨ４、ジゲルマンまたは他のＧｅ前駆物質から堆積される。高温融解プロセスについて上記されるように、アモルファスＳｉＧｅを堆積するために、堆積温度は、好ましくは、再成長速度が堆積速度より遅く、しかし商業上許容される堆積速度（好ましくは、１００Å／分より高く、より好ましくは約２００Å／分〜６００Å／分の間）であるのに充分に低い。温度、圧力及びＨ２キャリアのフローは、所定の温度及びゲルマニウム濃度で堆積速度を最適化するように調整される。１つの実施形態において、ＳｉＧｅは、４７５℃の温度で、トリシラン及びＧｅＨ４から、ＣＶＤによって堆積される。別の実施形態において、堆積温度は５００℃である。好ましくは、堆積温度は、約４００Ｃ〜約６００℃の間である。 The deposition of SiGe is preferably by CVD. Preferably, SiGe is deposited from trisilane and GeH 4 , digermane or other Ge precursor. As described above for the high temperature melting process, to deposit amorphous SiGe, the deposition temperature is preferably set so that the regrowth rate is slower than the deposition rate, but a commercially acceptable deposition rate (preferably less than 100 Å / min. High, more preferably low enough to be between about 200 liters / minute and 600 liters / minute). Temperature, pressure and H 2 carrier flow are adjusted to optimize the deposition rate at a given temperature and germanium concentration. In one embodiment, SiGe is deposited by CVD from trisilane and GeH 4 at a temperature of 475 ° C. In another embodiment, the deposition temperature is 500 ° C. Preferably, the deposition temperature is between about 400C and about 600 ° C.

基板上に堆積されるＳｉＧｅ層の厚さは、歪み緩和ＳｉＧｅ層の中のゲルマニウムの所望の濃度に基づいて決定される。このプロセスはＧｅ拡散なしで実施され得るので、上記の高温融解の場合と異なり、ＳｉＧｅ層の中のゲルマニウムの濃度が処理中に変化する必要はない。従って、層の中の初期ゲルマニウム濃度と最終ゲルマニウム濃度は、好ましくは同一である。   The thickness of the SiGe layer deposited on the substrate is determined based on the desired concentration of germanium in the strain relaxed SiGe layer. Since this process can be performed without Ge diffusion, unlike the high temperature melting case described above, the concentration of germanium in the SiGe layer need not change during processing. Therefore, the initial germanium concentration and the final germanium concentration in the layer are preferably the same.

しかし、堆積された層におけるゲルマニウム濃度は、欠陥密度を最小限にするために、好ましくは約６０％以下、より好ましくは約５０％以下である。図７に見出されるように、約６０％ゲルマニウム濃度より上では、欠陥密度は、ＳＰＥの間に有意に増加する。本明細書中に参考として援用される、米国特許第６，３４６，７３２号を参照のこと。従って、堆積されるＳｉＧｅ層は、好ましくは、約０％〜約６０％の間、より好ましくは、約２０％〜約５０％の間のゲルマニウム濃度を有している。   However, the germanium concentration in the deposited layer is preferably about 60% or less, more preferably about 50% or less in order to minimize defect density. As can be seen in FIG. 7, above about 60% germanium concentration, the defect density increases significantly during SPE. See US Pat. No. 6,346,732, incorporated herein by reference. Accordingly, the deposited SiGe layer preferably has a germanium concentration between about 0% to about 60%, more preferably between about 20% to about 50%.

エピタキシャル成長は、基板表面上の１未満の酸化物モノレイヤーの存在によって分断される。１つの実施形態において、酸化物は自然酸化膜である。別の実施形態において、酸化物は、基板上に故意に成長させられる。好ましくは、酸化物は、完全なモノレイヤー未満、より好ましくはモノレイヤーの４分の３未満、なおより好ましくはモノレイヤーの半分未満（３．５×１０１４ｃｍ−２）である。特定の実施形態において、酸化物の半分のモノレイヤーが、堆積温度での酸素環境における加熱によって、基板上に形成される。 Epitaxial growth is disrupted by the presence of less than one oxide monolayer on the substrate surface. In one embodiment, the oxide is a native oxide film. In another embodiment, the oxide is intentionally grown on the substrate. Preferably, the oxide is less than a complete monolayer, more preferably less than three quarters of the monolayer, and even more preferably less than half of the monolayer (3.5 × 10 14 cm −2 ). In certain embodiments, a half monolayer of oxide is formed on the substrate by heating in an oxygen environment at the deposition temperature.

１つの実施形態において、１層より厚いモノレイヤーの酸化物層が形成される。次いで、酸化物は、エッチングされるかそうでなければ還元されて、少なくとも幾分かの単結晶Ｓｉを露出する。例えば、より厚い化学酸化膜が、基板表面上に形成され得る。次いで、この化学酸化膜が、好ましくは、モノレイヤー未満、より好ましくはモノレイヤーの約半分未満までエッチングされる。エッチプロセスは、アモルファスＳｉＧｅの堆積の前に実施される。   In one embodiment, a monolayer oxide layer thicker than one layer is formed. The oxide is then etched or otherwise reduced to expose at least some single crystal Si. For example, a thicker chemical oxide film can be formed on the substrate surface. The chemical oxide is then preferably etched to less than a monolayer, more preferably less than about half of the monolayer. An etch process is performed prior to the deposition of amorphous SiGe.

ＳｉＧｅ層の堆積後、固相エピタキシーが実施される。これらの方法は当該分野において周知である。例えば、米国特許第６，３４６，７３２号を参照のこと。好ましくは、基板は、約３０分間、約５００℃〜約９００℃の間の温度まで加熱される。   After deposition of the SiGe layer, solid phase epitaxy is performed. These methods are well known in the art. See, for example, US Pat. No. 6,346,732. Preferably, the substrate is heated to a temperature between about 500 ° C. and about 900 ° C. for about 30 minutes.

１つの実施形態において、自然酸化膜のような酸化物の薄層が、ＳＰＥプロセスの前にＳｉＧｅ層上に形成される。周囲（または任意の酸化雰囲気）にＳｉＧｅ層を曝露して、ＳＰＥプロセスの前に薄い（自然）酸化膜を形成することは、ＳＰＥの間の表面の平滑さをさらに改善するのを助け得る。   In one embodiment, a thin layer of oxide, such as a native oxide, is formed on the SiGe layer prior to the SPE process. Exposing the SiGe layer to the surroundings (or any oxidizing atmosphere) to form a thin (native) oxide film prior to the SPE process can help further improve the surface smoothness during the SPE.

ＳＰＥ後に、シリコンの層が、ＳｉＧｅ上に、ヘテロエピタキシャリーに堆積され得る。ＳｉＧｅ層の緩んだ性質は、エピタキシャルシリコン層の中に歪みを生む。酸化物がＳＰＥの前にＳｉＧｅ層上に堆積された場合、酸化物は、好ましくは、シリコン層の堆積の前に除去される。   After SPE, a layer of silicon can be deposited heteroepitaxially on SiGe. The relaxed nature of the SiGe layer creates strain in the epitaxial silicon layer. If oxide is deposited on the SiGe layer prior to SPE, the oxide is preferably removed prior to deposition of the silicon layer.

バルク基板上にＳＰＥによって製造され、最上部にストレインドＳｉ層を有する、歪み緩和ＳｉＧｅを含む層スタックは、層トランスファー技術によって酸化ハンドルウエハの最上部にトランスファーされ、残留ＳｉＧｅの選択的な除去によってストレインドＳｉ（のみ）オンインシュレーター（ｓＳＯＩ）を形成する。任意の層トランスファー技術（例えば、Ｓｍａｒｔ−Ｃｕｔ／ＵｎｉｂｏｎｄＴＭ技術（ＳＯＩＴＥＣ（Ｂｅｒｎｉｎ，Ｆｒａｎｃｅ）製）、Ｂｏｎｄ ａｎｄ Ｅｔｃｈ−ｂａｃｋ ｏｒ Ｅｐｉｔａｘｉａｌ−Ｌａｙｅｒ ｔｒａｎｓｆｅｒ法（ＥＬＴＲＡＮＴＭ；Ｃａｎｏｎ ＮＹ，ＵＳＡ）またはＮａｎｏｃｌｅａｖｅＴＭ ｌａｙｅｒ ｔｒａｎｓｆｅｒ法（ＳｉＧｅｎ製（ＣＡ，ＵＳＡ）））が用いられ得る。 A layer stack comprising strain relaxed SiGe, fabricated by SPE on a bulk substrate and having a strained Si layer on the top, is transferred to the top of the oxidized handle wafer by layer transfer technology and selectively removed by residual SiGe. A strained Si (only) on insulator (sSOI) is formed. Any layer transfer technique (e.g., manufactured by Smart-Cut / Unibond TM technology (SOITEC (Bernin, France)) , Bond and Etch-back or Epitaxial-Layer transfer process (ELTRAN TM; Canon NY, USA ) or Nanocleave TM layer transfer Method (SiGen (CA, USA)) can be used.

歪み緩和ＳｉＧｅを形成するためのヘテロエピタキシー、その後の注入及びアニール（図１１）
本発明の別の局面において、歪み緩和ＳｉＧｅ層は、Ｓｉ上のＳｉＧｅのヘテロエピタキシー、その後の発泡剤の注入及びＳｉＧｅ層を緩和するための引き続くアニーリングによって形成される。歪み緩和の間の欠陥の形成は、下部Ｓｉ層と上部ＳｉＧｅ層との間の結晶界面の分断によって防がれる。例えば、その開示が本明細書中に参考として援用される、Ｌｕｙｓｂｅｒｇ Ｊ．Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ Ｏｃｔｏｂｅｒ １５ｔｈ ２００２；Ｈｅｒｚｏｇら、ＩＥＥＥ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｌｅｔｔｅｒｓ ２３：４８５（２００２）；及びＨｕａｎｇｅら、Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ ７８：１２６７（２００１）を参照のこと。 Heteroepitaxy to form strain relaxed SiGe, followed by implantation and annealing (FIG. 11)
In another aspect of the present invention, a strain-relaxed SiGe layer is formed by heteroepitaxy of SiGe on Si, followed by implantation of a blowing agent and subsequent annealing to relax the SiGe layer. The formation of defects during strain relaxation is prevented by breakage of the crystal interface between the lower Si layer and the upper SiGe layer. See, for example, Luysberg J., the disclosure of which is incorporated herein by reference. Applied Physics October 15th 2002; Herzog et al., IEEE Electron Devices Letters 23: 485 (2002); and Huange et al., Appl. Phys. Lett 78: 1267 (2001).

本質的に上に記述されるように、ＳｉＧｅは、好ましくは、シリコン前駆物質及びゲルマニウム前駆物質からＣＶＤによってエピタキシャリーに堆積される。好ましくは、シリコン前駆物質はトリシランである。１つの実施形態において、ゲルマニウム前駆物質はジゲルマンである。堆積温度は、好ましくは約３５０℃〜約７００℃、より好ましくは約４００℃〜約６００℃である。   As described essentially above, SiGe is preferably deposited epitaxially from a silicon precursor and a germanium precursor by CVD. Preferably, the silicon precursor is trisilane. In one embodiment, the germanium precursor is digermane. The deposition temperature is preferably about 350 ° C to about 700 ° C, more preferably about 400 ° C to about 600 ° C.

ＳｉＧｅ層は、好ましくは、層が堆積温度で緩和する臨界厚さ以下の厚さに堆積される。従って、堆積されたＳｉＧｅ層は、歪んだままである。臨界厚さが温度に依存するので、堆積は、好ましくは、全体的な層の厚さを最大限にするために、低温で実施される。それがより高いアニーリング温度で緩和するので、より厚い層が好ましい。   The SiGe layer is preferably deposited to a thickness below the critical thickness at which the layer relaxes at the deposition temperature. Thus, the deposited SiGe layer remains distorted. Since the critical thickness is temperature dependent, the deposition is preferably carried out at a low temperature to maximize the overall layer thickness. A thicker layer is preferred because it relaxes at higher annealing temperatures.

１つの実施形態において、ＳｉＧｅ層は、約５０〜約２００ｎｍの厚さ、より好ましくは約１００〜約１５０ｎｍの厚さまで堆積される。   In one embodiment, the SiGe layer is deposited to a thickness of about 50 to about 200 nm, more preferably about 100 to about 150 nm.

ストレインドＳｉＧｅ層の堆積後、発泡剤（例えば、イオン）は、ＳｉＧｅ層の真下に、好ましくはＳｉ／ＳｉＧｅ界面もしくはその下に注入される。より好ましくは、発泡剤は、Ｓｉ／ＳｉＧｅ界面の下約５０ｎｍ〜約１００ｎｍに注入される。１つの実施形態において、発泡剤はＨ＋である。別の実施形態において、発泡剤はＨｅ＋である。 After deposition of the strained SiGe layer, a blowing agent (eg, ions) is implanted directly below the SiGe layer, preferably at or below the Si / SiGe interface. More preferably, the blowing agent is injected from about 50 nm to about 100 nm below the Si / SiGe interface. In one embodiment, the blowing agent is H + . In another embodiment, the blowing agent is He + .

発泡剤は、Ｓｉ／ＳｉＧｅ界面で結晶構造を中断させるのに十分な量注入される。特定の実施形態において、約１×１０１６イオンｃｍ−２〜約１×１０１７イオンｃｍ−２が注入される。 The blowing agent is injected in an amount sufficient to disrupt the crystal structure at the Si / SiGe interface. In certain embodiments, about 1 × 10 16 ions cm −2 to about 1 × 10 17 ions cm −2 are implanted.

Ｓｉ／ＳｉＧｅ界面での酸素の注入も企図される。特に、酸素の注入が、ＳＯＩ基板上に充分に緩和されたＳｉＧｅ層を形成するために用いられ得る。例えば、本明細書中に参考として援用される、Ｓｕｇｉｙａｍａら、Ｔｈｉｎ Ｓｏｌｉｄ Ｆｉｌｍｓ ３６９：１９９（２０００）を参照のこと。   Oxygen implantation at the Si / SiGe interface is also contemplated. In particular, oxygen implantation may be used to form a fully relaxed SiGe layer on the SOI substrate. See, for example, Sugiyama et al., Thin Solid Films 369: 199 (2000), incorporated herein by reference.

引き続くＳｉＧｅ層のアニーリングは、層の緩和を導く。好ましくは、アニーリングは、約４００℃〜約１０００℃の間、より好ましくは約７００℃〜約８５０℃の間の温度で、実施される。アニーリングは、好ましくは、約１分〜約１２時間、より好ましくは約１分〜約１時間、より好ましくは１０分間実行される。アニーリング温度では、泡は、注入された発泡剤（例えばＨまたはＨｅ）から形成され、そしてパンチアウト転位ループを作り出す。この転位ループは、Ｓｉ／ＳｉＧｅ界面まで移動するかそうでなければ広がり、不整合な転位を緩和する歪みを形成する。さらに、層が臨界厚さ未満に堆積されるので、それは、引き続き、アニールプロセスまで歪んだままである（この点において、点緩和は、注入により作り出された欠陥と適応している）。従って、広がった結晶欠陥（例えば、貫通転位）が回避される。好ましくは、１０７貫通転位未満が、ＳｉＧｅ層中に存在し、より好ましくは１０５未満、そしてなおより好ましくは１０３未満である。 Subsequent annealing of the SiGe layer leads to layer relaxation. Preferably, the annealing is performed at a temperature between about 400 ° C and about 1000 ° C, more preferably between about 700 ° C and about 850 ° C. Annealing is preferably performed for about 1 minute to about 12 hours, more preferably about 1 minute to about 1 hour, more preferably 10 minutes. At the annealing temperature, the foam is formed from the injected blowing agent (eg H or He) and creates a punch-out dislocation loop. This dislocation loop migrates to the Si / SiGe interface or otherwise widens, creating a strain that relaxes misfit dislocations. Furthermore, as the layer is deposited below the critical thickness, it continues to be distorted until the annealing process (in this regard, point relaxation is accommodated with defects created by implantation). Thus, extended crystal defects (eg threading dislocations) are avoided. Preferably, less than 10 7 threading dislocations are present in the SiGe layer, more preferably less than 10 5 , and even more preferably less than 10 3 .

Ｓｉキャップ層は、好ましくは、ＳｉＧｅ層上に堆積されて、ストレインドシリコン層を作り出す。１つの実施形態において、ＳｉＧｅキャップ層は、アニーリングの後に堆積される。しかし、好ましくは、キャップ層は、アニーリングの前に堆積される。例えば、約１０〜約１５ｎｍ厚さのストレインドシリコンのキャップ層は、アニーリング前に、ストレインドＳｉＧｅ層上に堆積され得る。   A Si cap layer is preferably deposited on the SiGe layer to create a strained silicon layer. In one embodiment, the SiGe cap layer is deposited after annealing. However, preferably the cap layer is deposited prior to annealing. For example, a strained silicon cap layer of about 10 to about 15 nm thickness can be deposited on the strained SiGe layer prior to annealing.

さらなる実施形態において、得られる層スタックは、ハンドルウエハに移送される。   In a further embodiment, the resulting layer stack is transferred to a handle wafer.

前述の本発明は、特定の好ましい実施形態を用いて記載されたが、その他の実施形態は、本明細書中の開示を考慮して当業者に明白となる。従って、本発明は、好ましい実施形態の引用によって限定されることは意図されず、もっぱら添付の特許請求の範囲を参照して定義されることが意図される。   Although the foregoing invention has been described using certain preferred embodiments, other embodiments will become apparent to those skilled in the art in view of the disclosure herein. Accordingly, the invention is not intended to be limited by reference to the preferred embodiments, but is intended to be defined solely with reference to the appended claims.

Claims (26)

シリコン−オン−インシュレーター（ＳＯＩ）基板上で、化学気相成長（ＣＶＤ）法によって、第１のゲルマニウム濃度を有するアモルファスＳｉＧｅ層をドーパントの１以下のモノレイヤー上に堆積すること；
該アモルファスＳｉＧｅ層上にＳｉＯ２層を堆積すること；及び
該ＳｉＯ２層を堆積した後、１０００℃より高い温度で該アモルファスＳｉＧｅ層を融解することにより、該第１のゲルマニウム濃度よりも低い第２のゲルマニウム濃度を有するＳｉＧｅ部分を有するＳｉＧｅ−オン−インシュレーター基板を形成すること；
を含む、
ＳｉＧｅ−オン−インシュレーター（ＳｉＧｅ−ｏｎ ｉｎｓｕｌａｔｏｒ）基板を形成する方法。 Depositing an amorphous SiGe layer having a first germanium concentration on one or less monolayers of dopant on a silicon-on-insulator (SOI) substrate by chemical vapor deposition (CVD);
Depositing a SiO 2 layer on the amorphous SiGe layer; and, after depositing the SiO 2 layer, melting the amorphous SiGe layer at a temperature higher than 1000 ° C. to lower the first germanium concentration lower than the first germanium concentration. Forming a SiGe-on-insulator substrate having a SiGe portion having a germanium concentration of 2;
including,
A method of forming a SiGe-on insulator substrate. 該アモルファスＳｉＧｅ層が、トリシラン及びＧｅＨ４である前駆体を用いて堆積される、請求項１に記載の方法。 The method of claim 1, wherein the amorphous SiGe layer is deposited using a precursor that is trisilane and GeH 4 . 該アモルファスＳｉＧｅ層が４００℃〜６００℃の間の堆積温度で堆積される、請求項２に記載の方法。   The method of claim 2, wherein the amorphous SiGe layer is deposited at a deposition temperature between 400C and 600C. 前記ドーパントが、Ｂ、Ｐ、Ａｓ、Ｓｂ及びＣからなる群より選択される、請求項１に記載の方法。   The method of claim 1, wherein the dopant is selected from the group consisting of B, P, As, Sb and C. 前記アモルファスＳｉＧｅ層が、ＳＰＥまたはＲＮＧに起因するその再成長の速度より速い速度で堆積される、請求項１に記載の方法。   The method of claim 1, wherein the amorphous SiGe layer is deposited at a faster rate than its regrowth rate due to SPE or RNG. 該ＳＯＩ基板が、５０Å〜５００Åの間の厚さの内在するシリコン層を有する、請求項１に記載の方法。   The method of claim 1, wherein the SOI substrate has an underlying silicon layer with a thickness between 50 and 500 inches. 前記ＳｉＧｅ層が、２０％〜６０％の間のゲルマニウム濃度を有する、請求項１に記載の方法。   The method of claim 1, wherein the SiGe layer has a germanium concentration between 20% and 60%. ＳｉＯ２層の堆積が、アモルファスシリコン層を堆積すること及び該アモルファスシリコン層を酸化することを含む、請求項１に記載の方法。 The method of claim 1, wherein depositing the SiO 2 layer comprises depositing an amorphous silicon layer and oxidizing the amorphous silicon layer. ＣＶＤによって、第一Ｓｉ層上に、トリシラン及びゲルマニウム前駆物質からＳｉＧｅ層を堆積し、それによって該第一Ｓｉ層と該ＳｉＧｅ層との間に界面（ｉｎｔｅｒｆａｃｅ）を形成すること；
該堆積されたＳｉＧｅ層を歪み緩和単結晶構造へと変換すること；及び
該歪み緩和ＳｉＧｅ層上に第二Ｓｉ層をヘテロエピタキシャリーに堆積して、ストレインド第二Ｓｉ層を形成すること、
を含み、該歪み緩和ＳｉＧｅ層が１０７未満の貫通転位を有し、
前記ストレインドＳｉＧｅ層の歪み緩和単結晶構造への変換が、該ＳｉＧｅ層を堆積する前であり且つ固相エピタキシーを実施する前に、１以下のモノレイヤーのドーパントを存在させることを含む、緩和ＳｉＧｅ層上にストレインドシリコン層を形成する方法。 Depositing a SiGe layer from trisilane and germanium precursor on the first Si layer by CVD, thereby forming an interface between the first Si layer and the SiGe layer;
Converting the deposited SiGe layer into a strain-relaxed single crystal structure; and depositing a second Si layer on the strain-relaxed SiGe layer heteroepitaxially to form a strained second Si layer;
The strain relaxed SiGe layer has threading dislocations of less than 10 7 ;
Relaxation wherein the conversion of the strained SiGe layer to a strain-relieved single crystal structure includes the presence of no more than one monolayer dopant prior to depositing the SiGe layer and prior to performing solid phase epitaxy. A method of forming a strained silicon layer on a SiGe layer. 前記ＳｉＧｅ層が、堆積される際、アモルファスである、請求項９に記載の方法。   The method of claim 9, wherein the SiGe layer is amorphous when deposited. 前記ＳｉＧｅ層が、堆積される際、ストレインドヘテロエピタキシャル層である、請求項９に記載の方法。   The method of claim 9, wherein the SiGe layer is a strained heteroepitaxial layer when deposited. 前記ＳｉＧｅ層が、該ＳｉＧｅ層の堆積の間、その温度で、その臨界厚さ未満の厚さで堆積される、請求項１１に記載の方法。   The method of claim 11, wherein the SiGe layer is deposited at a temperature less than its critical thickness during deposition of the SiGe layer. 前記ストレインドＳｉＧｅ層の歪み緩和単結晶構造への変換が、前記第一Ｓｉ層と前記ＳｉＧｅ層との間の界面の下に発泡剤を注入（ｉｍｐｌａｎｔ）することを含む、請求項１１に記載の方法。   12. The transformation of the strained SiGe layer to a strain-relief single crystal structure comprises injecting a blowing agent below the interface between the first Si layer and the SiGe layer. the method of. 前記発泡剤が、Ｈｅ及びＨからなる群より選択される、請求項１３に記載の方法。   The method of claim 13, wherein the blowing agent is selected from the group consisting of He and H. 前記ストレインドＳｉＧｅ層の変換が、前記ＳｉＧｅ層をアニーリングすることをさらに含む、請求項１４に記載の方法。   The method of claim 14, wherein converting the strained SiGe layer further comprises annealing the SiGe layer. 前記界面が、前記第一Ｓｉ層上の、モノレイヤーの半分以下の酸化物の存在によって分断される、請求項９に記載の方法。   The method of claim 9, wherein the interface is disrupted by the presence of less than half of the monolayer oxide on the first Si layer. 前記界面が、不整合転位の存在によって分断される、請求項９に記載の方法。   The method of claim 9, wherein the interface is disrupted by the presence of misfit dislocations. 前記第一Ｓｉ層がＳＯＩ基板の一部であり、そして前記ストレインドＳｉＧｅ層の歪み緩和単結晶構造への変換が、該ＳｉＧｅ層を融解することを含む、請求項９に記載の方法。   The method of claim 9, wherein the first Si layer is part of an SOI substrate, and converting the strained SiGe layer to a strain relaxed single crystal structure comprises melting the SiGe layer. 融解が、ゲルマニウムを、前記ＳｉＧｅ層から前記第一Ｓｉ層を通って酸化物界面まで拡散させることを含む、請求項１８に記載の方法。   The method of claim 18, wherein melting comprises diffusing germanium from the SiGe layer through the first Si layer to an oxide interface. 該ＳＯＩ基板が、酸化物の部分を覆っているシリコンの部分を有し、
該アモルファスＳｉＧｅ層を融解することが、該ＳＯＩ基板のシリコンの部分を融解することをさらに含む、請求項１に記載の方法。 The SOI substrate has a silicon portion covering an oxide portion;
The method of claim 1, wherein melting the amorphous SiGe layer further comprises melting a silicon portion of the SOI substrate. 該ＳＯＩ基板が、酸化物の部分を覆っているシリコンの部分を有し、
該アモルファスＳｉＧｅ層を融解することが、該ＳＯＩ基板のシリコンの部分にゲルマニウムを拡散させることをさらに含む、請求項１に記載の方法。 The SOI substrate has a silicon portion covering an oxide portion;
The method of claim 1, wherein melting the amorphous SiGe layer further comprises diffusing germanium into a silicon portion of the SOI substrate. 該ＳＯＩ基板が、酸化物の部分を覆っているシリコンの部分を有し、
該ＳｉＧｅ−オン−インシュレーター基板のＳｉＧｅの部分を、該酸化物の部分に接触させる、請求項１に記載の方法。 The SOI substrate has a silicon portion covering an oxide portion;
The method of claim 1, wherein a SiGe portion of the SiGe-on-insulator substrate is contacted with the oxide portion. 該ＳｉＧｅ−オン−インシュレーター基板のＳｉＧｅの部分が、１０５ｃｍ−２未満の欠陥密度を有する、請求項２２に記載の方法。 23. The method of claim 22, wherein the SiGe portion of the SiGe-on-insulator substrate has a defect density of less than 10 < 5 > cm <-2 >. 該ＳｉＧｅ−オン−インシュレーター基板のＳｉＧｅの部分が、１０３ｃｍ−２未満の欠陥密度を有する、請求項１に記載の方法。 The method of claim 1, wherein the SiGe portion of the SiGe-on-insulator substrate has a defect density of less than 10 3 cm −2 . 該第２のゲルマニウム濃度が５０％以下である、請求項１に記載の方法。   The method of claim 1, wherein the second germanium concentration is 50% or less. 該ＳｉＧｅ−オン−インシュレーター基板のＳｉＧｅの部分が、実質的に均一なゲルマニウム濃度を有する、請求項１に記載の方法。   The method of claim 1, wherein the SiGe portion of the SiGe-on-insulator substrate has a substantially uniform germanium concentration.
JP2012153053A 2003-07-23 2012-07-06 Silicon-on-insulator structures and SiGe deposition on bulk substrates Active JP5601595B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US48969103P 2003-07-23 2003-07-23
US60/489,691 2003-07-23

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2006521223A Division JP2007505477A (en) 2003-07-23 2004-07-21 Silicon-on-insulator structures and SiGe deposition on bulk substrates

Publications (2)

Publication Number Publication Date
JP2012231165A true JP2012231165A (en) 2012-11-22
JP5601595B2 JP5601595B2 (en) 2014-10-08

Family

ID=34102923

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2006521223A Withdrawn JP2007505477A (en) 2003-07-23 2004-07-21 Silicon-on-insulator structures and SiGe deposition on bulk substrates
JP2012153053A Active JP5601595B2 (en) 2003-07-23 2012-07-06 Silicon-on-insulator structures and SiGe deposition on bulk substrates

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2006521223A Withdrawn JP2007505477A (en) 2003-07-23 2004-07-21 Silicon-on-insulator structures and SiGe deposition on bulk substrates

Country Status (5)

Country Link
US (2) US7208354B2 (en)
EP (1) EP1647046A2 (en)
JP (2) JP2007505477A (en)
KR (1) KR20060056331A (en)
WO (1) WO2005010946A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8927363B2 (en) 2013-05-17 2015-01-06 International Business Machines Corporation Integrating channel SiGe into pFET structures
US9818761B2 (en) 2015-06-25 2017-11-14 International Business Machines Corporation Selective oxidation for making relaxed silicon germanium on insulator structures

Families Citing this family (314)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
KR20060056331A (en) 2003-07-23 2006-05-24 에이에스엠 아메리카, 인코포레이티드 Deposition of sige on silicon-on-insulator structures and bulk substrates
US7029980B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor Inc. Method of manufacturing SOI template layer
US20060011906A1 (en) * 2004-07-14 2006-01-19 International Business Machines Corporation Ion implantation for suppression of defects in annealed SiGe layers
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
US7067400B2 (en) * 2004-09-17 2006-06-27 International Business Machines Corporation Method for preventing sidewall consumption during oxidation of SGOI islands
US7585792B2 (en) * 2005-02-09 2009-09-08 S.O.I.Tec Silicon On Insulator Technologies Relaxation of a strained layer using a molten layer
JP2006270000A (en) * 2005-03-25 2006-10-05 Sumco Corp PROCESS FOR PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THAT METHOD
US20070154637A1 (en) * 2005-12-19 2007-07-05 Rohm And Haas Electronic Materials Llc Organometallic composition
JP2007194336A (en) * 2006-01-18 2007-08-02 Sumco Corp Method for manufacturing semiconductor wafer
JP2007201336A (en) * 2006-01-30 2007-08-09 Hitachi Ltd Forming method of semiconductor laminated body
US7790527B2 (en) * 2006-02-03 2010-09-07 International Business Machines Corporation High-voltage silicon-on-insulator transistors and methods of manufacturing the same
US7901968B2 (en) * 2006-03-23 2011-03-08 Asm America, Inc. Heteroepitaxial deposition over an oxidized surface
US7785995B2 (en) * 2006-05-09 2010-08-31 Asm America, Inc. Semiconductor buffer structures
FR2902233B1 (en) * 2006-06-09 2008-10-17 Soitec Silicon On Insulator METHOD FOR LIMITING LACUNAR MODE BROADCAST DISTRIBUTION IN A HETEROSTRUCTURE
US7608526B2 (en) * 2006-07-24 2009-10-27 Asm America, Inc. Strained layers within semiconductor buffer structures
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
CN100447950C (en) * 2007-01-26 2008-12-31 厦门大学 Method for preparation of GeSi virtual substrate with low dislocation density
DE102007010563A1 (en) * 2007-02-22 2008-08-28 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Selective growth of polycrystalline silicon-containing semiconductor material on a silicon-containing semiconductor surface
US8053810B2 (en) * 2007-09-07 2011-11-08 International Business Machines Corporation Structures having lattice-mismatched single-crystalline semiconductor layers on the same lithographic level and methods of manufacturing the same
US8401774B2 (en) * 2009-01-23 2013-03-19 The Boeing Company System and method for detecting and preventing runway incursion, excursion and confusion
CN101609797B (en) * 2009-07-13 2014-01-01 清华大学 Method for reducing the surface roughness of SiGe virtual substrate
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
FR2953640B1 (en) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, WITH REDUCED ELECTRICAL LOSSES AND CORRESPONDING STRUCTURE
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
CN101916770B (en) * 2010-07-13 2012-01-18 清华大学 Si-Ge-Si semiconductor structure with double graded junctions and forming method thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
EP2474643B1 (en) 2011-01-11 2016-01-06 Imec Method for direct deposition of a germanium layer
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
KR101891373B1 (en) 2011-08-05 2018-08-24 엠아이이 후지쯔 세미컨덕터 리미티드 Semiconductor devices having fin structures and fabrication methods thereof
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
KR20130078136A (en) * 2011-12-30 2013-07-10 에스케이하이닉스 주식회사 Method for manufacturing phase-change random access memory device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
JP5909153B2 (en) * 2012-06-14 2016-04-26 信越化学工業株式会社 Method for producing high-purity polycrystalline silicon
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9171715B2 (en) 2012-09-05 2015-10-27 Asm Ip Holding B.V. Atomic layer deposition of GeO2
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
WO2014071049A2 (en) 2012-10-31 2014-05-08 Suvolta, Inc. Dram-type device with low variation transistor peripheral circuits, and related methods
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US20160376700A1 (en) 2013-02-01 2016-12-29 Asm Ip Holding B.V. System for treatment of deposition reactor
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
FR3006806A1 (en) * 2013-06-07 2014-12-12 St Microelectronics Sa METHOD FOR FORMING COMPONENTS ON A SILICON-GERMANIUM LAYER
CN103474386B (en) * 2013-09-26 2016-02-03 中国科学院上海微***与信息技术研究所 A kind of C of utilization doping SiGe modulating layer prepares the method for SGOI or GOI
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
US9418870B2 (en) 2014-02-12 2016-08-16 International Business Machines Corporation Silicon germanium-on-insulator formation by thermal mixing
US11015245B2 (en) 2014-03-19 2021-05-25 Asm Ip Holding B.V. Gas-phase reactor and system having exhaust plenum and components thereof
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US9305781B1 (en) 2015-04-30 2016-04-05 International Business Machines Corporation Structure and method to form localized strain relaxed SiGe buffer layer
JP6533309B2 (en) * 2015-06-01 2019-06-19 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ Method of manufacturing multilayer structure
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US10256098B2 (en) * 2015-10-29 2019-04-09 Micron Technology, Inc. Integrated assemblies containing germanium
CN106653676B (en) * 2015-11-03 2019-12-24 中芯国际集成电路制造(上海)有限公司 Substrate structure, semiconductor device and manufacturing method
TWI716511B (en) 2015-12-19 2021-01-21 美商應用材料股份有限公司 Conformal amorphous silicon as nucleation layer for w ald process
US10480066B2 (en) 2015-12-19 2019-11-19 Applied Materials, Inc. Metal deposition methods
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US9570300B1 (en) * 2016-02-08 2017-02-14 International Business Machines Corporation Strain relaxed buffer layers with virtually defect free regions
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US9698266B1 (en) * 2016-03-09 2017-07-04 International Business Machines Corporation Semiconductor device strain relaxation buffer layer
US10192775B2 (en) 2016-03-17 2019-01-29 Applied Materials, Inc. Methods for gapfill in high aspect ratio structures
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US9735062B1 (en) * 2016-06-03 2017-08-15 International Business Machines Corporation Defect reduction in channel silicon germanium on patterned silicon
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
KR102532607B1 (en) 2016-07-28 2023-05-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and method of operating the same
KR102629466B1 (en) * 2016-09-21 2024-01-26 에스케이하이닉스 주식회사 Manufacturing method of semiconductor device
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
KR102546317B1 (en) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Gas supply unit and substrate processing apparatus including the same
KR20180068582A (en) 2016-12-14 2018-06-22 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
KR20180070971A (en) 2016-12-19 2018-06-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10529563B2 (en) 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
JP6719415B2 (en) * 2017-03-30 2020-07-08 東京エレクトロン株式会社 Etching method and etching apparatus
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
US10797137B2 (en) 2017-06-30 2020-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method for reducing Schottky barrier height and semiconductor device with reduced Schottky barrier height
KR20190009245A (en) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. Methods for forming a semiconductor device structure and related semiconductor device structures
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US11018002B2 (en) 2017-07-19 2021-05-25 Asm Ip Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
US10541333B2 (en) 2017-07-19 2020-01-21 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11139191B2 (en) 2017-08-09 2021-10-05 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
KR102491945B1 (en) 2017-08-30 2023-01-26 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US11056344B2 (en) 2017-08-30 2021-07-06 Asm Ip Holding B.V. Layer forming method
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US10403504B2 (en) 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US10923344B2 (en) * 2017-10-30 2021-02-16 Asm Ip Holding B.V. Methods for forming a semiconductor structure and related semiconductor structures
US11022879B2 (en) 2017-11-24 2021-06-01 Asm Ip Holding B.V. Method of forming an enhanced unexposed photoresist layer
TWI791689B (en) 2017-11-27 2023-02-11 荷蘭商Ａｓｍ智慧財產控股私人有限公司 Apparatus including a clean mini environment
WO2019103613A1 (en) 2017-11-27 2019-05-31 Asm Ip Holding B.V. A storage device for storing wafer cassettes for use with a batch furnace
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
TWI799494B (en) 2018-01-19 2023-04-21 荷蘭商Ａｓｍ 智慧財產控股公司 Deposition method
US11482412B2 (en) 2018-01-19 2022-10-25 Asm Ip Holding B.V. Method for depositing a gap-fill layer by plasma-assisted deposition
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
CN111699278B (en) 2018-02-14 2023-05-16 Asm Ip私人控股有限公司 Method for depositing ruthenium-containing films on substrates by cyclical deposition processes
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
KR102636427B1 (en) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. Substrate processing method and apparatus
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
US11114283B2 (en) 2018-03-16 2021-09-07 Asm Ip Holding B.V. Reactor, system including the reactor, and methods of manufacturing and using same
KR102646467B1 (en) 2018-03-27 2024-03-11 에이에스엠 아이피 홀딩 비.브이. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
US11088002B2 (en) 2018-03-29 2021-08-10 Asm Ip Holding B.V. Substrate rack and a substrate processing system and method
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR20190128558A (en) 2018-05-08 2019-11-18 에이에스엠 아이피 홀딩 비.브이. Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
KR102596988B1 (en) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US11270899B2 (en) 2018-06-04 2022-03-08 Asm Ip Holding B.V. Wafer handling chamber with moisture reduction
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
KR102568797B1 (en) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing system
WO2020002995A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
KR20210027265A (en) 2018-06-27 2021-03-10 에이에스엠 아이피 홀딩 비.브이. Periodic deposition method for forming metal-containing material and film and structure comprising metal-containing material
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US11053591B2 (en) 2018-08-06 2021-07-06 Asm Ip Holding B.V. Multi-port gas injection system and reactor system including same
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
KR20200030162A (en) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. Method for deposition of a thin film
US11049751B2 (en) 2018-09-14 2021-06-29 Asm Ip Holding B.V. Cassette supply system to store and handle cassettes and processing apparatus equipped therewith
CN110970344A (en) 2018-10-01 2020-04-07 Asm Ip控股有限公司 Substrate holding apparatus, system including the same, and method of using the same
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102592699B1 (en) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same
KR102546322B1 (en) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
KR102605121B1 (en) 2018-10-19 2023-11-23 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
USD948463S1 (en) 2018-10-24 2022-04-12 Asm Ip Holding B.V. Susceptor for semiconductor substrate supporting apparatus
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (en) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and substrate processing apparatus including the same
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US11031242B2 (en) 2018-11-07 2021-06-08 Asm Ip Holding B.V. Methods for depositing a boron doped silicon germanium film
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US10847366B2 (en) 2018-11-16 2020-11-24 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
KR102636428B1 (en) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. A method for cleaning a substrate processing apparatus
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
JP2020096183A (en) 2018-12-14 2020-06-18 エーエスエム・アイピー・ホールディング・ベー・フェー Method of forming device structure using selective deposition of gallium nitride, and system for the same
TW202405220A (en) 2019-01-17 2024-02-01 荷蘭商Ａｓｍ Ｉｐ 私人控股有限公司 Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
KR20200091543A (en) 2019-01-22 2020-07-31 에이에스엠 아이피 홀딩 비.브이. Semiconductor processing device
CN111524788B (en) 2019-02-01 2023-11-24 Asm Ip私人控股有限公司 Method for topologically selective film formation of silicon oxide
KR20200102357A (en) 2019-02-20 2020-08-31 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for plug fill deposition in 3-d nand applications
KR102626263B1 (en) 2019-02-20 2024-01-16 에이에스엠 아이피 홀딩 비.브이. Cyclical deposition method including treatment step and apparatus for same
KR102638425B1 (en) 2019-02-20 2024-02-21 에이에스엠 아이피 홀딩 비.브이. Method and apparatus for filling a recess formed within a substrate surface
JP2020136677A (en) 2019-02-20 2020-08-31 エーエスエム・アイピー・ホールディング・ベー・フェー Periodic accumulation method for filing concave part formed inside front surface of base material, and device
JP2020133004A (en) 2019-02-22 2020-08-31 エーエスエム・アイピー・ホールディング・ベー・フェー Base material processing apparatus and method for processing base material
KR20200108242A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer
KR20200108248A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. STRUCTURE INCLUDING SiOCN LAYER AND METHOD OF FORMING SAME
KR20200108243A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Structure Including SiOC Layer and Method of Forming Same
JP2020167398A (en) 2019-03-28 2020-10-08 エーエスエム・アイピー・ホールディング・ベー・フェー Door opener and substrate processing apparatus provided therewith
KR20200116855A (en) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. Method of manufacturing semiconductor device
US11447864B2 (en) 2019-04-19 2022-09-20 Asm Ip Holding B.V. Layer forming method and apparatus
KR20200125453A (en) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system and method of using same
KR20200130118A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Method for Reforming Amorphous Carbon Polymer Film
KR20200130121A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Chemical source vessel with dip tube
KR20200130652A (en) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. Method of depositing material onto a surface and structure formed according to the method
JP2020188254A (en) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー．ブイ． Wafer boat handling device, vertical batch furnace, and method
JP2020188255A (en) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー．ブイ． Wafer boat handling device, vertical batch furnace, and method
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
USD935572S1 (en) 2019-05-24 2021-11-09 Asm Ip Holding B.V. Gas channel plate
USD922229S1 (en) 2019-06-05 2021-06-15 Asm Ip Holding B.V. Device for controlling a temperature of a gas supply unit
KR20200141002A (en) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. Method of using a gas-phase reactor system including analyzing exhausted gas
KR20200143254A (en) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
USD931978S1 (en) 2019-06-27 2021-09-28 Asm Ip Holding B.V. Showerhead vacuum transport
KR20210005515A (en) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. Temperature control assembly for substrate processing apparatus and method of using same
JP2021015791A (en) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー．ブイ． Plasma device and substrate processing method using coaxial waveguide
CN112216646A (en) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 Substrate supporting assembly and substrate processing device comprising same
KR20210010307A (en) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210010820A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Methods of forming silicon germanium structures
KR20210010816A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Radical assist ignition plasma system and method
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
JP2021019198A (en) 2019-07-19 2021-02-15 エーエスエム・アイピー・ホールディング・ベー・フェー Method of forming topology-controlled amorphous carbon polymer film
TW202113936A (en) 2019-07-29 2021-04-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation
CN112309899A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112309900A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
KR20210018759A (en) 2019-08-05 2021-02-18 에이에스엠 아이피 홀딩 비.브이. Liquid level sensor for a chemical source vessel
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
JP2021031769A (en) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー．ブイ． Production apparatus of mixed gas of film deposition raw material and film deposition apparatus
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
KR20210024423A (en) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for forming a structure with a hole
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
USD930782S1 (en) 2019-08-22 2021-09-14 Asm Ip Holding B.V. Gas distributor
KR20210024420A (en) 2019-08-23 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210029090A (en) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. Methods for selective deposition using a sacrificial capping layer
KR20210029663A (en) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11133178B2 (en) 2019-09-20 2021-09-28 Applied Materials, Inc. Seamless gapfill with dielectric ALD films
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (en) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process
TW202129060A (en) 2019-10-08 2021-08-01 荷蘭商Ａｓｍ Ｉｐ控股公司 Substrate processing device, and substrate processing method
TW202115273A (en) 2019-10-10 2021-04-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming a photoresist underlayer and structure including same
KR20210045930A (en) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. Method of Topology-Selective Film Formation of Silicon Oxide
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (en) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for selectively etching films
KR20210050453A (en) 2019-10-25 2021-05-07 에이에스엠 아이피 홀딩 비.브이. Methods for filling a gap feature on a substrate surface and related semiconductor structures
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR20210054983A (en) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. Structures with doped semiconductor layers and methods and systems for forming same
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (en) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
KR20210065848A (en) 2019-11-26 2021-06-04 에이에스엠 아이피 홀딩 비.브이. Methods for selectivley forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
CN112951697A (en) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112885693A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112885692A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
JP2021090042A (en) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー．ブイ． Substrate processing apparatus and substrate processing method
KR20210070898A (en) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
TW202125596A (en) 2019-12-17 2021-07-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming vanadium nitride layer and structure including the vanadium nitride layer
KR20210080214A (en) 2019-12-19 2021-06-30 에이에스엠 아이피 홀딩 비.브이. Methods for filling a gap feature on a substrate and related semiconductor structures
TW202140135A (en) 2020-01-06 2021-11-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Gas supply assembly and valve plate assembly
US11993847B2 (en) 2020-01-08 2024-05-28 Asm Ip Holding B.V. Injector
KR20210095050A (en) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. Method of forming thin film and method of modifying surface of thin film
TW202130846A (en) 2020-02-03 2021-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming structures including a vanadium or indium layer
KR20210100010A (en) 2020-02-04 2021-08-13 에이에스엠 아이피 홀딩 비.브이. Method and apparatus for transmittance measurements of large articles
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
TW202146715A (en) 2020-02-17 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for growing phosphorous-doped silicon layer and system of the same
TW202203344A (en) 2020-02-28 2022-01-16 荷蘭商Ａｓｍ Ｉｐ控股公司 System dedicated for parts cleaning
KR20210116249A (en) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. lockout tagout assembly and system and method of using same
KR20210116240A (en) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. Substrate handling device with adjustable joints
KR20210117157A (en) 2020-03-12 2021-09-28 에이에스엠 아이피 홀딩 비.브이. Method for Fabricating Layer Structure Having Target Topological Profile
US11101128B1 (en) * 2020-03-12 2021-08-24 Applied Materials, Inc. Methods for gapfill in substrates
KR20210124042A (en) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. Thin film forming method
TW202146689A (en) 2020-04-03 2021-12-16 荷蘭商Ａｓｍ Ｉｐ控股公司 Method for forming barrier layer and method for manufacturing semiconductor device
TW202145344A (en) 2020-04-08 2021-12-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Apparatus and methods for selectively etching silcon oxide films
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
US11996289B2 (en) 2020-04-16 2024-05-28 Asm Ip Holding B.V. Methods of forming structures including silicon germanium and silicon layers, devices formed using the methods, and systems for performing the methods
CN113555279A (en) 2020-04-24 2021-10-26 Asm Ip私人控股有限公司 Method of forming vanadium nitride-containing layers and structures including the same
KR20210132600A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
TW202146831A (en) 2020-04-24 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Vertical batch furnace assembly, and method for cooling vertical batch furnace
KR20210134226A (en) 2020-04-29 2021-11-09 에이에스엠 아이피 홀딩 비.브이. Solid source precursor vessel
KR20210134869A (en) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Fast FOUP swapping with a FOUP handler
KR20210141379A (en) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. Laser alignment fixture for a reactor system
TW202147383A (en) 2020-05-19 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing apparatus
KR20210145078A (en) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. Structures including multiple carbon layers and methods of forming and using same
KR20210145080A (en) 2020-05-22 2021-12-01 에이에스엠 아이피 홀딩 비.브이. Apparatus for depositing thin films using hydrogen peroxide
TW202201602A (en) 2020-05-29 2022-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing device
TW202218133A (en) 2020-06-24 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for forming a layer provided with silicon
TW202217953A (en) 2020-06-30 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing method
TW202219628A (en) 2020-07-17 2022-05-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Structures and methods for use in photolithography
TW202204662A (en) 2020-07-20 2022-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method and system for depositing molybdenum layers
TW202212623A (en) 2020-08-26 2022-04-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming metal silicon oxide layer and metal silicon oxynitride layer, semiconductor structure, and system
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (en) 2020-10-14 2022-08-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of depositing material on stepped structure
KR20220053482A (en) 2020-10-22 2022-04-29 에이에스엠 아이피 홀딩 비.브이. Method of depositing vanadium metal, structure, device and a deposition assembly
TW202223136A (en) 2020-10-28 2022-06-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for forming layer on substrate, and semiconductor processing system
TW202235675A (en) 2020-11-30 2022-09-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Injector, and substrate processing apparatus
CN114639631A (en) 2020-12-16 2022-06-17 Asm Ip私人控股有限公司 Fixing device for measuring jumping and swinging
TW202231903A (en) 2020-12-22 2022-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD1023959S1 (en) 2021-05-11 2024-04-23 Asm Ip Holding B.V. Electrode for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63240012A (en) * 1987-03-27 1988-10-05 Nec Corp Iii-v compound semiconductor and formation thereof
JPH0444431B2 (en) * 1984-02-01 1992-07-21 Hitachi Ltd
JPH0562911A (en) * 1991-09-04 1993-03-12 Fujitsu Ltd Manufacture of semiconductor superlattice
JPH10116787A (en) * 1996-10-15 1998-05-06 Fujitsu Ltd Electron beam excited solid phase growth method
JP2003031495A (en) * 2001-07-12 2003-01-31 Hitachi Ltd Manufacturing method of semiconductor device substrate and semiconductor device
JP2004363198A (en) * 2003-06-02 2004-12-24 Sumitomo Mitsubishi Silicon Corp Method of producing strained silicon soi substrate
JP2005050984A (en) * 2003-06-02 2005-02-24 Sumitomo Mitsubishi Silicon Corp Method for manufacturing strain si-soi substrate and strain si-soi substrate manufactured thereby

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4363828A (en) * 1979-12-12 1982-12-14 International Business Machines Corp. Method for depositing silicon films and related materials by a glow discharge in a disiland or higher order silane gas
JPH03185712A (en) * 1989-12-14 1991-08-13 Fujitsu Ltd Manufacture of semiconductor device
JP3033155B2 (en) * 1990-08-22 2000-04-17 日本電気株式会社 Method for manufacturing semiconductor device
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US5385864A (en) * 1993-05-28 1995-01-31 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor thin film and a Hall-effect device
JP2003178990A (en) * 1993-09-08 2003-06-27 Seiko Epson Corp Substrate heat treatment method, method of manufacturing semiconductor device, chemical vapor deposition method and display
JP2953567B2 (en) 1997-02-06 1999-09-27 日本電気株式会社 Method for manufacturing semiconductor device
JP3727449B2 (en) * 1997-09-30 2005-12-14 シャープ株式会社 Method for producing semiconductor nanocrystal
DE19802977A1 (en) * 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Single crystal layer production on a non-lattice-matched single crystal substrate in microelectronic or optoelectronics component manufacture
FR2783254B1 (en) 1998-09-10 2000-11-10 France Telecom METHOD FOR OBTAINING A LAYER OF MONOCRYSTALLINE GERMANIUM ON A MONOCRYSTALLINE SILICON SUBSTRATE, AND PRODUCTS OBTAINED
US6740247B1 (en) * 1999-02-05 2004-05-25 Massachusetts Institute Of Technology HF vapor phase wafer cleaning and oxide etching
US6255195B1 (en) * 1999-02-22 2001-07-03 Intersil Corporation Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method
US6346732B1 (en) * 1999-05-14 2002-02-12 Kabushiki Kaisha Toshiba Semiconductor device with oxide mediated epitaxial layer
US6411548B1 (en) * 1999-07-13 2002-06-25 Kabushiki Kaisha Toshiba Semiconductor memory having transistors connected in series
US6461945B1 (en) * 2000-06-22 2002-10-08 Advanced Micro Devices, Inc. Solid phase epitaxy process for manufacturing transistors having silicon/germanium channel regions
US6274463B1 (en) * 2000-07-31 2001-08-14 Hewlett-Packard Company Fabrication of a photoconductive or a cathoconductive device using lateral solid overgrowth method
JP2002184993A (en) * 2000-12-11 2002-06-28 Sony Corp Semiconductor device
KR100385857B1 (en) * 2000-12-27 2003-06-02 한국전자통신연구원 Fabrication Method of SiGe MODFET with a Metal-Oxide Gate
EP1421607A2 (en) * 2001-02-12 2004-05-26 ASM America, Inc. Improved process for deposition of semiconductor films
JP2002270507A (en) * 2001-03-14 2002-09-20 Hitachi Cable Ltd Crystal silicon layer forming method and crystal silicon semiconductor device
US6482705B1 (en) * 2001-04-03 2002-11-19 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having a MOSFET with an amorphous SiGe gate electrode and an elevated crystalline SiGe source/drain structure and a device thereby formed
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
JP3660897B2 (en) * 2001-09-03 2005-06-15 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
JP2003128494A (en) * 2001-10-22 2003-05-08 Sharp Corp Method for producing semiconductor device and semiconductor device
US6875279B2 (en) * 2001-11-16 2005-04-05 International Business Machines Corporation Single reactor, multi-pressure chemical vapor deposition for semiconductor devices
US6555439B1 (en) * 2001-12-18 2003-04-29 Advanced Micro Devices, Inc. Partial recrystallization of source/drain region before laser thermal annealing
US20030124818A1 (en) * 2001-12-28 2003-07-03 Applied Materials, Inc. Method and apparatus for forming silicon containing films
US6746902B2 (en) * 2002-01-31 2004-06-08 Sharp Laboratories Of America, Inc. Method to form relaxed sige layer with high ge content
US6723622B2 (en) * 2002-02-21 2004-04-20 Intel Corporation Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer
US6562703B1 (en) * 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
JP2003318110A (en) * 2002-04-23 2003-11-07 Hitachi Ltd Semiconductor substrate, its manufacturing method, and method for manufacturing semiconductor device
JP4951202B2 (en) * 2002-05-07 2012-06-13 エーエスエム アメリカ インコーポレイテッド Method for manufacturing silicon-on-insulator structure
US6689671B1 (en) * 2002-05-22 2004-02-10 Advanced Micro Devices, Inc. Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate
AU2002368035A1 (en) * 2002-06-19 2004-01-06 Massachusetts Institute Of Technology Ge photodetectors
US6774015B1 (en) * 2002-12-19 2004-08-10 International Business Machines Corporation Strained silicon-on-insulator (SSOI) and method to form the same
US6987037B2 (en) * 2003-05-07 2006-01-17 Micron Technology, Inc. Strained Si/SiGe structures by ion implantation
US7029995B2 (en) * 2003-06-13 2006-04-18 Asm America, Inc. Methods for depositing amorphous materials and using them as templates for epitaxial films by solid phase epitaxy
KR20060056331A (en) * 2003-07-23 2006-05-24 에이에스엠 아메리카, 인코포레이티드 Deposition of sige on silicon-on-insulator structures and bulk substrates
US6881158B2 (en) * 2003-07-24 2005-04-19 Fu Sheng Industrial Co., Ltd. Weight number for a golf club head
US7132338B2 (en) * 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US20050148162A1 (en) * 2004-01-02 2005-07-07 Huajie Chen Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444431B2 (en) * 1984-02-01 1992-07-21 Hitachi Ltd
JPS63240012A (en) * 1987-03-27 1988-10-05 Nec Corp Iii-v compound semiconductor and formation thereof
JPH0562911A (en) * 1991-09-04 1993-03-12 Fujitsu Ltd Manufacture of semiconductor superlattice
JPH10116787A (en) * 1996-10-15 1998-05-06 Fujitsu Ltd Electron beam excited solid phase growth method
JP2003031495A (en) * 2001-07-12 2003-01-31 Hitachi Ltd Manufacturing method of semiconductor device substrate and semiconductor device
JP2004363198A (en) * 2003-06-02 2004-12-24 Sumitomo Mitsubishi Silicon Corp Method of producing strained silicon soi substrate
JP2005050984A (en) * 2003-06-02 2005-02-24 Sumitomo Mitsubishi Silicon Corp Method for manufacturing strain si-soi substrate and strain si-soi substrate manufactured thereby

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8927363B2 (en) 2013-05-17 2015-01-06 International Business Machines Corporation Integrating channel SiGe into pFET structures
US9818761B2 (en) 2015-06-25 2017-11-14 International Business Machines Corporation Selective oxidation for making relaxed silicon germanium on insulator structures

Also Published As

Publication number Publication date
US20070042572A1 (en) 2007-02-22
KR20060056331A (en) 2006-05-24
US20050054175A1 (en) 2005-03-10
JP5601595B2 (en) 2014-10-08
WO2005010946A2 (en) 2005-02-03
JP2007505477A (en) 2007-03-08
WO2005010946A3 (en) 2006-09-08
EP1647046A2 (en) 2006-04-19
US7208354B2 (en) 2007-04-24

Similar Documents

Publication Publication Date Title
JP5601595B2 (en) Silicon-on-insulator structures and SiGe deposition on bulk substrates
US7416909B2 (en) Methods for preserving strained semiconductor substrate layers during CMOS processing
US9337026B2 (en) Graphene growth on a carbon-containing semiconductor layer
US20060057403A1 (en) Use of thin SOI to inhibit relaxation of SiGe layers
JP2005516395A (en) Strain-relieved SiGe-on-insulator and method for manufacturing the same
JP2006524426A (en) Method and layer structure for producing strained layers on a substrate
KR20070059157A (en) Semiconductor wafer manufacturing method
JPH09321307A (en) Semiconductor device
US7416957B2 (en) Method for forming a strained Si-channel in a MOSFET structure
JP2019195066A (en) Multilayer structure
US7141115B2 (en) Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers
US11688629B2 (en) Low-temperature method for manufacturing a semiconductor-on-insulator substrate
US7202142B2 (en) Method for producing low defect density strained -Si channel MOSFETS
JP2004146472A (en) Semiconductor device and its manufacturing method
JP2008130726A (en) Method for manufacturing semiconductor device
JPH07226516A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20130726

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130917

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131022

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131204

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140304

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140320

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140722

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140807

R150 Certificate of patent or registration of utility model

Ref document number: 5601595

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250