JP2012177927A - アクティブマトリクス基板、表示装置、アクティブマトリクス基板の製造方法または検査方法、および表示装置の製造方法または検査方法 - Google Patents
アクティブマトリクス基板、表示装置、アクティブマトリクス基板の製造方法または検査方法、および表示装置の製造方法または検査方法 Download PDFInfo
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Abstract
【解決手段】アクティブマトリクス基板2は、引出配線611,613,615,617が接続されたゲート端子51に接続される第1接続配線641,643,645,647と、引出配線612,614,616が接続されたゲート端子51に接続される第2接続配線642,644,646と、互いに隣接する2本の第1接続配線および第2接続配線を1本に束ねる束配線651〜654と、束配線のうちで互いに隣接しない束配線652,654へ検査信号を入力可能な第1検査配線66と、束配線のうち第1検査配線66が接続されておらずかつ互いに隣接しない束配線651,653へ検査信号を入力可能な第2検査配線67とを備える。
【選択図】図3
Description
図1は、本実施形態に係る液晶パネル1の概略構成を示す平面図である。図1に示すように、液晶パネル1は、アクティブマトリクス基板2と、アクティブマトリクス基板2に対向する対向基板3とを備えている。アクティブマトリクス基板2と対向基板3との間には、図示しない液晶材料が狭持されている。なお、本実施形態に係る対向基板3には、R(赤)、G(緑)、B(青)のカラーフィルタと、これらのカラーフィルタ間の光漏れを防止するブラックマトリクスとを含むカラーフィルタ層が形成されている。また、カラーフィルタ層の上には、共通電極が形成されている。
図6は、図1中に示したE1の部分と同じ部分を拡大した図である。図6に示すように、本実施形態に係るゲート用右側接続配線641〜647のそれぞれには、抵抗素子Rがさらに接続されている。ここで、抵抗素子Rは、例えば、画素電極として用いられるITOやIZO等で形成したパターン、TFTの半導体膜で形成したパターン、ダイオード、トランジスタ、任意のパターン等から構成される。なお、本実施形態に係るゲート用左側接続配線721〜727のそれぞれにも、抵抗素子Rがさらに接続されている。
Claims (15)
- 表示領域に互いに平行に形成された複数の第1配線と、
端子配置領域に配置された複数の第1端子と、
前記複数の第1配線と前記複数の第1端子とを各々接続する複数の第1引出配線と、
を備えたアクティブマトリクス基板において、
前記複数の第1引出配線の各々は、前記表示領域以外の領域で隣接して交互に形成される第2配線または第3配線と、前記第1端子を介して接続しており、
前記第2配線および第3配線を各々束ねる複数の束配線と接続した共通配線を備えた、アクティブマトリクス基板。 - 前記第2配線と接続する前記第1引出配線は、前記第1配線が形成された層と同じ層に形成されており、前記第3配線と接続する前記第1引出配線の少なくとも一部分は、前記第1配線が形成された層と絶縁材料を挟んで異なる層に形成された、請求項1に記載のアクティブマトリクス基板。
- 前記複数の束配線のうちで互いに隣接しない束配線を接続する第1共通配線と、
前記複数の束配線のうち前記第1共通配線が接続されておらずかつ互いに隣接しない束配線を接続する第2共通配線とを備えた、請求項1または2に記載のアクティブマトリクス基板。 - 前記複数の第2配線が接続された複数の第1端子と、
前記複数の第3配線が接続された複数の第1端子とが電気的に導通しないように切断された部位を含む、
請求項1〜3のいずれか一項に記載のアクティブマトリクス基板。 - 互いに隣接する前記第2配線および前記第3配線のうちの少なくともいずれか一方に、抵抗素子が接続された、請求項1〜3のいずれか一項に記載のアクティブマトリクス基板。
- 互いに隣接する2本の前記第2配線および前記第3配線のそれぞれに抵抗素子が接続される、請求項5に記載のアクティブマトリクス基板。
- 前記第2配線に接続された抵抗素子と、前記第3配線に接続された抵抗素子とは、略同じ抵抗値を有する、請求項6に記載のアクティブマトリクス基板。
- 前記複数の束配線のそれぞれが切断されている、請求項5〜7のいずれか一項に記載のアクティブマトリクス基板。
- 前記第1配線は、ソース配線またはゲート配線である、請求項1〜8の何れか一項に記載のアクティブマトリクス基板。
- 請求項1〜9の何れか一項に記載のアクティブマトリクス基板を備える、表示装置。
- 前記表示装置は液晶表示装置である、請求項10に記載の表示装置。
- 請求項1〜3のいずれか一項に記載のアクティブマトリクス基板、または、請求項1〜3のいずれか一項に記載のアクティブマトリクス基板を備えた表示装置の製造方法であって、
前記複数の第2配線および前記複数の第3配線を切断する切断工程を含む、アクティブマトリクス基板または表示装置の製造方法。 - 請求項5に記載のアクティブマトリクス基板、または、請求項5に記載のアクティブマトリクス基板を備えた表示装置の製造査方法であって、
前記複数の束配線を切断する切断工程を含む、アクティブマトリクス基板または表示装置の製造方法。 - 請求項1〜3のいずれか一項に記載のアクティブマトリクス基板、または、請求項1〜3のいずれか一項に記載のアクティブマトリクス基板を備えた表示装置の検査方法であって、
前記共通配線に検査信号を入力することにより、前記第1引出配線の検査を行う検査工程と、
前記検査工程の後に、前記複数の第2配線および前記複数の第3配線を切断する切断工程とを含む、アクティブマトリクス基板または表示装置の検査方法。 - 請求項5に記載のアクティブマトリクス基板、または、請求項5に記載のアクティブマトリクス基板を備えた表示装置の検査方法であって、
前記共通配線に検査信号を入力することにより、前記第1引出配線の検査を行う検査工程と、
前記検査工程の後に、前記複数の束配線を切断する切断工程とを含む、アクティブマトリクス基板または表示装置の検査方法。
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KR (1) | KR101247023B1 (ja) |
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KR20150069609A (ko) * | 2013-12-13 | 2015-06-24 | 엘지디스플레이 주식회사 | 표시장치 및 표시패널 |
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KR20110031503A (ko) | 2011-03-28 |
RU2011106755A (ru) | 2012-08-27 |
JP5438798B2 (ja) | 2014-03-12 |
EP2797069A1 (en) | 2014-10-29 |
US8502227B2 (en) | 2013-08-06 |
JPWO2010010750A1 (ja) | 2012-01-05 |
EP2317492A4 (en) | 2011-12-21 |
WO2010010750A1 (ja) | 2010-01-28 |
EP2797069B1 (en) | 2019-07-10 |
US20130299850A1 (en) | 2013-11-14 |
CN102099847A (zh) | 2011-06-15 |
US9299877B2 (en) | 2016-03-29 |
EP2317492A1 (en) | 2011-05-04 |
RU2475866C2 (ru) | 2013-02-20 |
CN102099847B (zh) | 2013-03-13 |
BRPI0917025A2 (pt) | 2016-02-16 |
EP2317492B1 (en) | 2014-05-14 |
US20110127536A1 (en) | 2011-06-02 |
KR101247023B1 (ko) | 2013-03-25 |
JP4982609B2 (ja) | 2012-07-25 |
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