JP2012160637A - 半導体装置及びその製造方法、並びにsoi基板及びその製造方法 - Google Patents
半導体装置及びその製造方法、並びにsoi基板及びその製造方法 Download PDFInfo
- Publication number
- JP2012160637A JP2012160637A JP2011020521A JP2011020521A JP2012160637A JP 2012160637 A JP2012160637 A JP 2012160637A JP 2011020521 A JP2011020521 A JP 2011020521A JP 2011020521 A JP2011020521 A JP 2011020521A JP 2012160637 A JP2012160637 A JP 2012160637A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- insulating film
- semiconductor device
- manufacturing
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 189
- 239000000758 substrate Substances 0.000 title claims abstract description 104
- 238000004519 manufacturing process Methods 0.000 title claims description 45
- 238000002955 isolation Methods 0.000 claims abstract description 41
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 89
- 238000005530 etching Methods 0.000 claims description 45
- 238000009792 diffusion process Methods 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 37
- 239000011229 interlayer Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 210000000746 body region Anatomy 0.000 claims description 8
- 230000007547 defect Effects 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 21
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 description 21
- 230000008569 process Effects 0.000 description 13
- 239000007789 gas Substances 0.000 description 10
- 238000001459 lithography Methods 0.000 description 7
- 230000000149 penetrating effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- -1 SiOC Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000001900 extreme ultraviolet lithography Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011819 refractory material Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000000233 ultraviolet lithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】半導体装置1は、半導体基材11と埋め込み絶縁膜12と半導体層16とを有するSOI基板と、このSOI基板上に形成された半導体素子構造とを備える。埋め込み絶縁膜12は、半導体基材11から半導体層16を電気的に絶縁分離する機能を有し、窒化膜14を有する。
【選択図】図1
Description
Claims (25)
- 半導体基材と、
半導体層と、
前記半導体基材と前記半導体層とに挟み込まれ、前記半導体基材から前記半導体層を電気的に絶縁分離する埋め込み絶縁膜と
を備え、
前記埋め込み絶縁膜は、窒化膜を含む
ことを特徴とするSOI基板。 - 請求項1に記載のSOI基板であって、前記窒化膜は、シリコン窒化膜であることを特徴とするSOI基板。
- 請求項2に記載のSOI基板であって、
前記埋め込み絶縁膜は、埋め込み酸化膜を含み、
前記埋め込み酸化膜は、シリコン酸化膜である
ことを特徴とするSOI基板。 - 請求項3に記載のSOI基板であって、前記シリコン酸化膜は、熱酸化膜であることを特徴とするSOI基板。
- 請求項3または4に記載のSOI基板であって、前記窒化膜は、化学気相成長法を用いて前記埋め込み酸化膜上に形成された膜であることを特徴とするSOI基板。
- 請求項1から5のうちのいずれか1項に記載のSOI基板と、
前記SOI基板上に形成された半導体素子構造と
を備えることを特徴とする半導体装置。 - 請求項6に記載の半導体装置であって、
前記半導体素子構造は、
前記SOI基板の当該半導体層の上に形成され、コンタクトホールを有する層間絶縁膜と、
前記コンタクトホールに埋め込まれ、前記半導体層と電気的に接続されたコンタクトプラグと
を含むことを特徴とする半導体装置。 - 請求項7に記載の半導体装置であって、
前記半導体素子構造は、前記半導体層上にゲート絶縁膜とゲート電極とを含むゲート構造を有し、
前記半導体層は、
互いに同じ導電型を有し前記ゲート構造の両側に形成された第1及び第2の不純物拡散領域と、
前記第1及び第2の不純物拡散領域の間に且つ前記ゲート構造の直下に形成されたボディ領域と
を含み、
前記第1及び第2の不純物拡散領域のいずれか一方が前記コンタクトプラグと電気的に接続されている
ことを特徴とする半導体装置。 - 請求項8に記載の半導体装置であって、
前記コンタクトホールの形成領域が素子分離領域と重複しており、
前記半導体層は、前記素子分離領域を画定するメサ形状の凸部を有する、
ことを特徴とする半導体装置。 - 請求項9に記載の半導体装置であって、前記凸部の側壁下端が前記埋め込み絶縁膜の上面に達していることを特徴とする半導体装置。
- 請求項8に記載の半導体装置であって、
前記半導体基板の上面から前記埋め込み絶縁膜に至るまで深さ方向に延在する素子分離用絶縁膜をさらに備え、
前記コンタクトホールの形成領域は、前記素子分離用絶縁膜の形成領域と重複している
ことを特徴とする半導体装置。 - 請求項8から11のうちのいずれか1項に記載の半導体装置であって、前記半導体層と前記コンタクトプラグとの間に介在し前記半導体層を下地として形成されたエピタキシャル層をさらに備えることを特徴とする半導体装置。
- 請求項1から5のうちのいずれか1項に記載のSOI基板を用意する工程と、
前記SOI基板上に半導体素子構造を形成する工程と
を備えることを特徴とする半導体装置の製造方法。 - 請求項13に記載の半導体装置の製造方法であって、
前記半導体素子構造を形成する当該工程は、
前記SOI基板の当該半導体層の上に層間絶縁膜を堆積する工程と、
所定のエッチング条件にて前記層間絶縁膜を選択的にエッチングしてコンタクトホールを形成する工程と、
前記半導体層と電気的に接続されたコンタクトプラグを前記コンタクトホールに埋め込む工程と
を含むことを特徴とする半導体装置の製造方法。 - 請求項14に記載の半導体装置の製造方法であって、
互いに同じ導電型の不純物を前記半導体層内に導入して第1及び第2の不純物拡散領域を形成する工程をさらに備え、
前記半導体素子構造を形成する当該工程は、前記半導体層上にゲート絶縁膜とゲート電極とを含むゲート構造を形成する工程を含み、
前記第1及び第2の不純物拡散領域は、前記ゲート構造をマスクとして前記半導体層内に前記不純物を導入することにより前記ゲート構造の両側に形成された領域であり、
前記第1及び第2の不純物拡散領域のいずれか一方が前記コンタクトプラグと電気的に接続される
ことを特徴とする半導体装置の製造方法。 - 請求項15に記載の半導体装置の製造方法であって、前記半導体層を選択的にエッチングして、素子分離領域を画定するメサ形状の凸部を形成する工程をさらに備え、
前記コンタクトホールの形成領域が前記素子分離領域と重複する
ことを特徴とする半導体装置の製造方法。 - 請求項16に記載の半導体装置の製造方法であって、前記半導体層を選択的にエッチングする当該工程では、前記凸部の側壁下端が前記埋め込み絶縁膜の上面に達するまでエッチングが実行されることを特徴とする半導体装置の製造方法。
- 請求項15に記載の半導体装置の製造方法であって、前記半導体基板の上面から前記埋め込み絶縁膜に至るまで深さ方向に延在する素子分離用絶縁膜を形成する工程をさらに備え、
前記コンタクトホールの形成領域は、前記素子分離用絶縁膜の形成領域と重複する
ことを特徴とする半導体装置の製造方法。 - 請求項14から18のうちのいずれか1項に記載の半導体装置の製造方法であって、
前記コンタクトホールが形成される前に、選択的エピタキシャル成長法により前記半導体層を下地としてエピタキシャル層を形成する工程をさらに備え、
前記コンタクトホールは、前記エピタキシャル層上に形成される
ことを特徴とする半導体装置の製造方法。 - 半導体層を含む第1の半導体基材を用意する工程と、
第2の半導体基材の主面上に窒化膜を含む絶縁膜を形成する工程と、
前記第2の半導体基材上の当該絶縁膜と前記第1の半導体基材の当該半導体層とを貼り合わせる工程と
を備え、
前記絶縁膜は、前記半導体層を前記第2の半導体基材から電気的に絶縁分離するように形成されることを特徴とするSOI基板の製造方法。 - 請求項20に記載のSOI基板の製造方法であって、
前記第1の半導体基材に不純物イオンを打ち込むことにより一定の深さで分布する欠陥層を形成する工程と、
当該貼り合わせる工程が完了した後に、前記欠陥層を境にして前記第1の半導体基材を2片に分割することにより前記半導体層を前記第1の半導体基材から剥離する工程と
をさらに備えることを特徴とするSOI基板の製造方法。 - 請求項20または21に記載のSOI基板の製造方法であって、前記窒化膜は、シリコン窒化膜であることを特徴とするSOI基板の製造方法。
- 請求項20から22のうちのいずれか1項に記載のSOI基板の製造方法であって、
前記絶縁膜を形成する工程は、
前記第2の半導体基材の主面上に酸化膜を形成する工程と、
前記酸化膜上に前記窒化膜を形成する工程とを含み、
前記酸化膜は、シリコン酸化膜である
ことを特徴とするSOI基板の製造方法。 - 請求項23に記載のSOI基板の製造方法であって、前記酸化膜は、前記第2の半導体基材の当該主面を熱酸化することで形成されることを特徴とするSOI基板の製造方法。
- 請求項23または24に記載のSOI基板の製造方法であって、前記窒化膜は、化学気相成長法を用いて前記酸化膜上に形成されることを特徴とするSOI基板の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011020521A JP6076584B2 (ja) | 2011-02-02 | 2011-02-02 | 半導体装置及びその製造方法 |
US13/362,093 US9136386B2 (en) | 2011-02-02 | 2012-01-31 | SOI substrate, method of manufacturing the SOI substrate, semiconductor device, and method of manufacturing the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011020521A JP6076584B2 (ja) | 2011-02-02 | 2011-02-02 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012160637A true JP2012160637A (ja) | 2012-08-23 |
JP6076584B2 JP6076584B2 (ja) | 2017-02-08 |
Family
ID=46576642
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011020521A Active JP6076584B2 (ja) | 2011-02-02 | 2011-02-02 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9136386B2 (ja) |
JP (1) | JP6076584B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014041822A1 (ja) * | 2012-09-14 | 2014-03-20 | 独立行政法人産業技術総合研究所 | 半導体基板及び半導体素子 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9859114B2 (en) * | 2012-02-08 | 2018-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Oxide semiconductor device with an oxygen-controlling insulating layer |
CN105576018A (zh) * | 2014-10-16 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
WO2018063207A1 (en) * | 2016-09-29 | 2018-04-05 | Intel Corporation | Resistive random access memory cell |
US10263013B2 (en) | 2017-02-24 | 2019-04-16 | Globalfoundries Inc. | Method of forming an integrated circuit (IC) with hallow trench isolation (STI) regions and the resulting IC structure |
US10163679B1 (en) | 2017-05-31 | 2018-12-25 | Globalfoundries Inc. | Shallow trench isolation formation without planarization |
US10319827B2 (en) * | 2017-07-12 | 2019-06-11 | Globalfoundries Inc. | High voltage transistor using buried insulating layer as gate dielectric |
KR20200143562A (ko) * | 2019-06-13 | 2020-12-24 | 삼성디스플레이 주식회사 | 박막트랜지스터 기판 및 이를 구비한 디스플레이 장치 |
CN118231414A (zh) * | 2024-05-24 | 2024-06-21 | 杭州积海半导体有限公司 | Pdsoi晶体管及其制造方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07183234A (ja) * | 1993-12-24 | 1995-07-21 | Semiconductor Energy Lab Co Ltd | 多目的基板処理装置およびその動作方法および薄膜集積回路の作製方法 |
JPH0818009A (ja) * | 1994-07-04 | 1996-01-19 | Nippondenso Co Ltd | 半導体装置 |
JP2000223713A (ja) * | 1999-02-02 | 2000-08-11 | Oki Electric Ind Co Ltd | 半導体素子及びその製造方法 |
JP2003152192A (ja) * | 2001-11-19 | 2003-05-23 | Sony Corp | 電界効果半導体装置及びその駆動方法 |
JP2003282878A (ja) * | 2002-03-20 | 2003-10-03 | Citizen Watch Co Ltd | 半導体装置およびその製造方法 |
JP2005244112A (ja) * | 2004-02-27 | 2005-09-08 | Oki Electric Ind Co Ltd | 半導体装置、及び半導体装置の製造方法 |
JP2007311747A (ja) * | 2006-04-18 | 2007-11-29 | Sharp Corp | 半導体装置の製造方法、半導体装置及び表示装置 |
JP2009135469A (ja) * | 2007-11-01 | 2009-06-18 | Semiconductor Energy Lab Co Ltd | 半導体基板の作製方法および半導体装置の作製方法 |
WO2010082498A1 (ja) * | 2009-01-19 | 2010-07-22 | 株式会社日立製作所 | 半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06140427A (ja) | 1992-10-26 | 1994-05-20 | Sony Corp | Soi構造を持つトランジスタおよびその製造方法 |
KR100291971B1 (ko) | 1993-10-26 | 2001-10-24 | 야마자끼 순페이 | 기판처리장치및방법과박막반도체디바이스제조방법 |
JP2002076336A (ja) * | 2000-09-01 | 2002-03-15 | Mitsubishi Electric Corp | 半導体装置およびsoi基板 |
JP2002124665A (ja) * | 2000-10-12 | 2002-04-26 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2003289144A (ja) | 2002-03-28 | 2003-10-10 | Toshiba Corp | 半導体装置およびその製造方法 |
-
2011
- 2011-02-02 JP JP2011020521A patent/JP6076584B2/ja active Active
-
2012
- 2012-01-31 US US13/362,093 patent/US9136386B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07183234A (ja) * | 1993-12-24 | 1995-07-21 | Semiconductor Energy Lab Co Ltd | 多目的基板処理装置およびその動作方法および薄膜集積回路の作製方法 |
JPH0818009A (ja) * | 1994-07-04 | 1996-01-19 | Nippondenso Co Ltd | 半導体装置 |
JP2000223713A (ja) * | 1999-02-02 | 2000-08-11 | Oki Electric Ind Co Ltd | 半導体素子及びその製造方法 |
JP2003152192A (ja) * | 2001-11-19 | 2003-05-23 | Sony Corp | 電界効果半導体装置及びその駆動方法 |
JP2003282878A (ja) * | 2002-03-20 | 2003-10-03 | Citizen Watch Co Ltd | 半導体装置およびその製造方法 |
JP2005244112A (ja) * | 2004-02-27 | 2005-09-08 | Oki Electric Ind Co Ltd | 半導体装置、及び半導体装置の製造方法 |
JP2007311747A (ja) * | 2006-04-18 | 2007-11-29 | Sharp Corp | 半導体装置の製造方法、半導体装置及び表示装置 |
JP2009135469A (ja) * | 2007-11-01 | 2009-06-18 | Semiconductor Energy Lab Co Ltd | 半導体基板の作製方法および半導体装置の作製方法 |
WO2010082498A1 (ja) * | 2009-01-19 | 2010-07-22 | 株式会社日立製作所 | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014041822A1 (ja) * | 2012-09-14 | 2014-03-20 | 独立行政法人産業技術総合研究所 | 半導体基板及び半導体素子 |
Also Published As
Publication number | Publication date |
---|---|
JP6076584B2 (ja) | 2017-02-08 |
US9136386B2 (en) | 2015-09-15 |
US20120193714A1 (en) | 2012-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6076584B2 (ja) | 半導体装置及びその製造方法 | |
TWI527242B (zh) | 半導體裝置與其製造方法 | |
JP4814304B2 (ja) | 集積回路およびその製造方法 | |
JP5434360B2 (ja) | 半導体装置及びその製造方法 | |
US9385231B2 (en) | Device structure with increased contact area and reduced gate capacitance | |
US8790991B2 (en) | Method and structure for shallow trench isolation to mitigate active shorts | |
CN111223816A (zh) | 半导体装置的形成方法 | |
JP2008536335A (ja) | 適応ウェル・バイアシング、並びにパワー及び性能強化のためのハイブリッド結晶配向cmos構造体 | |
JP5163311B2 (ja) | 半導体装置及びその製造方法 | |
WO2006006438A1 (ja) | 半導体装置及びその製造方法 | |
JP2010192588A (ja) | 半導体装置およびその製造方法 | |
TWI690025B (zh) | 絕緣體上半導體基底、其形成方法以及積體電路 | |
US20230052380A1 (en) | Semiconductor Device With Funnel Shape Spacer And Methods Of Forming The Same | |
US20160276371A1 (en) | Method for the formation of a finfet device having a partially dielectric isolated fin structure | |
JP2009004425A (ja) | 半導体装置及び半導体装置の製造方法 | |
US7829400B2 (en) | Semiconductor device fabrication method and semiconductor device | |
TW200826230A (en) | Semiconductor device and method for manufacturing the same | |
JP2005340782A (ja) | 半導体装置およびその製造方法 | |
US8134208B2 (en) | Semiconductor device having decreased contact resistance | |
TWI511187B (zh) | 製作具有本地接點之半導體裝置之方法 | |
JP5719381B2 (ja) | 低寄生容量ボディ・コンタクト・トランジスタ | |
JP2008112900A (ja) | 半導体装置およびその製造方法 | |
JP2005064194A (ja) | Soi構造を有する半導体基板及びその製造方法及び半導体装置 | |
TW202234726A (zh) | 半導體裝置及用於製造奈米片中之電容器之方法 | |
JP4942951B2 (ja) | Mos型トランジスタの製造方法及びmos型トランジスタ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140131 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20141217 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150106 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150220 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20150331 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150630 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20150707 |
|
A912 | Removal of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20150731 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160706 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161021 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170111 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6076584 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |