JP2012129251A5 - - Google Patents
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- JP2012129251A5 JP2012129251A5 JP2010277318A JP2010277318A JP2012129251A5 JP 2012129251 A5 JP2012129251 A5 JP 2012129251A5 JP 2010277318 A JP2010277318 A JP 2010277318A JP 2010277318 A JP2010277318 A JP 2010277318A JP 2012129251 A5 JP2012129251 A5 JP 2012129251A5
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- wiring board
- conductive film
- wall
- electrode
- manufacturing
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Description
基板に形成された複数の微細孔の内壁に、表面電極と裏面電極とを電気的に接続する導電膜を形成して配線基板を製造する配線基板の製造方法において、インクジェットヘッドから金属微粒子を含有するインクの液滴を吐出させ、前記微細孔の内壁に着弾させる工程と、前記着弾させた液滴により、前記内壁の一部の領域にのみ、前記導電膜を形成する工程と、を有することを特徴とする。 In a wiring board manufacturing method for manufacturing a wiring board by forming a conductive film that electrically connects a front electrode and a back electrode on the inner walls of a plurality of micro holes formed in the board, the metallic fine particles are contained from the inkjet head. ejecting ink droplet of the steps to land on an inner wall of the micropores, by said landed droplets, only a partial region of the inner wall, having the steps of forming the conductive film It is characterized by.
基板に形成された複数の微細孔の内壁に表面電極と裏面電極とを電気的に接続する導電膜が形成された配線基板において、前記導電膜は、前記微細孔の内壁の一部の領域にのみ形成され、前記導電膜は、膜厚が0.1μm以上であり、前記微細孔の円周方向に沿って、前記表面電極と前記裏面電極の間での最小幅が10μm以上であることを特徴とする。
また、基板に形成された複数の微細孔の内壁に表面電極と裏面電極とを電気的に接続する導電膜が形成された配線基板において、前記微細孔には溝が形成され、前記溝に形成された前記導電膜によって前記表面電極と前記裏面電極とが電気的に接続されていることを特徴とする。
In the wiring board in which the conductive film is formed to electrically connect the surface electrode and the back electrode on the inner wall of a plurality of fine holes formed in the substrate, the conductive film is in a partial region of the inner wall of the micropores only formed, said conductive film has a film thickness is not less 0.1μm or more, along the circumferential direction of the micropores, the minimum width between the surface electrode and the back electrode is 10μm or more Features.
Further, in the wiring substrate in which a conductive film for electrically connecting the front surface electrode and the back surface electrode is formed on the inner walls of the plurality of micro holes formed in the substrate, the micro holes are formed with grooves and formed in the grooves. The surface electrode and the back electrode are electrically connected by the conductive film .
Claims (9)
インクジェットヘッドから金属微粒子を含有するインクの液滴を吐出させ、前記微細孔の内壁に着弾させる工程と、
前記着弾させた液滴により、前記内壁の一部の領域にのみ、前記導電膜を形成する工程と、
を有することを特徴とする配線基板の製造方法。 In the method of manufacturing a wiring board, a conductive film that electrically connects the front surface electrode and the back surface electrode is formed on the inner wall of the plurality of fine holes formed in the substrate, and the wiring board is manufactured.
A step of the ink jet head to eject droplets of ink containing metal particles, to land on an inner wall of the micropore,
The droplets were the landing, only a partial region of the inner wall, and forming the conductive film,
A method of manufacturing a wiring board, comprising:
前記導電膜は、前記微細孔の内壁の一部の領域にのみ形成され、
前記導電膜は、膜厚が0.1μm以上であり、前記微細孔の円周方向に沿って、前記表面電極と前記裏面電極の間での最小幅が10μm以上であることを特徴とする配線基板。 In a wiring board in which a conductive film that electrically connects a front electrode and a back electrode is formed on the inner walls of a plurality of fine holes formed in the substrate ,
The conductive film is formed only in a partial region of the inner wall of the fine hole ,
The conductive film thickness is not less 0.1μm or more, along the circumferential direction of the micropores, wiring minimum width between the surface electrode and the rear electrode is equal to or is 10μm or more substrate.
前記微細孔には溝が形成され、前記溝に形成された前記導電膜によって前記表面電極と前記裏面電極とが電気的に接続されていることを特徴とする配線基板。A wiring board, wherein a groove is formed in the fine hole, and the front electrode and the back electrode are electrically connected by the conductive film formed in the groove.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010277318A JP5773633B2 (en) | 2010-12-13 | 2010-12-13 | Wiring board manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010277318A JP5773633B2 (en) | 2010-12-13 | 2010-12-13 | Wiring board manufacturing method |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012129251A JP2012129251A (en) | 2012-07-05 |
JP2012129251A5 true JP2012129251A5 (en) | 2014-02-06 |
JP5773633B2 JP5773633B2 (en) | 2015-09-02 |
Family
ID=46646007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010277318A Expired - Fee Related JP5773633B2 (en) | 2010-12-13 | 2010-12-13 | Wiring board manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5773633B2 (en) |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5145785B1 (en) * | 1967-09-16 | 1976-12-06 | ||
FR2522459A1 (en) * | 1982-02-26 | 1983-09-02 | Serras Paulet Edouard | PRINTED ELECTRICAL CIRCUIT |
JPH0379480U (en) * | 1989-12-05 | 1991-08-13 | ||
JPH05303915A (en) * | 1992-04-28 | 1993-11-16 | Fujitsu Ltd | Method of forming conductive high molecular fine wire |
JPH06283835A (en) * | 1993-03-26 | 1994-10-07 | Taiyo Yuden Co Ltd | Circuit board and production thereof |
JPH07231154A (en) * | 1994-02-21 | 1995-08-29 | Matsushita Electric Works Ltd | Method of forming three-dimensional circuit |
JPH09130015A (en) * | 1995-10-26 | 1997-05-16 | Toyama Print Kogyo Kk | Fabrication of printed circuit board |
JPH1075022A (en) * | 1996-08-31 | 1998-03-17 | Taiyo Yuden Co Ltd | Circuit board |
JP2000068650A (en) * | 1998-08-24 | 2000-03-03 | Ibiden Co Ltd | Multi-layered printed wiring board |
JP4127433B2 (en) * | 1998-09-17 | 2008-07-30 | イビデン株式会社 | Multilayer buildup wiring board and method for manufacturing multilayer buildup wiring board |
JP2000357873A (en) * | 1999-06-17 | 2000-12-26 | Hitachi Ltd | Multilayer wiring board and manufacture thereof |
JP2003318542A (en) * | 2002-04-22 | 2003-11-07 | Seiko Epson Corp | Method for forming multilayer wiring, multilayer wiring board, device, method for manufacturing the same, and electronic device |
JP2006173212A (en) * | 2004-12-13 | 2006-06-29 | Canon Inc | Device and method for forming pattern |
JPWO2006100790A1 (en) * | 2005-03-22 | 2008-08-28 | クラスターテクノロジー株式会社 | Wiring board manufacturing method and wiring board |
JP2006332615A (en) * | 2005-04-25 | 2006-12-07 | Brother Ind Ltd | Method for forming pattern |
JP2008294244A (en) * | 2007-05-25 | 2008-12-04 | Ricoh Co Ltd | Wiring pattern connecting method, wiring sheet, and wiring sheet laminate |
JP5455538B2 (en) * | 2008-10-21 | 2014-03-26 | キヤノン株式会社 | Semiconductor device and manufacturing method thereof |
-
2010
- 2010-12-13 JP JP2010277318A patent/JP5773633B2/en not_active Expired - Fee Related
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