JP2012084840A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2012084840A JP2012084840A JP2011100473A JP2011100473A JP2012084840A JP 2012084840 A JP2012084840 A JP 2012084840A JP 2011100473 A JP2011100473 A JP 2011100473A JP 2011100473 A JP2011100473 A JP 2011100473A JP 2012084840 A JP2012084840 A JP 2012084840A
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- semiconductor chip
- bonding
- insulating film
- wiring board
- semiconductor device
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Abstract
【解決手段】共通化基板(配線基板2)において複数のボンディングリード2cそれぞれを基板中心に向けて延在させるとともに、最小チップに対応したダイボンド領域であるソルダレジスト膜2gにダイボンド材6を塗布することで、大チップである第1半導体チップ1を搭載した際にもボンディングリード2cにダイボンド材6がかぶさることなくワイヤボンディングを行うことができ、これにより、開発コストを低減して半導体装置(LGA7)のコストの低減化を図る。
【選択図】図4
Description
図1は本発明の実施の形態1の半導体装置(大チップ搭載)の構造の一例を封止体を透過し、かつワイヤを取り除いて示す平面図、図2は図1のA部においてソルダレジスト膜を取り除き、かつワイヤ及び下面のランドを付加した構造の一例を示す部分拡大平面図、図3は図1のB−B線に沿って切断した構造の一例を示す断面図、図4は図3のA部の構造の一例を拡大して示す部分拡大断面図である。
図12は本発明の実施の形態2の半導体装置(大チップ搭載)の構造の一例を封止体を透過し、かつワイヤを取り除いて示す平面図、図13は図12のA部においてソルダレジスト膜を取り除き、かつワイヤ及び下面のランドを付加した構造の一例を示す部分拡大平面図、図14は図12のB−B線に沿って切断した構造の一例を示す断面図、図15は図14のA部の構造の一例を拡大して示す部分拡大断面図である。さらに、図16は本発明の実施の形態2の半導体装置(小チップ搭載)の構造の一例を封止体を透過し、かつワイヤを取り除いて示す平面図、図17は図16のA部においてソルダレジスト膜を取り除き、かつワイヤ及び下面のランドを付加した構造の一例を示す部分拡大平面図、図18は図16のB−B線に沿って切断した構造の一例を示す断面図、図19は図18のA部の構造の一例を拡大して示す部分拡大断面図である。
図21は本発明の実施の形態3の半導体装置(大チップ搭載)の構造の一例を封止体を透過し、かつワイヤを取り除いて示す平面図、図22は図21のA−A線に沿って切断した構造の一例を示す部分断面図、図23は図21の半導体装置の組み立て手順の一例を示す製造フロー図である。また、図24は図23の組み立てで用いる配線基板の構造の一例を示す平面図、図25は図23の組み立てにおけるダイボンド材塗布後の構造の一例を示す平面図、図26は図23の組み立てにおけるダイボンディング後の構造の一例を示す平面図、図27は図23の組み立てのダイボンディング工程の一例を示す斜視図である。
図34は本発明の実施の形態4の半導体装置(大チップ搭載)の構造の一例を封止体を透過し、かつワイヤを取り除いて示す平面図、図35は図34のA−A線に沿って切断した構造の一例を示す部分断面図である。さらに、図36は図34の半導体装置の組み立て手順の一例を示す製造フロー図、図37は図36の組み立てで用いる配線基板の構造の一例を示す平面図、図38は図36の組み立てにおけるダイボンド材供給後の構造の一例を示す平面図、図39は図36の組み立てにおけるダイボンディング後の構造の一例を示す平面図である。
1a 主面(表面)
1b 裏面
1c 電極パッド
2 配線基板
2a 上面
2b 下面
2c ボンディングリード
2d ニッケル−金めっき
2e ビア
2f 配線部
2g ソルダレジスト膜(絶縁膜、第1絶縁膜)
2h コア材
2i ランド(外部端子)
2j ボンディングリード
2k ソルダレジスト膜(絶縁膜、第1絶縁膜)
2n 多数個取り基板(配線基板)
2p デバイス領域
2q ソルダレジスト膜(第1絶縁膜)
2r ソルダレジスト膜(第2絶縁膜)
2s 溝部
2t 段差部
3 第2半導体チップ
3a 主面
3b 裏面
3c 電極パッド
4 封止体
5 ワイヤ(金属ワイヤ)
6 ダイボンド材(接着材、ペースト材)
6a 端部
7 LGA(半導体装置)
8 LGA(半導体装置)
9 LGA(半導体装置)
10 LGA(半導体装置)
11 BGA(半導体装置)
12 半田ボール(外部端子)
13 LGA(半導体装置)
14 シリンジ
15 多点ノズル
16 LGA(半導体装置)
17 接続点
18 LGA(半導体装置)
19 ダイボンド材
20 LGA(半導体装置)
21 半導体パッケージ
22 ダイボンド材
23 ウエハ
24 ウエハリング
25 ダイシングシート
30 LGA
Claims (25)
- 上面、前記上面のダイボンド材を塗布する領域に形成された絶縁膜及び前記絶縁膜の周囲に配置された複数のボンディングリード、前記上面とは反対側の下面、及び前記下面に形成された複数のランドを有する配線基板と、
主面及び前記主面に形成された複数の電極パッドを有し、前記配線基板の前記絶縁膜上に搭載された半導体チップと、
前記配線基板の前記絶縁膜と前記半導体チップとの間に配置された前記ダイボンド材と、
前記配線基板の前記複数のボンディングリードと前記半導体チップの前記複数の電極パッドとをそれぞれ電気的に接続する複数の金属ワイヤとを有し、
前記配線基板は、異なった平面サイズの前記半導体チップを搭載可能であり、前記配線基板の前記絶縁膜のパターンの大きさが前記半導体チップの平面サイズより小さいことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記配線基板には前記複数のボンディングリードそれぞれと繋がる複数のビアが形成されており、前記上面において前記複数のビアの内側と外側の両側の方向に前記ボンディングリードが延在していることを特徴とする半導体装置。
- 請求項2記載の半導体装置において、前記ダイボンド材は、前記半導体チップの外周より内側に配置されていることを特徴とする半導体装置。
- 請求項3記載の半導体装置において、前記半導体チップの裏面側の周縁部に封止体の一部が配置されていることを特徴とする半導体装置。
- 請求項4記載の半導体装置において、前記絶縁膜のパターンの外周部は、前記半導体チップの外周より内側の位置で終端していることを特徴とする半導体装置。
- 請求項5記載の半導体装置において、前記ボンディングリードの内側寄りの端部が前記半導体チップの下部に位置しており、平面視において前記ボンディングリードの前記内側寄りの端部が前記半導体チップと重なっていることを特徴とする半導体装置。
- 請求項6記載の半導体装置において、前記ダイボンド材はペースト状の接着材が塗布されて形成されたものであることを特徴とする半導体装置。
- 上面、前記上面のダイボンド材を塗布する領域に形成された絶縁膜及び前記絶縁膜の周囲に配置された複数のボンディングリード、前記上面とは反対側の下面、及び前記下面に形成された複数のランドを有する配線基板と、
主面及び前記主面に形成された複数の電極パッドを有し、前記配線基板の前記絶縁膜上に搭載された半導体チップと、
前記配線基板の前記絶縁膜と前記半導体チップとの間に配置された前記ダイボンド材と、
前記配線基板の前記複数のボンディングリードと前記半導体チップの前記複数の電極パッドとをそれぞれ電気的に接続する複数の金属ワイヤとを有し、
前記配線基板は、異なった平面サイズの前記半導体チップを搭載可能であり、前記配線基板の前記絶縁膜のパターンの大きさが前記半導体チップの平面サイズより小さく、
前記ボンディングリードの内側寄りの端部が前記半導体チップの下部に位置しており、平面視において前記ボンディングリードの前記内側寄りの端部が前記半導体チップと重なっていることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、前記配線基板には前記複数のボンディングリードそれぞれと繋がる複数のビアが形成されており、前記上面において前記複数のビアの内側と外側の両側の方向に前記ボンディングリードが延在していることを特徴とする半導体装置。
- 請求項9記載の半導体装置において、前記ダイボンド材は、前記半導体チップの外周より内側に配置されていることを特徴とする半導体装置。
- 請求項10記載の半導体装置において、前記半導体チップの裏面側の周縁部に封止体の一部が配置されていることを特徴とする半導体装置。
- 請求項11記載の半導体装置において、前記ダイボンド材はペースト状の接着材が塗布されて成されたものであることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記半導体チップが搭載された前記絶縁膜の膜厚は、前記半導体チップが搭載されていない絶縁膜の膜厚よりも厚いことを特徴とする半導体装置。
- 請求項13記載の半導体装置において、前記半導体チップが搭載された前記絶縁膜と前記複数のボンディングリードとの間に前記ダイボンド材の端部が位置することを特徴とする半導体装置。
- 上面、前記上面のダイボンド材を塗布する領域に形成された第1絶縁膜、前記第1絶縁膜の周囲に形成された第2絶縁膜、前記第1絶縁膜の周囲に配置された複数のボンディングリード、前記上面とは反対側の下面、及び前記下面に形成された複数のランドを有する配線基板と、
主面及び前記主面に形成された複数の電極パッドを有し、前記配線基板の前記第1絶縁膜上に搭載された半導体チップと、
前記配線基板の前記第1絶縁膜と前記半導体チップとの間に配置された前記ダイボンド材と、
前記配線基板の前記複数のボンディングリードと前記半導体チップの前記複数の電極パッドとをそれぞれ電気的に接続する複数の金属ワイヤとを有し、
前記配線基板の前記第1絶縁膜の面積は、前記半導体チップの面積よりも小さく、
前記配線基板の前記第1絶縁膜の膜厚は、前記第2絶縁膜の膜厚よりも厚いことを特徴とする半導体装置。 - 請求項15記載の半導体装置において、前記第2絶縁膜は前記第1絶縁膜と前記複数のボンディングリードとの間に形成され、かつ前記第1絶縁膜から離れて配置されており、前記ダイボンド材の端部の一部は、前記第1絶縁膜と前記第2絶縁膜との間に位置することを特徴とする半導体装置。
- 請求項16記載の半導体装置において、前記ダイボンド材は、ペースト状の接着材であることを特徴とする半導体装置。
- 請求項15記載の半導体装置において、前記ダイボンド材の前記配線基板との接着面積は、前記第1絶縁膜の面積よりも大きいことを特徴とする半導体装置。
- 請求項18記載の半導体装置において、前記ダイボンド材の端部は、前記第1絶縁膜と、前記金属ワイヤと前記ボンディングリードとが接続している接続点との間に位置することを特徴とする半導体装置。
- 請求項18記載の半導体装置において、前記ダイボンド材はフィルム状の接着材であることを特徴とする半導体装置。
- 請求項20記載の半導体装置において、前記複数のボンディングリードの上面の一部は前記ダイボンド材で覆われていることを特徴とする半導体装置。
- (a)半導体チップを準備する工程と、
(b)配線基板上に接着材を供給する工程と、
(c)前記接着材を介して前記半導体チップを配線基板上に搭載する工程と、
(d)前記半導体チップの表面の電極パッドと前記配線基板の上面のボンディングリードとを金属ワイヤにより電気的に接続する工程と、
(e)前記半導体チップおよび前記金属ワイヤを封止体により封止する工程と、を有し、
前記配線基板の上面には、その面積が前記半導体チップの面積よりも小さく、前記半導体チップが搭載される第1絶縁膜を有し、
前記ボンディングリードは、前記第1絶縁膜の周囲に配置されており、
前記(b)工程において、前記接着材は前記配線基板の前記第1絶縁膜上に供給され、
前記(c)工程は、前記半導体チップと前記配線基板の前記第1絶縁膜との間が前記接着材で充たされるように行うことを特徴とする半導体装置の製造方法。 - 請求項22記載の半導体装置の製造方法において、前記接着材はペースト状の接着材であって、前記(c)工程は、前記接着材の端部が前記第1絶縁膜と前記ボンディングリードとの間に位置するように行うことを特徴とする半導体装置の製造方法。
- 請求項22記載の半導体装置の製造方法であって、前記接着材はフィルム状の接着材であることを特徴とする半導体装置の製造方法。
- (a)半導体ウエハを準備する工程と、
(b)前記半導体ウエハの裏面にフィルム状の接着材を貼り付ける工程と、
(c)前記半導体ウエハをダイシングして、その裏面に前記フィルム状の接着材が貼り付けられた状態の半導体チップを取得する工程と、
(d)前記半導体チップを配線基板上に搭載する工程と、
(e)前記半導体チップの表面の電極パッドと前記配線基板の上面のボンディングリードとを金属ワイヤにより電気的に接続する工程と、
(f)前記半導体チップおよび前記金属ワイヤを封止体により封止する工程と、を有し、
前記配線基板の上面には、その面積が前記半導体チップの面積よりも小さく、前記半導体チップが搭載される第1絶縁膜を有し、
前記ボンディングリードは、前記第1絶縁膜の周囲に配置されており、
前記(d)工程は、前記第1絶縁膜と前記ボンディングリードの上面の一部が前記フィルム状の接着材で覆われるように前記半導体チップを前記配線基板上に搭載することを特徴とする半導体装置の製造方法。
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