JP2012054850A - Isolator - Google Patents

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JP2012054850A
JP2012054850A JP2010197355A JP2010197355A JP2012054850A JP 2012054850 A JP2012054850 A JP 2012054850A JP 2010197355 A JP2010197355 A JP 2010197355A JP 2010197355 A JP2010197355 A JP 2010197355A JP 2012054850 A JP2012054850 A JP 2012054850A
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opening
ferrite
isolator
line
main line
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Takashi Hasegawa
長谷川　　隆
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide an isolator capable of achieving a reduction in height and cost with a simple structure.SOLUTION: The isolator includes: a ferrite 10; a connection conductor 15 that is provided on the ferrite 10 and includes openings P1, P2 and P3; a permanent magnet that applies a direct-current field to the ferrite 10; a resistance R that is provided between the first opening P1 and the second opening P2. A main line arranged between the first opening P1 and the second opening P2 does not resonate and an end of a sub-line branched from the main line is defined as the third opening P3. The deflected wave from the sub-line is adjusted to be deviated by a 90-degree phase at the intersection with the connection conductor 15. When a high-frequency signal is input from the first opening P1, a phase difference between the first opening P1 and the second opening P2 is kept small and the high-frequency signal is directly transmitted to the second opening P2 while a current scarcely flows through the resistance R. When a high-frequency signal is input from the second opening P2, the phase difference becomes larger and, a current flows through the resistance R, and the high-frequency signal is absorbed.

Description

本発明は、アイソレータ、特に、マイクロ波帯などで使用されるアイソレータに関する。   The present invention relates to an isolator, and more particularly to an isolator used in a microwave band or the like.

一般に、アイソレータは信号を特定方向にのみ伝送し、逆方向には伝送しない特性を有し、携帯電話などの移動体通信機器の送信回路部に搭載されている。この種の２端子型アイソレータとして基本的な構成が特許文献１に記載されている。フェライト上に第１中心電極及び第２中心電極を所定の角度で交差させ、かつ、互いに絶縁状態で配置し、フェライトに永久磁石から直流磁界を印加するようにしたものである。   In general, an isolator has a characteristic of transmitting a signal only in a specific direction and not in a reverse direction, and is mounted on a transmission circuit unit of a mobile communication device such as a mobile phone. A basic configuration of this type of two-terminal isolator is described in Patent Document 1. The first center electrode and the second center electrode intersect each other at a predetermined angle on the ferrite and are arranged in an insulated state so that a DC magnetic field is applied to the ferrite from a permanent magnet.

しかしながら、前記２端子型アイソレータにあっては、フェライト上に中心電極を絶縁層を介して２層に配置するため（計３層）、重層構造となって複雑であり、製造コストが上昇し、かつ、低背化が困難であるという問題点を有している。   However, in the two-terminal type isolator, since the center electrode is arranged in two layers on the ferrite via the insulating layer (total of three layers), it is complicated with a multi-layer structure, and the manufacturing cost increases. In addition, there is a problem that it is difficult to reduce the height.

特開昭５８−３４０２号公報JP 58-3402 A

そこで、本発明の目的は、簡単な構造からなり、低背化、低コスト化を達成できる２端子型のアイソレータを提供することにある。   Accordingly, an object of the present invention is to provide a two-terminal isolator having a simple structure and capable of achieving a reduction in height and cost.

本発明の一形態であるアイソレータは、
フェライトと、
前記フェライトに配置された、第１開口、第２開口及び第３開口を有する接合導体と、
前記フェライトに直流磁界を印加する永久磁石と、
を備え、
前記接合導体は、第１開口と第２開口との間に配置された主線路と、該主線路から分岐して第３開口に至る副線路とからなり、
抵抗素子が第１開口と第２開口との間に前記主線路に対して並列に接続され、
第３開口はグランドに接続されていること、
を特徴とする。 An isolator according to one aspect of the present invention is
With ferrite,
A bonding conductor disposed in the ferrite and having a first opening, a second opening, and a third opening;
A permanent magnet for applying a DC magnetic field to the ferrite;
With
The junction conductor is composed of a main line disposed between the first opening and the second opening, and a sub line branched from the main line to reach the third opening,
A resistance element is connected in parallel to the main line between the first opening and the second opening,
The third opening is connected to ground,
It is characterized by.

前記アイソレータにおいて、フェライトの内部には、第１開口又は第２開口からの入力波と第３開口からの反射波で合成された波が形成される。反射波が導体のインダクタンス値やフェライトの動作磁界などにより、入射波に対して９０°の位相差を付けられることにより、フェライトの内部に正及び負の円偏波が形成される。正の円偏波が生じるとフェライトの磁気共鳴点付近では大きな透磁率となり、通過位相が大きくなって第１及び第２開口間で電位差が生じ、並列に接続されている抵抗に電流が流れ、高周波信号が吸収される。負の円偏波が生じると透磁率は略１に等しく、第１及び第２開口間の位相差が小さく抑えられ、抵抗にはほとんど電流が流れず、高周波信号はそのまま通過する。また、接合導体は、主線路と該主線路から分岐した副線路から構成され、主線路及び副線路の一部をフェライト上に１層で形成するだけで済み、接合導体を簡略化できる。   In the isolator, a wave synthesized by an input wave from the first opening or the second opening and a reflected wave from the third opening is formed inside the ferrite. When the reflected wave has a 90 ° phase difference with respect to the incident wave due to the inductance value of the conductor or the operating magnetic field of the ferrite, positive and negative circularly polarized waves are formed inside the ferrite. When positive circular polarization occurs, the magnetic permeability near the magnetic resonance point of the ferrite becomes large, the passing phase becomes large, a potential difference occurs between the first and second openings, and a current flows through the resistors connected in parallel. High frequency signals are absorbed. When negative circular polarization occurs, the magnetic permeability is substantially equal to 1, the phase difference between the first and second openings is kept small, almost no current flows through the resistor, and the high-frequency signal passes as it is. Further, the junction conductor is composed of a main line and a sub-line branched from the main line, and it is only necessary to form a part of the main line and the sub-line on the ferrite in one layer, and the junction conductor can be simplified.

本発明によれば、主線路及び副線路の一部をフェライト上に１層に形成するだけで済み、複数層にわたって形成する必要がなく、低背化、低コスト化を達成できる。   According to the present invention, it is only necessary to form a part of the main line and the sub line on the ferrite in one layer, and it is not necessary to form over a plurality of layers, and a reduction in height and cost can be achieved.

第１実施例であるアイソレータを示す斜視図である。It is a perspective view which shows the isolator which is 1st Example. 第１実施例であるアイソレータを示す分解斜視図である。It is a disassembled perspective view which shows the isolator which is 1st Example. 第１実施例であるアイソレータのフェライトを示し、（Ａ）は表面図、（Ｂ）は裏面図である。The ferrite of the isolator which is 1st Example is shown, (A) is a front view, (B) is a back view. 第１実施例であるアイソレータの回路を示し、（Ａ）は接合導体を含む回路図、（Ｂ）は等価回路図である。The circuit of the isolator which is 1st Example is shown, (A) is a circuit diagram containing a junction conductor, (B) is an equivalent circuit diagram. 第１実施例であるアイソレータの特性を示すグラフである。It is a graph which shows the characteristic of the isolator which is 1st Example. 第２実施例であるアイソレータを示す斜視図である。It is a perspective view which shows the isolator which is 2nd Example. 第２実施例であるアイソレータを示す分解斜視図である。It is a disassembled perspective view which shows the isolator which is 2nd Example. 第２実施例であるアイソレータの等価回路図である。It is an equivalent circuit diagram of the isolator which is 2nd Example. 第２実施例であるアイソレータの特性を示すグラフである。It is a graph which shows the characteristic of the isolator which is 2nd Example.

以下、本発明に係る磁気共鳴型アイソレータの実施例について添付図面を参照して説明する。なお、各図において、共通する部品、部分には同じ符号を付し、重複する説明は省略する。また、各図において斜線を付した部分は導電体であることを示している。   Embodiments of a magnetic resonance type isolator according to the present invention will be described below with reference to the accompanying drawings. In addition, in each figure, the same code | symbol is attached | subjected to a common component and part, and the overlapping description is abbreviate | omitted. In each figure, the hatched portion indicates a conductor.

（第１実施例、図１〜図５参照）
第１実施例であるアイソレータ１Ａは、図１及び図２に示すように、フェライト１０と、フェライト１０の第１主面１１に配置された逆Ｔ字形状をなす三つの開口Ｐ１，Ｐ２，Ｐ３を有する接合導体１５と、フェライト１０に直流磁界を印加する永久磁石２０と、抵抗Ｒと、入出力のインピーダンス整合素子として機能するコンデンサＣ１，Ｃ２と、実装用基板３０と、を備えている。 (Refer 1st Example and FIGS. 1-5)
As shown in FIGS. 1 and 2, the isolator 1 </ b> A according to the first embodiment includes a ferrite 10 and three openings P <b> 1, P <b> 2, P <b> 3 having an inverted T shape disposed on the first main surface 11 of the ferrite 10. , A permanent magnet 20 that applies a DC magnetic field to the ferrite 10, a resistor R, capacitors C1 and C2 that function as input / output impedance matching elements, and a mounting substrate 30.

接合導体１５は、導電性金属による蒸着などで形成された薄膜あるいは導電性ペーストの塗布・焼付けにて形成された厚膜である。図３に示すように、接合導体の三つの開口Ｐ１，Ｐ２，Ｐ３のうち、直線状に対向する第１開口Ｐ１と第２開口Ｐ２との間に配置された主線路は１／４波長以下の共振しない線路長とされている。第１主面１１上で接合導体１５の主線路から分岐した副線路は、第２主面１２に主線路と直交する方向に延在されて対向導体１７とされ、対向導体１７の端部が第３開口Ｐ３とされている。ここで、主線路とは第１及び第２開口Ｐ１，Ｐ２間の導体を意味し、副線路とは主線路の中央部分から分岐して第３開口Ｐ３へ至る導体を意味する。   The bonding conductor 15 is a thin film formed by vapor deposition using a conductive metal or a thick film formed by applying and baking a conductive paste. As shown in FIG. 3, the main line arranged between the first opening P1 and the second opening P2 that are linearly opposed to each other among the three openings P1, P2, and P3 of the junction conductor is ¼ wavelength or less. The line length is not resonant. The sub-line branched from the main line of the junction conductor 15 on the first main surface 11 is extended to the second main surface 12 in a direction orthogonal to the main line to be a counter conductor 17, and the end of the counter conductor 17 is The third opening P3. Here, the main line means a conductor between the first and second openings P1 and P2, and the sub-line means a conductor branched from the central portion of the main line and reaching the third opening P3.

実装用基板３０には、入力端子電極３１、出力端子電極３２、グランド端子電極３３がそれぞれ形成されている。フェライト１０と永久磁石２０は同じ面積であり、フェライト１０は第１主面１１上に永久磁石２０が貼着された状態で実装用基板３０上に搭載される。このとき、主線路の一端（第１開口Ｐ１）は入力端子電極３１に接続され、他端（第２開口Ｐ２）は出力端子電極３２に接続され、副線路の端部（第３開口Ｐ３）はグランド端子電極３３に接続される。抵抗Ｒは一端が入力端子電極３１に接続され、他端が出力端子電極３２に接続される。即ち、抵抗Ｒは第１開口Ｐ１と第２開口Ｐ２との間に主線路に対して並列に接続される。抵抗Ｒの接続箇所は、入力端子電極３１の端部３１ａ及び出力端子電極３２の端部３２ａである。コンデンサＣ１は一端が入力端子電極３１に接続され、他端がグランド端子電極３３に接続される。コンデンサＣ２は一端が出力端子電極３２に接続され、他端がグランド端子電極３３に接続される。   On the mounting substrate 30, an input terminal electrode 31, an output terminal electrode 32, and a ground terminal electrode 33 are formed. The ferrite 10 and the permanent magnet 20 have the same area, and the ferrite 10 is mounted on the mounting substrate 30 with the permanent magnet 20 attached to the first main surface 11. At this time, one end (first opening P1) of the main line is connected to the input terminal electrode 31, the other end (second opening P2) is connected to the output terminal electrode 32, and the end of the sub line (third opening P3). Is connected to the ground terminal electrode 33. The resistor R has one end connected to the input terminal electrode 31 and the other end connected to the output terminal electrode 32. That is, the resistor R is connected in parallel to the main line between the first opening P1 and the second opening P2. Connection points of the resistor R are an end portion 31 a of the input terminal electrode 31 and an end portion 32 a of the output terminal electrode 32. One end of the capacitor C 1 is connected to the input terminal electrode 31, and the other end is connected to the ground terminal electrode 33. One end of the capacitor C <b> 2 is connected to the output terminal electrode 32, and the other end is connected to the ground terminal electrode 33.

等価回路は図４（Ｂ）に示すとおりであり、主線路はインダクタＬ１，Ｌ２を形成しており、副線路はインダクタＬ３を形成している。以上の構成からなるアイソレータ１Ａにおいて、グランドに接続されている副線路からの反射波が第１開口Ｐ１又は第２開口Ｐ２からの入射波に対して接合導体１５の交点で９０°位相がずれるように調整されている。詳しくは、第１開口Ｐ１からの入射波は、副線路からの反射波によって交点に負の円偏波が生じるので透磁率は略１に等しく、第１及び第２開口Ｐ１，Ｐ２間の位相差が小さく抑えられ、抵抗Ｒにほとんど電流が流れず、入射波は第２開口Ｐ２に伝送される。一方、第２開口Ｐ２からの入射波は、副線路からの反射波によって交点に正の円偏波が生じ、磁気共鳴点近傍で大きな透磁率となり、第１及び第２開口Ｐ１，Ｐ２間の位相差が大きくなるので抵抗Ｒに電流が流れて吸収される。さらに、この入力波はフェライト１０が磁気共鳴することによっても吸収される。   The equivalent circuit is as shown in FIG. 4B. The main line forms inductors L1 and L2, and the sub line forms an inductor L3. In the isolator 1A having the above configuration, the reflected wave from the sub-line connected to the ground is 90 ° out of phase with the incident wave from the first opening P1 or the second opening P2 at the intersection of the junction conductor 15. Has been adjusted. Specifically, the incident wave from the first opening P1 has a negative circularly polarized wave at the intersection point due to the reflected wave from the sub line, so that the magnetic permeability is substantially equal to 1, and the position between the first and second openings P1 and P2. The phase difference is kept small, almost no current flows through the resistor R, and the incident wave is transmitted to the second opening P2. On the other hand, the incident wave from the second opening P2 has a positive circularly polarized wave at the intersection point due to the reflected wave from the sub line, and has a large permeability near the magnetic resonance point, and between the first and second openings P1 and P2. Since the phase difference increases, a current flows through the resistor R and is absorbed. Further, this input wave is also absorbed by the magnetic resonance of the ferrite 10.

第１実施例であるアイソレータ１Ａの入力リターンロスを図５（Ａ）に示し、アイソレーションを図５（Ｂ）に示し、挿入損失を図５（Ｃ）に示し、出力リターンロスを図５（Ｄ）に示す。コンデンサＣ１，Ｃ２の容量はそれぞれ２．５ｐＦ、抵抗Ｒは１５Ωである。入出力端のインピーダンスは１０Ωであり、電気特性は１０Ωで正規化されている。１９２０〜１９８０ＭＨｚで挿入損失が０．９２ｄＢ、アイソレーションが１５．５ｄＢである。   The input return loss of the isolator 1A according to the first embodiment is shown in FIG. 5A, the isolation is shown in FIG. 5B, the insertion loss is shown in FIG. 5C, and the output return loss is shown in FIG. D). Capacitors C1 and C2 each have a capacitance of 2.5 pF and a resistance R of 15Ω. The impedance of the input / output terminals is 10Ω, and the electrical characteristics are normalized by 10Ω. The insertion loss is 0.92 dB and the isolation is 15.5 dB at 1920 to 1980 MHz.

また、主線路が共振することはないので、主線路を１／４波長以下に短くすることができ、第１実施例において、フェライト１０のサイズは縦横が０．６ｍｍ、厚さが０．２ｍｍ、線路幅は０．２ｍｍ、飽和磁化は１００ｍＴである。このように、フェライト１０が従来よりも非常に小さなサイズであること、及び、接合導体１５がフェライト１０の第１主面１１さらに第２主面１２に１層で形成されていることと相俟って、安価、小型、低背で低インピーダンスのアイソレータが得られる。   Further, since the main line does not resonate, the main line can be shortened to ¼ wavelength or less. In the first embodiment, the size of the ferrite 10 is 0.6 mm in length and width and 0.2 mm in thickness. The line width is 0.2 mm and the saturation magnetization is 100 mT. Thus, the fact that the ferrite 10 is much smaller than the conventional size, and that the joining conductor 15 is formed in one layer on the first main surface 11 and the second main surface 12 of the ferrite 10 is combined. Thus, an inexpensive, small, low profile, low impedance isolator can be obtained.

特に、本第１実施例においてはアイソレーションが広帯域である。また、第１及び第２開口Ｐ１，Ｐ２間の主線路と直交する方向に延在する対向導体１７が配置されているため、対向導体１７によって高周波磁界がフェライト１０に閉じ込められて磁束の漏れが小さくなり、挿入損失特性、アイソレーション特性が向上する。なお、対向導体１７は必ずしも必要ではない。   In particular, in the first embodiment, the isolation is broadband. In addition, since the opposing conductor 17 extending in the direction orthogonal to the main line between the first and second openings P1 and P2 is disposed, the high frequency magnetic field is confined in the ferrite 10 by the opposing conductor 17 and magnetic flux leakage occurs. As a result, the insertion loss characteristic and the isolation characteristic are improved. The opposing conductor 17 is not always necessary.

このアイソレータ１Ａは、例えば、移動体通信機器の送信回路モジュールに組み込まれる。実装用基板３０は送信回路モジュールにおけるパワーアンプを搭載するためのプリント配線基板であってもよい。この場合、接合導体１５を備えかつ永久磁石２０を貼着したフェライト１０が送信モジュールの組立て工程に供給されることになる。この点は以下に示す第２実施例でも同様である。   For example, the isolator 1A is incorporated in a transmission circuit module of a mobile communication device. The mounting board 30 may be a printed wiring board for mounting a power amplifier in the transmission circuit module. In this case, the ferrite 10 provided with the joining conductor 15 and having the permanent magnet 20 attached thereto is supplied to the assembling process of the transmission module. This also applies to the second embodiment described below.

（第２実施例、図６〜図９参照）
第２実施例であるアイソレータ１Ｂは、前記第１実施例に対して、コンデンサＣ３を第１開口Ｐ１と第２開口Ｐ２との間に、かつ、主線路及び抵抗Ｒに対して並列に接続したものである。コンデンサＣ３は、図７に示す入力端子電極３１と出力端子電極３２に接続される。他の構成は第１実施例と同様である。ちなみに、コンデンサＣ３の接続箇所は、入力端子電極３１の端部３１ｂ及び出力端子電極３２の端部３２ｂである。 (Refer 2nd Example and FIGS. 6-9)
In the isolator 1B according to the second embodiment, a capacitor C3 is connected between the first opening P1 and the second opening P2 and in parallel with the main line and the resistor R with respect to the first embodiment. Is. Capacitor C3 is connected to input terminal electrode 31 and output terminal electrode 32 shown in FIG. Other configurations are the same as those of the first embodiment. Incidentally, the connection location of the capacitor C3 is the end portion 31b of the input terminal electrode 31 and the end portion 32b of the output terminal electrode 32.

本第２実施例の作用効果は前記第１実施例と基本的に同様である。第２実施例であるアイソレータ１Ｂの入力リターンロスを図９（Ａ）に示し、アイソレーションを図９（Ｂ）に示し、挿入損失を図９（Ｃ）に示し、出力リターンロスを図９（Ｄ）に示す。コンデンサＣ１，Ｃ２の容量はそれぞれ２．８ｐＦ、抵抗Ｒは１５Ω、コンデンサＣ３の容量は１．２ｐＦである。入出力端のインピーダンスは１０Ωであり、電気特性は１０Ωで正規化されている。１９２０〜１９８０ＭＨｚで挿入損失が０．９４ｄＢ、アイソレーションが２０．５ｄＢである。フェライト１０のサイズなどは第１実施例と同様である。特に、本第２実施例では、コンデンサＣ３によって通過位相を微調整することができるのでアイソレーション特性が向上する。   The operational effects of the second embodiment are basically the same as those of the first embodiment. The input return loss of the isolator 1B according to the second embodiment is shown in FIG. 9A, the isolation is shown in FIG. 9B, the insertion loss is shown in FIG. 9C, and the output return loss is shown in FIG. D). Capacitors C1 and C2 each have a capacitance of 2.8 pF, resistor R is 15Ω, and capacitor C3 has a capacitance of 1.2 pF. The impedance of the input / output terminals is 10Ω, and the electrical characteristics are normalized by 10Ω. From 1920 to 1980 MHz, the insertion loss is 0.94 dB, and the isolation is 20.5 dB. The size of the ferrite 10 is the same as that of the first embodiment. In particular, in the second embodiment, since the passing phase can be finely adjusted by the capacitor C3, the isolation characteristic is improved.

（他の実施例）
なお、本発明に係るアイソレータは前記実施例に限定するものではなく、その要旨の範囲内で種々に変更できる。 (Other examples)
The isolator according to the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the gist thereof.

例えば、接合導体は必ずしも逆Ｔ字形状である必要はなく、交点が９０°より若干大きいあるいは小さい角度を有していてもよい。また、実装用基板にあってはその大きさ、形状、構造などは任意である。   For example, the junction conductor does not necessarily have an inverted T shape, and the intersection may have an angle slightly larger or smaller than 90 °. Further, the size, shape, structure, etc. of the mounting substrate are arbitrary.

また、前記実施例では、整合素子として入出力端子とグランド端子との間に容量素子を接続したが、入出力端子と第１開口及び第２開口との間に容量素子を接続してもよい。   In the embodiment, the capacitive element is connected between the input / output terminal and the ground terminal as the matching element. However, the capacitive element may be connected between the input / output terminal and the first opening and the second opening. .

さらに、入力端子と第１開口との間に容量素子を接続し、出力端子とグランド端子との間に容量素子を接続してもよい。この場合には、入力端のインピーダンスを出力端に比べて低くでき、パワーアンプなどのインピーダンス変換回路を一部削減できる。   Furthermore, a capacitive element may be connected between the input terminal and the first opening, and a capacitive element may be connected between the output terminal and the ground terminal. In this case, the impedance at the input end can be made lower than that at the output end, and the impedance conversion circuit such as a power amplifier can be partially reduced.

以上のように、本発明は、アイソレータに有用であり、特に、簡単な構造からなり、低背化、低コスト化を達成できる点で優れている。   As described above, the present invention is useful for an isolator, and is particularly excellent in that it has a simple structure and can achieve a reduction in height and cost.

１Ａ，１Ｂ…アイソレータ
１０…フェライト
１１，１２…主面
１５…接合導体
１７…対向導体
２０…永久磁石
Ｃ１，Ｃ２，Ｃ３…コンデンサ
Ｒ…抵抗
Ｐ１…第１開口
Ｐ２…第２開口
Ｐ３…第３開口 DESCRIPTION OF SYMBOLS 1A, 1B ... Isolator 10 ... Ferrite 11, 12 ... Main surface 15 ... Joint conductor 17 ... Opposing conductor 20 ... Permanent magnet C1, C2, C3 ... Capacitor R ... Resistance P1 ... 1st opening P2 ... 2nd opening P3 ... 3rd Opening

Claims (4)

フェライトと、
前記フェライトに配置された、第１開口、第２開口及び第３開口を有する接合導体と、
前記フェライトに直流磁界を印加する永久磁石と、
を備え、
前記接合導体は、第１開口と第２開口との間に配置された主線路と、該主線路から分岐して第３開口に至る副線路とからなり、
抵抗素子が第１開口と第２開口との間に前記主線路に対して並列に接続され、
第３開口はグランドに接続されていること、
を特徴とするアイソレータ。 With ferrite,
A bonding conductor disposed in the ferrite and having a first opening, a second opening, and a third opening;
A permanent magnet for applying a DC magnetic field to the ferrite;
With
The junction conductor is composed of a main line disposed between the first opening and the second opening, and a sub line branched from the main line to reach the third opening,
A resistance element is connected in parallel to the main line between the first opening and the second opening,
The third opening is connected to ground,
An isolator characterized by. 容量素子が第１開口と第２開口との間に前記主線路及び前記抵抗素子に対して並列に接続されていること、を特徴とする請求項１に記載のアイソレータ。   The isolator according to claim 1, wherein a capacitive element is connected in parallel to the main line and the resistance element between the first opening and the second opening. 第１開口及び第２開口にそれぞれインピーダンス整合素子が接続されていること、を特徴とする請求項１又は請求項２に記載のアイソレータ。   The isolator according to claim 1 or 2, wherein an impedance matching element is connected to each of the first opening and the second opening. 前記フェライトは第１主面及び第２主面を有し、
前記主線路及び前記副線路は第１主面上に形成され、
前記副線路は第２主面側に前記主線路と直交する方向に延在されて対向導体とされ、該対向導体の端部を第３開口としたこと、
を特徴とする請求項１ないし請求項３のいずれかに記載のアイソレータ。 The ferrite has a first main surface and a second main surface;
The main line and the sub line are formed on a first main surface,
The sub-line extends in a direction orthogonal to the main line on the second main surface side to be a counter conductor, and the end of the counter conductor is a third opening;
The isolator according to any one of claims 1 to 3, wherein:
JP2010197355A 2010-09-03 2010-09-03 Isolator Pending JP2012054850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010197355A JP2012054850A (en) 2010-09-03 2010-09-03 Isolator

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JP2010197355A JP2012054850A (en) 2010-09-03 2010-09-03 Isolator

Publications (1)

Publication Number Publication Date
JP2012054850A true JP2012054850A (en) 2012-03-15

Family

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Family Applications (1)

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Country Status (1)

Country Link
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