JP2012015516A - 半導体基板上のボンディングコンタクト - Google Patents
半導体基板上のボンディングコンタクト Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 90
- 239000002184 metal Substances 0.000 claims abstract description 90
- 230000003014 reinforcing effect Effects 0.000 claims description 38
- 239000004020 conductor Substances 0.000 claims description 25
- 238000002161 passivation Methods 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 239000010949 copper Substances 0.000 abstract description 5
- 230000002787 reinforcement Effects 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 138
- 239000000463 material Substances 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
【解決手段】半導体基板上の、補強構造体を有するボンディングコンタクトにおいて、このボンディングコンタクトには、半導体基板上に配置される少なくとも1つの第1金属層と、この第1金属層の上方に配置される第3金属層とを有しており、第1金属層には、パターンを有する補強構造体が収容され、第3金属層は、ボンディング面を有するボンディングコンタクト層であり、さらに上記のボンディング面の下方かつ第1金属層の上方に絶縁層が配置されており、この絶縁層は、ボンディング面の縁部を越えて突き出ている。る、ボンディング個所(1)において、上記の補強構造体は、ボンディング面の上側から見た場合にこのボンディング面の下方において第1金属層内に構成されており、この補強構造体には誘電体島が含まれている。
【選択図】図1
Description
− 上記の補強構造体は、規則的に配置される第1形状の島および第2形状の島から構成され、
− 第1形状の島は格子状に配置されており、
− 格子点を構成しかつ隣接する4つの第1形状の島の間にそれぞれ第2形状の島が配置されており、
− 第2形状の島は、格子状の構造を構成する。
− 上記の補強構造体が、規則的に配置される島からなるパターンを有し、
− 上記の導電性材料層は、補強構造体をフレーム状に包囲し、
− 上記の導電性材料層は、縁部領域にて、少なくとも1つの誘電体層に配置される貫通コンタクト部を介して上記のボンディングコンタクト層に電気的に接続される。
Claims (12)
- 半導体基板(2)上の、補強構造体(10)を有するボンディングコンタクト(1)において、
該ボンディングコンタクトには、
− 前記の半導体基板(2)上に配置される少なくとも1つの第1金属層(3)と、
− 当該の第1金属層(3)の上方に配置される第3金属層(4)とを有しており、
前記の第1金属層(3)には、パターンを有する補強構造体(10)が収容され、
前記の第3金属層(4)は、ボンディング面(ボンディングパッド)(5)を有するボンディングコンタクト層であり、
さらに
− 前記のボンディング面(5)の下方かつ第1金属層(3)の上方に絶縁層(14)が配置されており、
当該の絶縁層(14)は、前記のボンディング面(5)の縁部(5a)を越えて突き出ている、ボンディングコンタクト(1)において、
− 前記の補強構造体(10)は、当該のボンディング面(5)の上側から見た場合に当該のボンディング面(5)の下方において第1金属層(3)内に構成されており、
− 当該の補強構造体(10)には誘電体島(11,12)が含まれていることを特徴とする
ボンディングコンタクト(1)。 - 前記の絶縁層(14)は、少なくともほぼ2μmの厚さを有し、かつ複数の部分層から構成される、
請求項1に記載のボンディングコンタクト。 - − 前記の補強構造体(10)は、規則的に配置される第1形状の島(11)および第2形状の島(12)から構成され、
− 第1形状の島(11)は格子状に配置されており、
− 当該の第1形状の島(11)は、直に隣接する4つの第2形状の島(12)の間にそれぞれ配置されており、
− 第2形状の島(12)は格子状の構造を構成する、
請求項1または2項に記載のボンディングコンタクト。 - 前記の第1金属層(3)にフレーム(3c)が構成されており、
当該フレーム(3c)により、前記の補強構造体(10)が包囲される、
請求項1から3までのいずれか1項に記載のボンディングコンタクト。 - 前記の第1金属層(3)は、縁部領域にて、少なくとも1つの誘電体層(8)に配置される貫通コンタクト部(15)を介して前記のボンディングコンタクト層(4)に電気的に接続される、
請求項1から4までのいずれか1項に記載のボンディングコンタクト。 - 前記の第1形状の島(11)は、第1金属層(3)の面にて正方形または矩形の断面を有する、
請求項1から5までのいずれか1項に記載のボンディングコンタクト(1)。 - 前記の第2形状の島(12)は、第1金属層(3)の面にて十字形の断面を有する、
請求項1から6までのいずれか1項に記載のボンディングコンタクト(1)。 - 第2金属層(7)が設けられており、
該第2金属層(7)は、前記の補強構造体(10)を有する第1金属層(3)の上に配置されており、かつ誘電体から構成されかつ中央に配置される島を有しており、
当該の島は、第2金属層(7)によってフレーム状に包囲される、
請求項1から7までのいずれか1項に記載のボンディングコンタクト(1)。 - 前記の第1金属層(3)と第2金属層(7)との間に誘電体層(8)が配置されており、
該誘電体層より、縁部領域に配置された貫通コンタクト部(15)を介して前記の2つの導電性材料層(3,7)が電気的に接続される、
請求項8に記載のボンディングコンタクト(1)。 - 前記のボンディング面(5)は、縁部領域にて、誘電体層(6)に配置される貫通コンタクト部(16)を介して第2金属層(7)に電気的に接続される、
請求項9に記載のボンディングコンタクト(1)。 - 前記のボンディング面(5)は、パッシベーション層(13)の開口部によって定められ、
前記の貫通コンタクト部(15,16)は、当該のパッシベーション層(13)の縁部領域に配置される、
請求項1から10までのいずれか1項に記載のボンディングコンタクト(1)。 - 前記の金属製のフレームの外側の縁部(3c,7a)と、ボンディング面の外側の縁部(5a)とはそれぞれラテラル方向にずれている、
請求項1から11までのいずれか1項に記載のボンディング個所(1)。
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US11251122B2 (en) | 2019-10-30 | 2022-02-15 | Kioxia Corporation | Semiconductor device having a bonding pad area of a first wiring layer overlaps a bonding pad electrode of a second wiring layer |
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US6143396A (en) * | 1997-05-01 | 2000-11-07 | Texas Instruments Incorporated | System and method for reinforcing a bond pad |
US6552438B2 (en) * | 1998-06-24 | 2003-04-22 | Samsung Electronics Co. | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same |
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US7629689B2 (en) * | 2004-01-22 | 2009-12-08 | Kawasaki Microelectronics, Inc. | Semiconductor integrated circuit having connection pads over active elements |
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