JP2011515842A - 高密度インターコネクトのためのシリコンパッチ含有マイクロエレクトロニクスパッケージおよびその製造方法 - Google Patents
高密度インターコネクトのためのシリコンパッチ含有マイクロエレクトロニクスパッケージおよびその製造方法 Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 68
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 68
- 239000010703 silicon Substances 0.000 title claims abstract description 68
- 238000004377 microelectronic Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims description 28
- 230000007246 mechanism Effects 0.000 claims description 26
- 230000008878 coupling Effects 0.000 claims description 19
- 238000010168 coupling process Methods 0.000 claims description 19
- 238000005859 coupling reaction Methods 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 238000002788 crimping Methods 0.000 claims description 4
- 239000012928 buffer substance Substances 0.000 claims 2
- 230000008901 benefit Effects 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 239000010410 layer Substances 0.000 description 6
- 239000011295 pitch Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Abstract
【選択図】図1
Description
Claims (20)
- 基板と、
前記基板に埋め込まれたシリコンパッチと、
前記シリコンパッチの第1位置の第1インターコネクト構造および前記シリコンパッチの第2位置の第2インターコネクト構造と、
前記第1インターコネクト構造と前記第2インターコネクト構造とを互いに接続する前記シリコンパッチ中の電気的導電線とを備えるマイクロエレクトロニクスパッケージ。 - 前記基板は、内部に緩衝物質を有するウェルを含み、
前記シリコンパッチは、前記緩衝物質に隣接して前記ウェル中に埋め込まれる請求項1に記載のマイクロエレクトロニクスパッケージ。 - 前記第1インターコネクト構造および前記第2インターコネクト構造の少なくとも一方は銅ピラーを備える請求項1に記載のマイクロエレクトロニクスパッケージ。
- 前記銅ピラーは連結機構を備える請求項3に記載のマイクロエレクトロニクスパッケージ。
- 前記電気的導電線の幅は略0.2ミクロンよりも小さい請求項1に記載のマイクロエレクトロニクスパッケージ。
- 前記基板中に電力線をさらに備える請求項1に記載のマイクロエレクトロニクスパッケージ。
- 前記基板は、略10ppm/°Kから略12ppm/°Kの間の実効熱膨張係数を有する請求項1に記載のマイクロエレクトロニクスパッケージ。
- 基板と、
前記基板上の第1ダイおよび第2ダイと、
前記基板に埋め込まれたシリコンパッチと、
前記第1ダイの下にある前記シリコンパッチ中の第1の複数のインターコネクト構造、および前記第2ダイの下にある前記シリコンパッチ中の第2の複数のインターコネクト構造と、
前記第1の複数のインターコネクト構造の1つと、前記第2の複数のインターコネクト構造の1つとを互いに接続する電気的導電線とを備えるマイクロエレクトロニクスパッケージ。 - 前記基板は、内部に緩衝物質を有するウェルを含み、
前記シリコンパッチは、前記緩衝物質に隣接して前記ウェル中に埋め込まれる請求項8に記載のマイクロエレクトロニクスパッケージ。 - 前記第1の複数のインターコネクト構造および前記第2の複数のインターコネクト構造の少なくとも一方における少なくとも1対の隣接したインターコネクト構造間の間隔が80ミクロンよりも小さい請求項9に記載のマイクロエレクトロニクスパッケージ。
- 前記基板は、略10ppm/°Kから略12ppm/°Kの間の実効熱膨張係数を有する請求項9に記載のマイクロエレクトロニクスパッケージ。
- 前記第1の複数のインターコネクト構造および前記第2の複数のインターコネクト構造のそれぞれは銅ピラーを備える請求項9に記載のマイクロエレクトロニクスパッケージ。
- 前記銅ピラーの少なくとも1つは連結機構を備える請求項12に記載のマイクロエレクトロニクスパッケージ。
- 前記電気的導電線の幅は略0.2ミクロンよりも小さい請求項12に記載のマイクロエレクトロニクスパッケージ。
- 前記基板中に電力線をさらに備える請求項14に記載のマイクロエレクトロニクスパッケージ。
- 埋め込まれたシリコンパッチを内部に有する基板を提供する段階と、
前記シリコンパッチの第1の位置に第1インターコネクト構造を形成し、前記シリコンパッチの第2の位置に第2インターコネクト構造を形成する段階と、
前記第1インターコネクト構造と前記第2インターコネクト構造とを電気的に互いに接続する段階とを備えるマイクロエレクトロニクスパッケージの製造方法。 - 前記第1の位置上に第1ダイを、前記第2の位置上に第2ダイを与える段階と、
前記第1ダイと前記第1インターコネクト構造とを電気的に互いに接続する段階と、
前記第2ダイと前記第2インターコネクト構造とを電気的に互いに接続する段階とをさらに備える請求項16に記載の方法。 - 前記第1ダイと前記第1インターコネクト構造とを電気的に互いに接続する段階は、
前記第1ダイに第1電気的導電構造を与える段階と、
前記第1電気的導電構造と前記第1インターコネクト構造との間の第1はんだ接合を与える段階とを備え、
前記第2ダイと前記第2インターコネクト構造とを電気的に互いに接続する段階は、
前記第2ダイに第2電気的導電構造を与える段階と、
前記第2電気的導電構造と前記第2インターコネクト構造との間の第2はんだ接合を与える段階とを備える請求項17に記載の方法。 - 前記第1ダイと前記第1インターコネクト構造とを電気的に互いに接続する段階は、
前記第1ダイに第1電気的導電構造を与える段階と、
前記第1電気的導電構造と前記第1インターコネクト構造とを一緒に圧着する段階とを備え、
前記第2ダイと前記第2インターコネクト構造とを電気的に互いに接続する段階は、
前記第2ダイに第2電気的導電構造を与える段階と、
前記第2電気的導電構造と前記第2インターコネクト構造とを一緒に圧着する段階とを備える請求項17に記載の方法。 - 前記第1インターコネクト構造は第1連結機構を有し、
前記第2インターコネクト構造は第2連結機構を有し、
前記第1ダイと前記第1インターコネクト構造とを電気的に互いに接続する段階は、
第3連結機構を有する第1電気的導電構造を前記第1ダイに与える段階と、
前記第1連結機構と前記第3連結機構とを連結する段階とを備え、
前記第2ダイと前記第2インターコネクト構造とを電気的に互いに接続する段階は、
第4連結機構を有する第2電気的導電構造を前記第2ダイに与える段階と、
前記第2連結機構と前記第4連結機構とを連結する段階とを備える請求項17に記載の方法。
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Also Published As
Publication number | Publication date |
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KR20100116689A (ko) | 2010-11-01 |
KR101182010B1 (ko) | 2012-09-11 |
GB201015981D0 (en) | 2010-11-03 |
DE112009000351T5 (de) | 2011-05-05 |
US8441809B2 (en) | 2013-05-14 |
WO2009146007A2 (en) | 2009-12-03 |
US20110241208A1 (en) | 2011-10-06 |
DE112009005576B4 (de) | 2024-05-08 |
DE112009000351B4 (de) | 2014-07-17 |
TW200950034A (en) | 2009-12-01 |
GB2470866A (en) | 2010-12-08 |
US20090244874A1 (en) | 2009-10-01 |
WO2009146007A3 (en) | 2010-01-21 |
CN101960589A (zh) | 2011-01-26 |
GB2470866B (en) | 2012-10-03 |
CN101960589B (zh) | 2012-10-10 |
TWI425602B (zh) | 2014-02-01 |
DE112009005519B4 (de) | 2021-08-19 |
US8064224B2 (en) | 2011-11-22 |
DE112009005519A5 (de) | 2014-12-31 |
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