JP2011249491A - Power semiconductor device - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000010410 layer Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000003870 refractory metal Substances 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000006378 damage Effects 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
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Abstract
Description
本発明は、IGBT(Insulated Gate Bipolar Transistor)やMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)などの電力用半導体装置に関し、特に素子破壊を防いで信頼性を向上することができる電力用半導体装置に関する。 The present invention relates to power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and more particularly to power semiconductor devices that can prevent element destruction and improve reliability. About.
電力用半導体装置では、特性向上のために複数のセル領域が主電極により並列接続されている。また、主電極と複数のセル領域の制御電極とは、層間絶縁膜により絶縁されている。各セル領域において層間絶縁膜と半導体層の間に段差が存在する(例えば、特許文献1参照)。 In a power semiconductor device, a plurality of cell regions are connected in parallel by a main electrode in order to improve characteristics. Further, the main electrode and the control electrodes of the plurality of cell regions are insulated by the interlayer insulating film. In each cell region, there is a step between the interlayer insulating film and the semiconductor layer (see, for example, Patent Document 1).
各セル領域において段差が存在するため、複数のセル領域上の主電極にワイヤを超音波接続する場合、大きな超音波パワーにより層間絶縁膜やセル領域などの素子が破壊される場合があった。また、アウタリードを主電極に直接に圧接やはんだ接続する場合でも、熱ストレスにより素子が破壊される場合があった。 Since there is a step in each cell region, when a wire is ultrasonically connected to a main electrode on a plurality of cell regions, elements such as an interlayer insulating film and a cell region may be destroyed by a large ultrasonic power. Even when the outer lead is directly pressed or soldered to the main electrode, the element may be destroyed due to thermal stress.
本発明は、上述のような課題を解決するためになされたもので、その目的は、素子破壊を防いで信頼性を向上することができる電力用半導体装置を得るものである。 The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a power semiconductor device that can prevent element destruction and improve reliability.
本発明は、互いに対向する第1の主面と第2の主面を有する半導体基板と、前記半導体基板の前記第1の主面に形成された複数のセル領域と、前記複数のセル領域上に形成された第1の主電極と、前記半導体基板の前記第2の主面上に形成された第2の主電極とを備え、各セル領域は、前記第1の主電極に接続された半導体層と、制御電極と、前記制御電極を覆って前記第1の主電極に対して絶縁する層間絶縁膜とを有し、各セル領域において前記層間絶縁膜と前記半導体層の間に段差が存在し、前記第1の主電極は、前記半導体基板上に順次形成された、第1の金属膜と、高強度金属膜と、第2の金属膜とを有し、前記第1の金属膜及び前記第2の金属膜はAlを95%以上有し、前記高強度金属膜は、前記第2の金属膜よりも強度が高いことを特徴とする電力用半導体装置である。 The present invention provides a semiconductor substrate having a first main surface and a second main surface facing each other, a plurality of cell regions formed on the first main surface of the semiconductor substrate, and the plurality of cell regions. A first main electrode formed on the semiconductor substrate and a second main electrode formed on the second main surface of the semiconductor substrate, each cell region being connected to the first main electrode A semiconductor layer; a control electrode; and an interlayer insulating film that covers the control electrode and insulates from the first main electrode, and a step is formed between the interlayer insulating film and the semiconductor layer in each cell region. The first main electrode includes a first metal film, a high-strength metal film, and a second metal film, which are sequentially formed on the semiconductor substrate, and the first metal film The second metal film has 95% or more of Al, and the high-strength metal film has higher strength than the second metal film. DOO is a power semiconductor device according to claim.
本発明により、素子破壊を防いで信頼性を向上することができる。 According to the present invention, element breakdown can be prevented and reliability can be improved.
本発明の実施の形態に係る電力用半導体装置について図面を参照して説明する。同じ構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。 A power semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same components are denoted by the same reference numerals, and repeated description may be omitted.
実施の形態1.
図1は、実施の形態1に係る電力用半導体装置を示す断面図である。n型半導体基板10はSiからなり、互いに対向する第1の主面と第2の主面を有する。n型半導体基板10の第1の主面にp型半導体層12が形成されている。p型半導体層12の表面の一部にn+半導体層14が形成されている。n+半導体層14とp型半導体層12を貫通してn型半導体基板10に達するトレンチ溝16が形成されている。トレンチ溝16内にゲート絶縁膜18を介してゲート電極20が埋設されている。層間絶縁膜22がゲート電極20を覆っている。
Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the power semiconductor device according to the first embodiment. N-
n型半導体基板10の第1の主面に複数のセル領域24が形成されている。各セル領域24は、n+半導体層14及びp型半導体層12と、ゲート電極20と、層間絶縁膜22とを有する。各セル領域24において層間絶縁膜22とn+半導体層14及びp型半導体層12との間に段差が存在する。
A plurality of
複数のセル領域24上にエミッタ電極26が形成されている。エミッタ電極26はn+半導体層14及びp型半導体層12に接続されている。ゲート電極20は層間絶縁膜22によりエミッタ電極26に対して絶縁されている。n型半導体基板10の第2の主面にn+半導体層28とp型コレクタ層30が形成されている。第2の主面上にコレクタ電極32が形成されている。
エミッタ電極26は、n型半導体基板10上に順次形成されたバリアメタル26aと、第1の金属膜26bと、高強度金属膜26cと、第2の金属膜26dとを有する。ここで、加工性やワイヤ接続の容易性から、第1の金属膜26b及び第2の金属膜26dはAlを95%以上有する金属からなる。一方、バリアメタル26a及び高強度金属膜26cは、Ti,W,Mo,Vなどの高融点金属又は高融点金属の導電性化合物からなる。従って、高強度金属膜26cは第2の金属膜26dよりも強度が高い。
The
本実施の形態の効果について比較例と比較しながら説明する。図2は、比較例に係る電力用半導体装置を示す断面図である。比較例では、エミッタ電極34は、Alを95%以上有する1つの膜だけからなる。このエミッタ電極34にワイヤを超音波接続する際にエミッタ電極34が変形して、層間絶縁膜22やセル領域24などの素子が破壊される場合がある。
The effect of this embodiment will be described in comparison with a comparative example. FIG. 2 is a cross-sectional view showing a power semiconductor device according to a comparative example. In the comparative example, the
一方、本実施の形態でも、エミッタ電極26にワイヤを超音波接続する際に第2の金属膜26dは変形する。しかし、第2の金属膜26dよりも強度が高い高強度金属膜26cが存在するため、第1の金属膜26bの変形は抑制される。従って、ワイヤ接続による層間絶縁膜22やセル領域24へのダメージを緩和できる。また、アウタリードを主電極に直接に圧接やはんだ接続する場合でも、熱ストレスによる素子破壊を防ぐことができる。よって、素子破壊を防いで信頼性を向上することができる。
On the other hand, also in the present embodiment, the
また、第1の金属膜26bの下に高融点金属又は高融点金属の導電性化合物からなるバリアメタル26aを設けることで、MOSFETやIGBTなどの微細パターンを有する半導体装置において電極によるSi食われを防止できる。
Further, by providing a
また、第1の金属膜26bは層間絶縁膜22よりも厚いことが好ましい。そして、0.5mmΦ程度の太線ワイヤや0.5mm厚程度のリボンワイヤーを接続することを考えると、第2の金属膜26dの厚みは3μm以上であることが好ましい。これにより、更に確実に素子破壊を防ぐことができる。
The
実施の形態2.
図3は、実施の形態2に係る電力用半導体装置を示す断面図である。第1の金属膜26bはAlの高温スパッタやリフローAl工程により層間絶縁膜22を埋めることで形成され、第1の金属膜26bの上面は平坦化されている。
Embodiment 2. FIG.
FIG. 3 is a cross-sectional view showing the power semiconductor device according to the second embodiment. The
これにより、ワイヤ36を接続する際に第2の金属膜26dにかかる応力を高強度金属膜26cで均等に受けることができるため、ダメージを更に緩和できる。なお、アウタリードを主電極に直接に圧接やはんだ接続する場合でも、同様に熱ストレスによる素子破壊を更に確実に防ぐことができる。
Thereby, when the
なお、実施の形態1,2に係る電力用半導体装置はトレンチIGBTであるが、これに限らず本発明は複数のセル領域を備える縦型の電力用半導体装置に適用することができる。 The power semiconductor device according to the first and second embodiments is a trench IGBT. However, the present invention is not limited to this, and the present invention can be applied to a vertical power semiconductor device including a plurality of cell regions.
10 n型半導体基板(半導体基板)
12 p型半導体層(半導体層)
14 n+半導体層(半導体層)
20 ゲート電極(制御電極)
22 層間絶縁膜
24 セル領域
26 エミッタ電極(第1の主電極)
26a バリアメタル
26b 第1の金属膜
26c 高強度金属膜
26d 第2の金属膜
32 コレクタ電極(第2の主電極)
10 n-type semiconductor substrate (semiconductor substrate)
12 p-type semiconductor layer (semiconductor layer)
14 n + semiconductor layer (semiconductor layer)
20 Gate electrode (control electrode)
22
Claims (5)
前記半導体基板の前記第1の主面に形成された複数のセル領域と、
前記複数のセル領域上に形成された第1の主電極と、
前記半導体基板の前記第2の主面上に形成された第2の主電極とを備え、
各セル領域は、前記第1の主電極に接続された半導体層と、制御電極と、前記制御電極を覆って前記第1の主電極に対して絶縁する層間絶縁膜とを有し、
各セル領域において前記層間絶縁膜と前記半導体層の間に段差が存在し、
前記第1の主電極は、前記半導体基板上に順次形成された、第1の金属膜と、高強度金属膜と、第2の金属膜とを有し、
前記第1の金属膜及び前記第2の金属膜はAlを95%以上有し、
前記高強度金属膜は、前記第2の金属膜よりも強度が高いことを特徴とする電力用半導体装置。 A semiconductor substrate having a first main surface and a second main surface facing each other;
A plurality of cell regions formed on the first main surface of the semiconductor substrate;
A first main electrode formed on the plurality of cell regions;
A second main electrode formed on the second main surface of the semiconductor substrate,
Each cell region has a semiconductor layer connected to the first main electrode, a control electrode, and an interlayer insulating film that covers the control electrode and insulates from the first main electrode,
In each cell region, there is a step between the interlayer insulating film and the semiconductor layer,
The first main electrode includes a first metal film, a high-strength metal film, and a second metal film, which are sequentially formed on the semiconductor substrate,
The first metal film and the second metal film have 95% or more of Al,
The power semiconductor device is characterized in that the high-strength metal film has higher strength than the second metal film.
前記第2の金属膜の厚みは3μm以上であることを特徴とする請求項1〜3の何れか1項に記載の電力用半導体装置。 The first metal film is thicker than the interlayer insulating film,
4. The power semiconductor device according to claim 1, wherein a thickness of the second metal film is 3 μm or more. 5.
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