JP2011249491A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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JP2011249491A
JP2011249491A JP2010120059A JP2010120059A JP2011249491A JP 2011249491 A JP2011249491 A JP 2011249491A JP 2010120059 A JP2010120059 A JP 2010120059A JP 2010120059 A JP2010120059 A JP 2010120059A JP 2011249491 A JP2011249491 A JP 2011249491A
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metal film
electrode
semiconductor layer
semiconductor substrate
semiconductor device
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Takuya Hamaguchi
卓也 浜口
Tetsujiro Tsunoda
哲次郎 角田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to KR1020110036002A priority patent/KR101248440B1/en
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Abstract

PROBLEM TO BE SOLVED: To obtain a power semiconductor device which can enhance reliability by preventing breakdown of elements.SOLUTION: A plurality of cell regions 24 are formed on a first principal surface of an n-type semiconductor substrate 10, and an emitter electrode 26 is formed on the plurality of cell regions 24. A collector electrode 32 is formed on a second principal surface of the n-type semiconductor substrate 10. Each cell region 24 has an n+ semiconductor layer 14 and a p-type semiconductor layer 12 connected with the emitter electrode 26, a gate electrode 20, and an interlayer insulating film 22 which covers the gate electrode 20 and insulates the gate electrode 20 for the emitter electrode 26. In each cell region 24, a level difference exists between the interlayer insulating film 22 and the n+ semiconductor layer 14 and p-type semiconductor layer 12. The emitter electrode 26 has a first metal film 26b, a high strength metal film 26c, and a second metal film 26d formed sequentially on the n-type semiconductor substrate 10. The first metal film 26b and the second metal film 26d contain 95% or more of Al. The high strength metal film 26c has a strength higher than that of the second metal film 26d.

Description

本発明は、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）などの電力用半導体装置に関し、特に素子破壊を防いで信頼性を向上することができる電力用半導体装置に関する。   The present invention relates to power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and more particularly to power semiconductor devices that can prevent element destruction and improve reliability. About.

電力用半導体装置では、特性向上のために複数のセル領域が主電極により並列接続されている。また、主電極と複数のセル領域の制御電極とは、層間絶縁膜により絶縁されている。各セル領域において層間絶縁膜と半導体層の間に段差が存在する（例えば、特許文献１参照）。   In a power semiconductor device, a plurality of cell regions are connected in parallel by a main electrode in order to improve characteristics. Further, the main electrode and the control electrodes of the plurality of cell regions are insulated by the interlayer insulating film. In each cell region, there is a step between the interlayer insulating film and the semiconductor layer (see, for example, Patent Document 1).

特開平５−２７５５０１号公報JP-A-5-275501

各セル領域において段差が存在するため、複数のセル領域上の主電極にワイヤを超音波接続する場合、大きな超音波パワーにより層間絶縁膜やセル領域などの素子が破壊される場合があった。また、アウタリードを主電極に直接に圧接やはんだ接続する場合でも、熱ストレスにより素子が破壊される場合があった。   Since there is a step in each cell region, when a wire is ultrasonically connected to a main electrode on a plurality of cell regions, elements such as an interlayer insulating film and a cell region may be destroyed by a large ultrasonic power. Even when the outer lead is directly pressed or soldered to the main electrode, the element may be destroyed due to thermal stress.

本発明は、上述のような課題を解決するためになされたもので、その目的は、素子破壊を防いで信頼性を向上することができる電力用半導体装置を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a power semiconductor device that can prevent element destruction and improve reliability.

本発明は、互いに対向する第１の主面と第２の主面を有する半導体基板と、前記半導体基板の前記第１の主面に形成された複数のセル領域と、前記複数のセル領域上に形成された第１の主電極と、前記半導体基板の前記第２の主面上に形成された第２の主電極とを備え、各セル領域は、前記第１の主電極に接続された半導体層と、制御電極と、前記制御電極を覆って前記第１の主電極に対して絶縁する層間絶縁膜とを有し、各セル領域において前記層間絶縁膜と前記半導体層の間に段差が存在し、前記第１の主電極は、前記半導体基板上に順次形成された、第１の金属膜と、高強度金属膜と、第２の金属膜とを有し、前記第１の金属膜及び前記第２の金属膜はＡｌを９５％以上有し、前記高強度金属膜は、前記第２の金属膜よりも強度が高いことを特徴とする電力用半導体装置である。   The present invention provides a semiconductor substrate having a first main surface and a second main surface facing each other, a plurality of cell regions formed on the first main surface of the semiconductor substrate, and the plurality of cell regions. A first main electrode formed on the semiconductor substrate and a second main electrode formed on the second main surface of the semiconductor substrate, each cell region being connected to the first main electrode A semiconductor layer; a control electrode; and an interlayer insulating film that covers the control electrode and insulates from the first main electrode, and a step is formed between the interlayer insulating film and the semiconductor layer in each cell region. The first main electrode includes a first metal film, a high-strength metal film, and a second metal film, which are sequentially formed on the semiconductor substrate, and the first metal film The second metal film has 95% or more of Al, and the high-strength metal film has higher strength than the second metal film. DOO is a power semiconductor device according to claim.

本発明により、素子破壊を防いで信頼性を向上することができる。   According to the present invention, element breakdown can be prevented and reliability can be improved.

実施の形態１に係る電力用半導体装置を示す断面図である。1 is a cross-sectional view showing a power semiconductor device according to a first embodiment. 比較例に係る電力用半導体装置を示す断面図である。It is sectional drawing which shows the power semiconductor device which concerns on a comparative example. 実施の形態２に係る電力用半導体装置を示す断面図である。FIG. 6 is a cross-sectional view showing a power semiconductor device according to a second embodiment.

本発明の実施の形態に係る電力用半導体装置について図面を参照して説明する。同じ構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A power semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、実施の形態１に係る電力用半導体装置を示す断面図である。ｎ型半導体基板１０はＳｉからなり、互いに対向する第１の主面と第２の主面を有する。ｎ型半導体基板１０の第１の主面にｐ型半導体層１２が形成されている。ｐ型半導体層１２の表面の一部にｎ＋半導体層１４が形成されている。ｎ＋半導体層１４とｐ型半導体層１２を貫通してｎ型半導体基板１０に達するトレンチ溝１６が形成されている。トレンチ溝１６内にゲート絶縁膜１８を介してゲート電極２０が埋設されている。層間絶縁膜２２がゲート電極２０を覆っている。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the power semiconductor device according to the first embodiment. N-type semiconductor substrate 10 is made of Si and has a first main surface and a second main surface facing each other. A p-type semiconductor layer 12 is formed on the first main surface of the n-type semiconductor substrate 10. An n + semiconductor layer 14 is formed on part of the surface of the p-type semiconductor layer 12. A trench groove 16 that penetrates the n + semiconductor layer 14 and the p-type semiconductor layer 12 and reaches the n-type semiconductor substrate 10 is formed. A gate electrode 20 is embedded in the trench 16 via a gate insulating film 18. An interlayer insulating film 22 covers the gate electrode 20.

ｎ型半導体基板１０の第１の主面に複数のセル領域２４が形成されている。各セル領域２４は、ｎ＋半導体層１４及びｐ型半導体層１２と、ゲート電極２０と、層間絶縁膜２２とを有する。各セル領域２４において層間絶縁膜２２とｎ＋半導体層１４及びｐ型半導体層１２との間に段差が存在する。   A plurality of cell regions 24 are formed on the first main surface of the n-type semiconductor substrate 10. Each cell region 24 includes an n + semiconductor layer 14 and a p-type semiconductor layer 12, a gate electrode 20, and an interlayer insulating film 22. In each cell region 24, there is a step between the interlayer insulating film 22 and the n + semiconductor layer 14 and the p-type semiconductor layer 12.

複数のセル領域２４上にエミッタ電極２６が形成されている。エミッタ電極２６はｎ＋半導体層１４及びｐ型半導体層１２に接続されている。ゲート電極２０は層間絶縁膜２２によりエミッタ電極２６に対して絶縁されている。ｎ型半導体基板１０の第２の主面にｎ＋半導体層２８とｐ型コレクタ層３０が形成されている。第２の主面上にコレクタ電極３２が形成されている。   Emitter electrodes 26 are formed on the plurality of cell regions 24. The emitter electrode 26 is connected to the n + semiconductor layer 14 and the p-type semiconductor layer 12. The gate electrode 20 is insulated from the emitter electrode 26 by the interlayer insulating film 22. An n + semiconductor layer 28 and a p-type collector layer 30 are formed on the second main surface of the n-type semiconductor substrate 10. A collector electrode 32 is formed on the second main surface.

エミッタ電極２６は、ｎ型半導体基板１０上に順次形成されたバリアメタル２６ａと、第１の金属膜２６ｂと、高強度金属膜２６ｃと、第２の金属膜２６ｄとを有する。ここで、加工性やワイヤ接続の容易性から、第１の金属膜２６ｂ及び第２の金属膜２６ｄはＡｌを９５％以上有する金属からなる。一方、バリアメタル２６ａ及び高強度金属膜２６ｃは、Ｔｉ，Ｗ，Ｍｏ，Ｖなどの高融点金属又は高融点金属の導電性化合物からなる。従って、高強度金属膜２６ｃは第２の金属膜２６ｄよりも強度が高い。   The emitter electrode 26 includes a barrier metal 26a, a first metal film 26b, a high-strength metal film 26c, and a second metal film 26d that are sequentially formed on the n-type semiconductor substrate 10. Here, from the viewpoint of workability and ease of wire connection, the first metal film 26b and the second metal film 26d are made of a metal containing 95% or more of Al. On the other hand, the barrier metal 26a and the high-strength metal film 26c are made of a refractory metal such as Ti, W, Mo, or V or a conductive compound of a refractory metal. Accordingly, the high-strength metal film 26c has higher strength than the second metal film 26d.

本実施の形態の効果について比較例と比較しながら説明する。図２は、比較例に係る電力用半導体装置を示す断面図である。比較例では、エミッタ電極３４は、Ａｌを９５％以上有する１つの膜だけからなる。このエミッタ電極３４にワイヤを超音波接続する際にエミッタ電極３４が変形して、層間絶縁膜２２やセル領域２４などの素子が破壊される場合がある。   The effect of this embodiment will be described in comparison with a comparative example. FIG. 2 is a cross-sectional view showing a power semiconductor device according to a comparative example. In the comparative example, the emitter electrode 34 is composed of only one film having 95% or more of Al. When the wire is ultrasonically connected to the emitter electrode 34, the emitter electrode 34 may be deformed, and elements such as the interlayer insulating film 22 and the cell region 24 may be destroyed.

一方、本実施の形態でも、エミッタ電極２６にワイヤを超音波接続する際に第２の金属膜２６ｄは変形する。しかし、第２の金属膜２６ｄよりも強度が高い高強度金属膜２６ｃが存在するため、第１の金属膜２６ｂの変形は抑制される。従って、ワイヤ接続による層間絶縁膜２２やセル領域２４へのダメージを緩和できる。また、アウタリードを主電極に直接に圧接やはんだ接続する場合でも、熱ストレスによる素子破壊を防ぐことができる。よって、素子破壊を防いで信頼性を向上することができる。   On the other hand, also in the present embodiment, the second metal film 26d is deformed when a wire is ultrasonically connected to the emitter electrode 26. However, since the high-strength metal film 26c having higher strength than the second metal film 26d exists, the deformation of the first metal film 26b is suppressed. Therefore, damage to the interlayer insulating film 22 and the cell region 24 due to wire connection can be reduced. Further, even when the outer lead is directly pressed or soldered to the main electrode, it is possible to prevent element destruction due to thermal stress. Therefore, element destruction can be prevented and reliability can be improved.

また、第１の金属膜２６ｂの下に高融点金属又は高融点金属の導電性化合物からなるバリアメタル２６ａを設けることで、ＭＯＳＦＥＴやＩＧＢＴなどの微細パターンを有する半導体装置において電極によるＳｉ食われを防止できる。   Further, by providing a barrier metal 26a made of a refractory metal or a conductive compound of a refractory metal under the first metal film 26b, Si erosion due to the electrodes is prevented in a semiconductor device having a fine pattern such as a MOSFET or IGBT. Can be prevented.

また、第１の金属膜２６ｂは層間絶縁膜２２よりも厚いことが好ましい。そして、０．５ｍｍΦ程度の太線ワイヤや０．５ｍｍ厚程度のリボンワイヤーを接続することを考えると、第２の金属膜２６ｄの厚みは３μｍ以上であることが好ましい。これにより、更に確実に素子破壊を防ぐことができる。   The first metal film 26 b is preferably thicker than the interlayer insulating film 22. In consideration of connecting a thick wire of about 0.5 mmΦ or a ribbon wire of about 0.5 mm, the thickness of the second metal film 26d is preferably 3 μm or more. Thereby, element destruction can be prevented more reliably.

実施の形態２．
図３は、実施の形態２に係る電力用半導体装置を示す断面図である。第１の金属膜２６ｂはＡｌの高温スパッタやリフローＡｌ工程により層間絶縁膜２２を埋めることで形成され、第１の金属膜２６ｂの上面は平坦化されている。 Embodiment 2. FIG.
FIG. 3 is a cross-sectional view showing the power semiconductor device according to the second embodiment. The first metal film 26b is formed by filling the interlayer insulating film 22 by high temperature sputtering of Al or a reflow Al process, and the upper surface of the first metal film 26b is flattened.

これにより、ワイヤ３６を接続する際に第２の金属膜２６ｄにかかる応力を高強度金属膜２６ｃで均等に受けることができるため、ダメージを更に緩和できる。なお、アウタリードを主電極に直接に圧接やはんだ接続する場合でも、同様に熱ストレスによる素子破壊を更に確実に防ぐことができる。   Thereby, when the wire 36 is connected, the stress applied to the second metal film 26d can be evenly received by the high-strength metal film 26c, so that the damage can be further alleviated. Even when the outer lead is directly press-contacted or soldered to the main electrode, similarly, element destruction due to thermal stress can be further reliably prevented.

なお、実施の形態１，２に係る電力用半導体装置はトレンチＩＧＢＴであるが、これに限らず本発明は複数のセル領域を備える縦型の電力用半導体装置に適用することができる。   The power semiconductor device according to the first and second embodiments is a trench IGBT. However, the present invention is not limited to this, and the present invention can be applied to a vertical power semiconductor device including a plurality of cell regions.

１０ ｎ型半導体基板（半導体基板）
１２ ｐ型半導体層（半導体層）
１４ ｎ＋半導体層（半導体層）
２０ ゲート電極（制御電極）
２２ 層間絶縁膜
２４ セル領域
２６ エミッタ電極（第１の主電極）
２６ａ バリアメタル
２６ｂ 第１の金属膜
２６ｃ 高強度金属膜
２６ｄ 第２の金属膜
３２ コレクタ電極（第２の主電極） 10 n-type semiconductor substrate (semiconductor substrate)
12 p-type semiconductor layer (semiconductor layer)
14 n + semiconductor layer (semiconductor layer)
20 Gate electrode (control electrode)
22 Interlayer insulating film 24 Cell region 26 Emitter electrode (first main electrode)
26a barrier metal 26b first metal film 26c high-strength metal film 26d second metal film 32 collector electrode (second main electrode)

Claims (5)

互いに対向する第１の主面と第２の主面を有する半導体基板と、
前記半導体基板の前記第１の主面に形成された複数のセル領域と、
前記複数のセル領域上に形成された第１の主電極と、
前記半導体基板の前記第２の主面上に形成された第２の主電極とを備え、
各セル領域は、前記第１の主電極に接続された半導体層と、制御電極と、前記制御電極を覆って前記第１の主電極に対して絶縁する層間絶縁膜とを有し、
各セル領域において前記層間絶縁膜と前記半導体層の間に段差が存在し、
前記第１の主電極は、前記半導体基板上に順次形成された、第１の金属膜と、高強度金属膜と、第２の金属膜とを有し、
前記第１の金属膜及び前記第２の金属膜はＡｌを９５％以上有し、
前記高強度金属膜は、前記第２の金属膜よりも強度が高いことを特徴とする電力用半導体装置。 A semiconductor substrate having a first main surface and a second main surface facing each other;
A plurality of cell regions formed on the first main surface of the semiconductor substrate;
A first main electrode formed on the plurality of cell regions;
A second main electrode formed on the second main surface of the semiconductor substrate,
Each cell region has a semiconductor layer connected to the first main electrode, a control electrode, and an interlayer insulating film that covers the control electrode and insulates from the first main electrode,
In each cell region, there is a step between the interlayer insulating film and the semiconductor layer,
The first main electrode includes a first metal film, a high-strength metal film, and a second metal film, which are sequentially formed on the semiconductor substrate,
The first metal film and the second metal film have 95% or more of Al,
The power semiconductor device is characterized in that the high-strength metal film has higher strength than the second metal film. 前記高強度金属膜は、高融点金属又は高融点金属の導電性化合物からなることを特徴とする請求項１に記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein the high-strength metal film is made of a refractory metal or a conductive compound of a refractory metal. 前記第１の主電極は、前記第１の金属膜の下に設けられ、高融点金属又は高融点金属の導電性化合物からなるバリアメタルを更に有することを特徴とする請求項１又は２に記載の電力用半導体装置。   The first main electrode is further provided with a barrier metal formed under the first metal film and made of a refractory metal or a conductive compound of a refractory metal. Power semiconductor devices. 前記第１の金属膜は前記層間絶縁膜よりも厚く、
前記第２の金属膜の厚みは３μｍ以上であることを特徴とする請求項１〜３の何れか１項に記載の電力用半導体装置。 The first metal film is thicker than the interlayer insulating film,
4. The power semiconductor device according to claim 1, wherein a thickness of the second metal film is 3 μm or more. 5. 前記第１の金属膜の上面は平坦化されていることを特徴とする請求項１〜４の何れか１項に記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein an upper surface of the first metal film is flattened.
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014091545A1 (en) * 2012-12-10 2014-06-19 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP2014192351A (en) * 2013-03-27 2014-10-06 Mitsubishi Electric Corp Semiconductor device manufacturing method
JP2017011129A (en) * 2015-06-23 2017-01-12 三菱電機株式会社 Semiconductor device
JP2018022836A (en) * 2016-08-05 2018-02-08 トヨタ自動車株式会社 Semiconductor device
DE102018101392A1 (en) 2017-01-24 2018-07-26 Toyota Jidosha Kabushiki Kaisha SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
KR20180087172A (en) 2017-01-24 2018-08-01 도요타 지도샤（주） Semiconductor device and method of manufacturing the same
US10115798B2 (en) 2017-02-15 2018-10-30 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US10217859B2 (en) 2016-10-12 2019-02-26 Fuji Electric Co., Ltd. Semiconductor device
US10217832B2 (en) 2016-10-12 2019-02-26 Fuji Electric Co., Ltd. Semiconductor device
CN110858610A (en) * 2018-08-23 2020-03-03 三菱电机株式会社 Power semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003109984A (en) * 2001-09-28 2003-04-11 Seiko Epson Corp Ic-mounted oscillator
JP2005302941A (en) * 2004-04-09 2005-10-27 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device
JP2007142138A (en) * 2005-11-18 2007-06-07 Mitsubishi Electric Corp Semiconductor device
JP2007335432A (en) * 2006-06-12 2007-12-27 Toyota Central Res & Dev Lab Inc Semiconductor device and its fabrication process
JP2008112825A (en) * 2006-10-30 2008-05-15 Denso Corp Semiconductor device, and its manufacturing method
JP2010129585A (en) * 2008-11-25 2010-06-10 Toyota Motor Corp Method for manufacturing semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4231580B2 (en) * 1999-02-05 2009-03-04 株式会社日立製作所 Semiconductor device
JP4906184B2 (en) * 2000-11-17 2012-03-28 オンセミコンダクター・トレーディング・リミテッド Insulated gate type semiconductor device manufacturing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003109984A (en) * 2001-09-28 2003-04-11 Seiko Epson Corp Ic-mounted oscillator
JP2005302941A (en) * 2004-04-09 2005-10-27 Matsushita Electric Ind Co Ltd Manufacturing method of semiconductor device
JP2007142138A (en) * 2005-11-18 2007-06-07 Mitsubishi Electric Corp Semiconductor device
JP2007335432A (en) * 2006-06-12 2007-12-27 Toyota Central Res & Dev Lab Inc Semiconductor device and its fabrication process
JP2008112825A (en) * 2006-10-30 2008-05-15 Denso Corp Semiconductor device, and its manufacturing method
JP2010129585A (en) * 2008-11-25 2010-06-10 Toyota Motor Corp Method for manufacturing semiconductor device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014091545A1 (en) * 2012-12-10 2014-06-19 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP2014192351A (en) * 2013-03-27 2014-10-06 Mitsubishi Electric Corp Semiconductor device manufacturing method
JP2017011129A (en) * 2015-06-23 2017-01-12 三菱電機株式会社 Semiconductor device
US10347725B2 (en) 2015-06-23 2019-07-09 Mitsubishi Electric Corporation Semiconductor device that facilitates a reduction in the occurrences of cracking in a semiconductor layer accompanying thermal stress
JP2018022836A (en) * 2016-08-05 2018-02-08 トヨタ自動車株式会社 Semiconductor device
US10217859B2 (en) 2016-10-12 2019-02-26 Fuji Electric Co., Ltd. Semiconductor device
US10217832B2 (en) 2016-10-12 2019-02-26 Fuji Electric Co., Ltd. Semiconductor device
DE102018101392A1 (en) 2017-01-24 2018-07-26 Toyota Jidosha Kabushiki Kaisha SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
JP2018121050A (en) * 2017-01-24 2018-08-02 トヨタ自動車株式会社 Semiconductor device and method for manufacturing the same
KR101995933B1 (en) 2017-01-24 2019-07-03 도요타 지도샤（주） Semiconductor device and method of manufacturing the same
KR20180087172A (en) 2017-01-24 2018-08-01 도요타 지도샤（주） Semiconductor device and method of manufacturing the same
US10490638B2 (en) 2017-01-24 2019-11-26 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US10115798B2 (en) 2017-02-15 2018-10-30 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the same
CN110858610A (en) * 2018-08-23 2020-03-03 三菱电机株式会社 Power semiconductor device
US10971591B2 (en) 2018-08-23 2021-04-06 Mitsubishi Electric Corporation Power semiconductor device
CN110858610B (en) * 2018-08-23 2023-09-08 三菱电机株式会社 Semiconductor device for electric power
DE102019211754B4 (en) 2018-08-23 2024-08-01 Mitsubishi Electric Corporation Power semiconductor device

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