JP2011211042A - Electronic device - Google Patents

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JP2011211042A
JP2011211042A JP2010078644A JP2010078644A JP2011211042A JP 2011211042 A JP2011211042 A JP 2011211042A JP 2010078644 A JP2010078644 A JP 2010078644A JP 2010078644 A JP2010078644 A JP 2010078644A JP 2011211042 A JP2011211042 A JP 2011211042A
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electrode
semiconductor element
layer
semiconductor
solder
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JP5585167B2 (en
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Toshiya Akamatsu
俊也 赤松
Nobuhiro Imaizumi
延弘 今泉
Masataka Mizukoshi
正孝 水越
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]

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Abstract

PROBLEM TO BE SOLVED: To provide an electronic device that can obtain superior solder bonding without being affected by a shape before solder bonding.SOLUTION: The electronic device includes a first element 1; a columnar protrusion 5 formed on the first element 1 and in which an exposed surface is formed of an insulating material; and a plurality of first electrodes 3 formed around the columnar protrusion 5. The columnar protrusion 5 is set between a plurality of bump electrodes 14 formed on a second element 11 disposed opposite to the first element 1, and first electrodes 3 and bump electrodes 14 are connected via solder layers 4, 15.

Description

本発明は、電子デバイスに関する。   The present invention relates to an electronic device.

半導体素子（ＬＳＩ）のパッケージ基板への接合方法として、多端子化が可能なフリップチップ接合が主流となってきている。さらに、電子機器の小型化、高密度化に伴い、接続端子の微細化が進行している。接続端子の微細化が進むと、チップと回路基板の間のはんだ微細接合部において電流密度が増加する。この電流密度の増加によって、従来ではＬＳＩの内配線で問題であったエレクトロマイグレーションが、ＬＳＩとパッケージ基板とを接合する半田層においても生じるので、対策が必要になってくる。   As a method for bonding a semiconductor element (LSI) to a package substrate, flip chip bonding capable of increasing the number of terminals has become the mainstream. Furthermore, the miniaturization of connection terminals is progressing with the downsizing and high density of electronic devices. As the connection terminal becomes finer, the current density increases at the solder fine junction between the chip and the circuit board. Due to this increase in current density, electromigration, which has conventionally been a problem with LSI internal wiring, also occurs in the solder layer that joins the LSI and the package substrate, so a countermeasure is required.

エレクトロマイグレーション対策として、銅（Ｃｕ）ポストなどが用いられる。Ｃｕポストは電極上にめっきで形成されている。そして、Ｃｕポストの先端上とこれに対向するパッケージ基板側の電極上のそれぞれにはんだ（半田）が形成され、半田を加熱溶融してＣｕポストとパッケージ基板側の電極を接合する。   A copper (Cu) post or the like is used as an electromigration countermeasure. The Cu post is formed on the electrode by plating. Then, solder (solder) is formed on the tip of the Cu post and on the electrode on the package substrate opposite thereto, and the solder is heated and melted to join the Cu post and the electrode on the package substrate.

これにより、半導体チップと半導体チップ、または半導体チップとパッケージ基板との微細接合を行っている。
Ｃｕポストを突起電極として使用するためには、電極径が１００μｍ程度の場合、６０〜８０μｍの高さが必要になる。現在では、半導体素子の微細化が進行し、直径３０μｍ、ピッチ６０μｍ以下の接合体が検討され始めている。 Thus, fine bonding between the semiconductor chip and the semiconductor chip or between the semiconductor chip and the package substrate is performed.
In order to use the Cu post as a protruding electrode, when the electrode diameter is about 100 μm, a height of 60 to 80 μm is required. At present, the miniaturization of semiconductor elements has progressed, and a joined body having a diameter of 30 μm and a pitch of 60 μm or less has begun to be studied.

特開２００３−１９７６６５号公報JP 2003-197665 A 富士時報 Ｖｏｌ．７８、Ｎｏ．４、２００５年、３１６頁−３１８頁Fuji Times Vol. 78, no. 4, 2005, pages 316-318

Ｃｕポスト上に形成された半田層は、先端形状が半球状になっている。このため、Ｃｕポストを介して半導体素子同士を接続する場合に、一方の半導体素子上の半球状の半田と、他方の半導体素子上の半球状の半田を上下に位置合わせすると、凸同士で接触する。このため、半田を溶融させるまでに振動などで上下の半田に位置ずれが発生し、接合不良となりやすい。   The solder layer formed on the Cu post has a hemispherical tip shape. For this reason, when semiconductor elements are connected to each other via a Cu post, if the hemispherical solder on one semiconductor element and the hemispherical solder on the other semiconductor element are vertically aligned, they are in contact with each other. To do. For this reason, a position shift occurs in the upper and lower solders due to vibration or the like until the solder is melted, which tends to cause a bonding failure.

本発明の目的は、半田の接合前の形状に影響されずに半田接合を良好にするための電子デバイスを提供することにある。   An object of the present invention is to provide an electronic device for improving solder bonding without being affected by the shape before solder bonding.

１つの観点によれば、第１の素子と、前記第１の素子の上に形成され、少なくとも露出面が絶縁材から形成される柱状突起と、前記柱状突起の周囲に形成される複数の第１電極と、有する電子デバイスが提供される。
前述の一般的な説明および以下の詳細な説明は、典型例および説明のためのものであって、本発明を限定するためのものではない、と理解すべきである。 According to one aspect, a first element, a columnar protrusion formed on the first element and having at least an exposed surface formed of an insulating material, and a plurality of second protrusions formed around the columnar protrusion. An electronic device having one electrode is provided.
It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

本発明によれば、第１の素子の上に、少なくとも表面が絶縁材に覆われる柱状突起を形成したので、第１の素子に対向して配置される第２の素子上の複数の突起電極の間に嵌め込むことにより、第１の素子と第２の素子の位置ズレを防止することができる。
これにより、第１の素子と第２の素子にそれぞれ形成される電極の位置会わせを高い精度で行うことができ、電極間の半田接合を良好に行うことができる。 According to the present invention, since the columnar protrusion whose surface is covered with the insulating material is formed on the first element, the plurality of protruding electrodes on the second element disposed to face the first element. By fitting between the first element and the second element, positional deviation between the first element and the second element can be prevented.
As a result, the electrodes formed on the first element and the second element can be positioned with high accuracy, and solder bonding between the electrodes can be performed satisfactorily.

図１Ａは、第１実施形態に係る半導体装置における２つの半導体素子の接続方法を示す側面図、図１Ｂ、図１Ｃは、第１実施形態に係る半導体装置内の２つの半導体素子のそれぞれの半田層の配置を示す平面図である。FIG. 1A is a side view showing a method of connecting two semiconductor elements in the semiconductor device according to the first embodiment, and FIGS. 1B and 1C are solders of the two semiconductor elements in the semiconductor device according to the first embodiment. It is a top view which shows arrangement | positioning of a layer. 図２Ａ、図２Ｂは、第１実施形態に係る半導体装置に含まれる２つの半導体素子の接続方法を示す斜視図である。2A and 2B are perspective views illustrating a method for connecting two semiconductor elements included in the semiconductor device according to the first embodiment. 図３は、第１実施形態に係る半導体装置を示す側面図である。FIG. 3 is a side view showing the semiconductor device according to the first embodiment. 図４Ａ〜図４Ｅは、第１実施形態に係る半導体装置における第１の半導体素子の半田層及び突起の形成工程を示す断面図（その１〜５）である。4A to 4E are cross-sectional views (Nos. 1 to 5) showing the formation process of the solder layer and the protrusion of the first semiconductor element in the semiconductor device according to the first embodiment. 図４Ｆ〜図４Ｈは、第１実施形態に係る半導体装置における第１の半導体素子の半田層及び突起の形成工程を示す断面図（その６〜８）である。4F to 4H are cross-sectional views (Nos. 6 to 8) showing the formation process of the solder layer and the protrusion of the first semiconductor element in the semiconductor device according to the first embodiment. 図５Ａ〜図５Ｅは、第１実施形態に係る半導体装置における第２の半導体素子の突起電極の形成工程を示す断面図である。FIG. 5A to FIG. 5E are cross-sectional views illustrating the process of forming the protruding electrode of the second semiconductor element in the semiconductor device according to the first embodiment. 図６Ａ、図６Ｂは、第２実施形態に係る半導体装置内の第１、第２の半導体素子のそれぞれの半田層の配置を示す平面図である。6A and 6B are plan views showing the arrangement of the solder layers of the first and second semiconductor elements in the semiconductor device according to the second embodiment. 図７Ａ、図７Ｂは、第２実施形態に係る半導体装置における２つの半導体素子の接続方法を示す側面図である。7A and 7B are side views showing a method of connecting two semiconductor elements in the semiconductor device according to the second embodiment. 図８は、第２実施形態に係る半導体装置の第１、第２の半導体装置の接合部を示す平面図である。FIG. 8 is a plan view showing a joint portion of the first and second semiconductor devices of the semiconductor device according to the second embodiment. 図９Ａ〜図９Ｄは、第２実施形態に係る半導体装置における第１の半導体素子の柱状の突起の形成工程を示す断面図（その１〜４）である。9A to 9D are cross-sectional views (parts 1 to 4) showing a process of forming columnar protrusions of the first semiconductor element in the semiconductor device according to the second embodiment. 図９Ｅ〜図９Ｇは、第２実施形態に係る半導体装置における第１の半導体素子の柱状の突起の形成工程を示す断面図（その５〜７）である。FIGS. 9E to 9G are cross-sectional views (Nos. 5 to 7) showing a process of forming columnar protrusions of the first semiconductor element in the semiconductor device according to the second embodiment. 図９Ｈ〜図９Ｊは、第２実施形態に係る半導体装置における第１の半導体素子の柱状の突起の形成工程を示す断面図（その８〜１０）である。FIGS. 9H to 9J are cross-sectional views (Nos. 8 to 10) showing the process of forming the columnar protrusions of the first semiconductor element in the semiconductor device according to the second embodiment. 図１０Ａ〜図１０Ｄは、第２実施形態に係る半導体装置における第１の半導体素子の柱状の突起の形成工程を示す平面図である。FIG. 10A to FIG. 10D are plan views illustrating a process of forming columnar protrusions of the first semiconductor element in the semiconductor device according to the second embodiment. 図１１は、第２実施形態に係る半導体装置における第１の半導体素子上の柱状の突起の別の例を示す平面図である。FIG. 11 is a plan view showing another example of columnar protrusions on the first semiconductor element in the semiconductor device according to the second embodiment. 図１２は、第２実施形態に係る半導体装置における第１の半導体素子上の柱状の突起のさらに別の例を示す断面図である。FIG. 12 is a cross-sectional view showing still another example of columnar protrusions on the first semiconductor element in the semiconductor device according to the second embodiment. 図１３は、実施形態に係る半導体装置における第１の半導体素子の柱状の突起のさらに別の構造を示す側面図である。FIG. 13 is a side view showing still another structure of the columnar protrusions of the first semiconductor element in the semiconductor device according to the embodiment.

以下に、図面を参照して本発明の好ましい実施形態を説明する。図面において、同様の構成要素には同じ参照番号が付されている。
（第１の実施の形態）
図１Ａは本発明の第１実施形態に係る半導体装置となる第１の半導体素子１と第２の半導体装置１１の接続方法を示す側面図である。第１の半導体素子１は、第２の半導体素子１１に対して受け側の素子となる。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.
(First embodiment)
FIG. 1A is a side view showing a method of connecting the first semiconductor element 1 and the second semiconductor device 11 which are the semiconductor device according to the first embodiment of the present invention. The first semiconductor element 1 is an element on the receiving side with respect to the second semiconductor element 11.

図１Ａにおいて、半導体集積回路が形成された第１の半導体素子１の第１面上には、内部の半導体集積回路に電気的に接続される直径約３０μｍの複数の第１電極３がピッチ６
０μｍで形成されている。第１電極３は、図１Ｂに示すように、縦横に複数間隔をおいて配置されていて、その上面には半球状の第１の半田層４が接合されている。 In FIG. 1A, a plurality of first electrodes 3 having a diameter of about 30 μm and electrically connected to an internal semiconductor integrated circuit are formed on a first surface of a first semiconductor element 1 on which a semiconductor integrated circuit is formed.
It is formed with 0 μm. As shown in FIG. 1B, the first electrodes 3 are arranged at a plurality of intervals in the vertical and horizontal directions, and a hemispherical first solder layer 4 is bonded to the upper surface thereof.

さらに、第１電極３に囲まれる十字状の領域の中央には、位置ズレ抑制用突起５が柱状に形成されている。位置ズレ抑制用突起５の高さは、第１電極３及び第１の半田層４の厚さの合計よりも高く、且つ第１電極３と後述の第２電極１３及び突起電極１４の厚さの合計以下で、例えば約３０μｍ〜８０μｍに形成されている。位置ズレ抑制用突起５のうち少なくとも表面は絶縁材から形成されている。   Further, a misalignment suppressing protrusion 5 is formed in a columnar shape at the center of the cross-shaped region surrounded by the first electrode 3. The height of the misalignment suppressing protrusion 5 is higher than the total thickness of the first electrode 3 and the first solder layer 4, and the thickness of the first electrode 3, the second electrode 13 and the protruding electrode 14 described later. For example, about 30 μm to 80 μm. At least the surface of the misalignment suppressing protrusion 5 is made of an insulating material.

半導体集積回路が形成された第２の半導体素子１１の第１面上には、図１Ｃの平面図に示すように、第１の半導体素子１１の第１電極３に対向して配置される第２電極１３が形成され、第２電極１３上には約４０μｍ〜８０μｍの高さのＣｕの柱状の突起電極１４が形成されている。さらに、突起電極１４の先端面の上には、表面が半球状の第２の半田層１５が形成されている。
突起電極１４に囲まれた十字状の領域の上の空間は、位置ズレ抑制用突起５を嵌め込む突起嵌合領域１６となっている。 On the first surface of the second semiconductor element 11 on which the semiconductor integrated circuit is formed, as shown in the plan view of FIG. 1C, a first electrode disposed opposite to the first electrode 3 of the first semiconductor element 11 is arranged. Two electrodes 13 are formed, and a columnar protruding electrode 14 of Cu having a height of about 40 μm to 80 μm is formed on the second electrode 13. Further, a second solder layer 15 having a hemispherical surface is formed on the tip surface of the protruding electrode 14.
A space above the cross-shaped region surrounded by the protruding electrodes 14 is a protrusion fitting region 16 into which the positional deviation suppressing protrusion 5 is fitted.

なお、第１、第２電極３、１３は、Ｃｕ、Ｃｕ合金、Ｎｉ（ニッケル）などの金属層から形成されている。また、第１、第２の半田層４、１５は、鉛フリー半田材料、例えば融点が約２１７℃のＳｎＡｇＣｕ合金から形成されている。   In addition, the 1st, 2nd electrodes 3 and 13 are formed from metal layers, such as Cu, Cu alloy, and Ni (nickel). The first and second solder layers 4 and 15 are made of a lead-free solder material, for example, a SnAgCu alloy having a melting point of about 217 ° C.

第１、第２の半導体素子１、１１を接続する場合には、図２Ａの斜視図に示すように、第１の半導体素子１の第１面と第２の半導体素子１１の第１面を対向させ、さらに第２の半導体素子１１の突起電極１４上の第２の半田層１５を第１の半導体素子１の第１電極３上の第１の半田層４に重ねる。その際、図２Ｂの斜視図に示すように、第２の半導体素子１１上の突起電極１４に囲まれた領域に位置ズレ抑制用突起５を嵌め込む。それらの操作は、フリップチップボンダを用いて行われる。   When connecting the first and second semiconductor elements 1 and 11, as shown in the perspective view of FIG. 2A, the first surface of the first semiconductor element 1 and the first surface of the second semiconductor element 11 are connected to each other. Further, the second solder layer 15 on the protruding electrode 14 of the second semiconductor element 11 is overlapped with the first solder layer 4 on the first electrode 3 of the first semiconductor element 1. At that time, as shown in the perspective view of FIG. 2B, the misalignment suppressing protrusion 5 is fitted into a region surrounded by the protruding electrode 14 on the second semiconductor element 11. These operations are performed using a flip chip bonder.

その後に、第１、第２の半田層４、１５を重ねた状態で、第１、第２の半導体素子１、１１をリフロー炉内に入れて窒素雰囲気で第１、第２の半田層４、１５を融点より例えば約２０℃高い温度で加熱、溶融し、その後に常温に戻す。これにより、図３の側面図に示すように、第２電極１３上の突起電極１４と第１電極３は、第１、第２の半田層４、１５に接合され、電気的に導通する。
以上により、第１、第２の半導体素子１、１１を有する半導体装置１０が形成される。 Thereafter, with the first and second solder layers 4 and 15 being stacked, the first and second semiconductor elements 1 and 11 are placed in a reflow furnace and the first and second solder layers 4 are placed in a nitrogen atmosphere. 15 is heated and melted at a temperature, for example, about 20 ° C. higher than the melting point, and then returned to room temperature. Thereby, as shown in the side view of FIG. 3, the protruding electrode 14 and the first electrode 3 on the second electrode 13 are joined to the first and second solder layers 4 and 15 and are electrically conducted.
Thus, the semiconductor device 10 having the first and second semiconductor elements 1 and 11 is formed.

上記のように本実施形態によれば、表面が半球状の第１、第２の半田層４、１５を重ね合わせた状態で、位置ズレ抑制用突起５によって周囲の突起電極１４の横方向の移動が規制されるので、第１の半導体素子１に対して第２の半導体素子１１が横方向に位置ズレしない。また、位置ズレ抑制用突起５は、突起電極１４を垂直方向に移動させる場合のガイドとなり、第１の半導体素子１に対して第２の半導体素子１１の傾きを抑制できる。
また、第１、第２の半田層４、１５が溶融により流れる際にも、その横方向の位置ズレの規制により、第１電極３と突起電極１５の対向位置がずれなくなる。
従って、位置ズレ抑制用突起５を第１の半導体素子１上に形成することにより、垂直方向及び水平方向のズレを緩和することができる。 As described above, according to the present embodiment, in the state where the first and second solder layers 4 and 15 having hemispherical surfaces are superposed, the lateral displacement of the surrounding protruding electrodes 14 is caused by the positional deviation suppressing protrusions 5. Since the movement is restricted, the second semiconductor element 11 does not shift in the lateral direction with respect to the first semiconductor element 1. Further, the positional deviation suppressing protrusion 5 serves as a guide when the protruding electrode 14 is moved in the vertical direction, and can suppress the inclination of the second semiconductor element 11 with respect to the first semiconductor element 1.
Further, even when the first and second solder layers 4 and 15 flow due to melting, the opposed positions of the first electrode 3 and the protruding electrode 15 do not shift due to the regulation of the positional deviation in the lateral direction.
Therefore, by forming the misalignment suppressing protrusion 5 on the first semiconductor element 1, the vertical and horizontal misalignments can be reduced.

本実施形態の半導体装置１０の接合の不良確率について実験を行ったところ、第１の半導体素子１と第２の半導体素子１１の位置ズレ不良は無く、第１の半田層４と第２の半田層１５の接合は良好であった。
これに対し、比較例として、位置ズレ抑制用突起５の無い従来品を用いて第１の半田層４と第２の半田層１５を接合したところ、約１０％の確率で位置ずれ不良が発生した。こ
の場合、電極直径の１／２以上のズレが生じた状態を位置ズレの不良とした。 When an experiment was conducted on the bonding failure probability of the semiconductor device 10 of this embodiment, there was no misalignment between the first semiconductor element 1 and the second semiconductor element 11, and the first solder layer 4 and the second solder. The bonding of layer 15 was good.
On the other hand, as a comparative example, when the first solder layer 4 and the second solder layer 15 are joined using a conventional product without the misalignment suppressing protrusion 5, a misalignment failure occurs with a probability of about 10%. did. In this case, a state in which a deviation of 1/2 or more of the electrode diameter occurred was regarded as a positional deviation defect.

これらの結果、第１、第２の半田層４、１５の表面が半球状に湾曲していても第１電極３と突起電極１５を１対１で良好に接続することができ、従来よりも位置ずれ不良確率を減らすことが可能になった。これにより、薄いチップ状の半導体素子のように反りの大きい半導体素子についても接合不良を低減できるようになる。   As a result, even if the surfaces of the first and second solder layers 4 and 15 are hemispherically curved, the first electrode 3 and the protruding electrode 15 can be connected in a good one-to-one relationship. It has become possible to reduce the probability of misalignment. As a result, it is possible to reduce bonding defects even for a semiconductor element having a large warp such as a thin chip-like semiconductor element.

次に、図４Ａ〜図４Ｈを参照し、第１の半導体装置１の第１電極３の上に第１の半田層４を形成し、さらに位置ズレ抑制用突起５を形成する工程を説明する。
まず、図４Ａに示すように、第１の半導体素子１の上面と第１電極３の上にシード層６を形成する。シード層６として、例えば、厚さ約５０ｎｍのＣｒ（クロム）層と厚さ約１００ｎｍのＣｕ層を順にスパッタにより形成する。この場合、第１の半導体素子１は、分離前の６インチのウエーハに隣接して複数形成された状態にある。 Next, with reference to FIGS. 4A to 4H, a process of forming the first solder layer 4 on the first electrode 3 of the first semiconductor device 1 and further forming the misalignment suppressing protrusion 5 will be described. .
First, as shown in FIG. 4A, a seed layer 6 is formed on the upper surface of the first semiconductor element 1 and the first electrode 3. As the seed layer 6, for example, a Cr (chromium) layer having a thickness of about 50 nm and a Cu layer having a thickness of about 100 nm are sequentially formed by sputtering. In this case, a plurality of first semiconductor elements 1 are formed adjacent to the 6-inch wafer before separation.

次に、図４Ｂに示すように、シード層６上にドライレジストフィルム７をラミネート法で形成し、これを露光、現像等することにより、複数の第１電極３のそれぞれの上に開口部７ａを有する。   Next, as shown in FIG. 4B, a dry resist film 7 is formed on the seed layer 6 by a laminating method, and this is exposed, developed, and the like, whereby openings 7a are formed on each of the plurality of first electrodes 3. Have

次に、図４Ｃに示すように、ドライレジストフィルム７の開口部７ａを通して第１シード層６上の開口部７ａ内に、電解めっき法によりＣｕ層４ａを約２μｍ、Ｎｉ層４ｂを約３μｍ、ＳｎＡｇ（スズ銀）層４ｃを約１２μｍの厚さに順に形成する。この場合、シード層６は電解めっき用電極として使用する。   Next, as shown in FIG. 4C, the Cu layer 4a is about 2 μm and the Ni layer 4b is about 3 μm by electrolytic plating into the opening 7a on the first seed layer 6 through the opening 7a of the dry resist film 7. An SnAg (tin silver) layer 4c is sequentially formed to a thickness of about 12 μm. In this case, the seed layer 6 is used as an electrode for electrolytic plating.

ドライレジストフィルム７を除去した後に、図４Ｄに示すように、ＳｎＡｇ層４ｃをマスクにして、シード層６をエッチングする。この場合、シード層６のＣｕ層を硫酸、過酸化水素を含むエッチャントによりエッチングし、さらに、シード６のＣｒ層をフェリシアン化カリウム含有のエッチャントによりエッチングする。
続いて、図４Ｅに示すように、ＳｎＡｇ層４ｃを加熱溶融して上面を曲面にし、ＳｎＡｇ層４ｃを第１の半田層４とする。 After the dry resist film 7 is removed, the seed layer 6 is etched using the SnAg layer 4c as a mask, as shown in FIG. 4D. In this case, the Cu layer of the seed layer 6 is etched with an etchant containing sulfuric acid and hydrogen peroxide, and the Cr layer of the seed 6 is etched with an etchant containing potassium ferricyanide.
Subsequently, as shown in FIG. 4E, the SnAg layer 4 c is heated and melted to make the upper surface curved, and the SnAg layer 4 c is used as the first solder layer 4.

次に、図４Ｆに示すように、第１の半導体装置１が形成されたウエーハの全面に感光性エポキシ樹脂５ａをスピンコートにより約５０μｍの厚さに塗布する。その後に、図４Ｇに示すように、感光性エポキシ樹脂５ａの上にガラスマスク８を配置した状態で、ガラスマスク８を通して感光性のエポキシ樹脂５ａを露光し、さらに、現像等を行う。   Next, as shown in FIG. 4F, a photosensitive epoxy resin 5a is applied to the entire surface of the wafer on which the first semiconductor device 1 is formed to a thickness of about 50 μm by spin coating. Thereafter, as shown in FIG. 4G, with the glass mask 8 disposed on the photosensitive epoxy resin 5a, the photosensitive epoxy resin 5a is exposed through the glass mask 8, and development or the like is further performed.

これにより、図４Ｈに示すように、複数の第１電極３の間の十字状の領域の中央にエポキシ樹脂５ａを円柱状に残す。円柱状のエポキシ樹脂５ａは、例えば直径が５０μｍ、ピッチが１２０μｍの密度で形成され、上記の位置ズレ抑制用突起５として使用される。   As a result, as shown in FIG. 4H, the epoxy resin 5a is left in a columnar shape at the center of the cross-shaped region between the plurality of first electrodes 3. The cylindrical epoxy resin 5a is formed with a density of, for example, a diameter of 50 μm and a pitch of 120 μm, and is used as the above-described misregistration suppression protrusion 5.

その後に、第１の半導体素子１が複数形成されたウエーハを切断し、チップ状に分離する。第１の半導体素子１のチップサイズは、例えば１０ｍｍ×１０ｍｍの平面形状を有している。
以上の工程によれば、第１の半導体素子１上において、複数の第１電極３に挟まれる領域の位置ズレ抑制用突起５は、絶縁性樹脂のパターニングにより形成しているので、複雑な工程を必要としない。 Thereafter, the wafer on which a plurality of first semiconductor elements 1 are formed is cut and separated into chips. The chip size of the first semiconductor element 1 has, for example, a planar shape of 10 mm × 10 mm.
According to the above process, since the positional deviation suppression protrusion 5 in the region sandwiched between the plurality of first electrodes 3 on the first semiconductor element 1 is formed by patterning the insulating resin, it is a complicated process. Do not need.

次に、図５Ａ〜図５Ｅに示すように、第２の半導体装置１１の第２電極１３の上に突起電極１４、第２の半田層１５を形成する工程を説明する。
まず、図５Ａに示す構造を形成するまでの工程について説明する。
第２の半導体素子１１の上面と第２電極１３の上にシード層１７を形成する。シード層
１７として、例えば、厚さ約５０ｎｍのＣｒ層と厚さ約５００ｎｍのＣｕ層を順にスパッタにより形成する。この場合、第２の半導体素子１１は、分離前の６インチのウエーハに隣接して複数形成された状態にある。 Next, as shown in FIGS. 5A to 5E, a process of forming the protruding electrode 14 and the second solder layer 15 on the second electrode 13 of the second semiconductor device 11 will be described.
First, steps required until a structure shown in FIG. 5A is formed will be described.
A seed layer 17 is formed on the upper surface of the second semiconductor element 11 and the second electrode 13. As the seed layer 17, for example, a Cr layer having a thickness of about 50 nm and a Cu layer having a thickness of about 500 nm are sequentially formed by sputtering. In this case, a plurality of second semiconductor elements 11 are formed adjacent to the 6-inch wafer before separation.

続いて、シード層１７上にドライレジストフィルム１８をラミネート法で形成し、これを露光、現像等することにより、複数の第２電極１３の上方に開口部１８ａを有する。   Subsequently, a dry resist film 18 is formed on the seed layer 17 by a laminating method, and this is exposed, developed, and the like, thereby having openings 18 a above the plurality of second electrodes 13.

次に、図５Ｂに示すように、ドライレジストフィルム１８の開口部１８ａを通してシード層１７上に、電解めっき法により厚さ約５０μｍのＣｕの突起電極１４、厚さ５μｍのＮｉ層１５ａを順に形成する。この場合、シード層１７は電解めっき用電極として使用する。
続いて、図５Ｃに示すように、開口部１８ａ内のＮｉ層１５ａの上に厚さ１０μｍのＳｎ層１５ｂを電解めっきにより形成し、ドライレジストフィルム１８の上に突出させる。 Next, as shown in FIG. 5B, a Cu protruding electrode 14 having a thickness of about 50 μm and a Ni layer 15a having a thickness of 5 μm are sequentially formed on the seed layer 17 through the opening 18a of the dry resist film 18 by an electrolytic plating method. To do. In this case, the seed layer 17 is used as an electrode for electrolytic plating.
Subsequently, as shown in FIG. 5C, a 10 μm-thick Sn layer 15 b is formed on the Ni layer 15 a in the opening 18 a by electrolytic plating, and is projected on the dry resist film 18.

ドライレジストフィルム１８を除去した後に、図５Ｄに示すように、Ｓｎ層１５ｂをマスクにしてシード層１７を除去する。この場合、シード層１７のＣｕ層を硫酸、過酸化水素を含むエッチャントによりエッチングし、さらにシード１７のＣｒ層をフェリシアン化カリウム含有のエッチャントによりエッチングする。
この後に、図５Ｅに示すように、Ｓｎ層１５ｂを加熱溶融した後に常温に戻すことによりＳｎ層１５ａを第２の半田層１５として使用する。この場合、第２の半田層１５の露出面は曲面となる。 After the dry resist film 18 is removed, as shown in FIG. 5D, the seed layer 17 is removed using the Sn layer 15b as a mask. In this case, the Cu layer of the seed layer 17 is etched with an etchant containing sulfuric acid and hydrogen peroxide, and the Cr layer of the seed 17 is further etched with an etchant containing potassium ferricyanide.
Thereafter, as shown in FIG. 5E, the Sn layer 15a is used as the second solder layer 15 by heating and melting the Sn layer 15b and then returning to the normal temperature. In this case, the exposed surface of the second solder layer 15 is a curved surface.

その後に、第２の半導体素子１１が複数形成されたウエーハを切断し、チップ状に分離する。第２の半導体素子１１のチップサイズは、例えば７ｍｍ×５ｍｍの平面形状を有している。   Thereafter, the wafer on which a plurality of second semiconductor elements 11 are formed is cut and separated into chips. The chip size of the second semiconductor element 11 has, for example, a planar shape of 7 mm × 5 mm.

（第２の実施の形態）
図６Ａ、図６Ｂは、本発明の第２実施形態に係る半導体装置を形成するための２つの半導体素子を示す平面図であり、図１、図１Ｂ、図１Ｃと同じ符号は同じ要素を示している。
図６Ａに示す第１の半導体素子３１は、図６Ｂに示す第２の半導体素子１１に接続する際には受け側の素子となる。 (Second Embodiment)
6A and 6B are plan views showing two semiconductor elements for forming a semiconductor device according to the second embodiment of the present invention. The same reference numerals as those in FIGS. 1, 1B, and 1C denote the same elements. ing.
The first semiconductor element 31 shown in FIG. 6A becomes a receiving element when connected to the second semiconductor element 11 shown in FIG. 6B.

図６Ａに示す第１の半導体素子３１の第１面上には、図６Ｂに示す第２の半導体装置１１上の突起電極１４が嵌め込まれる複数の突起電極配置領域３０が区画されて、突起電極配置領域３０の間には十字状の領域が形成される。第１の半導体素子３１の第１面上における縦方向と横方向に配置される複数の十字状の領域の中央には、１つおきに柱状の位置ズレ抑制用突起３２が形成されている。   On the first surface of the first semiconductor element 31 shown in FIG. 6A, a plurality of protruding electrode arrangement regions 30 into which the protruding electrodes 14 on the second semiconductor device 11 shown in FIG. A cross-shaped area is formed between the arrangement areas 30. In the center of the plurality of cross-shaped regions arranged in the vertical direction and the horizontal direction on the first surface of the first semiconductor element 31, every other columnar positional displacement suppression protrusion 32 is formed.

位置ズレ抑制用突起３２は、例えば四角柱の形状を有し、少なくとも表面は絶縁材から形成されている。その絶縁材は僅かな弾性を有するか、変形が可能な材料であることが好ましい。位置ズレ抑制用突起３２が四角柱状の場合には、その４つの側面が周囲の突起電極配置領域３０に対向する配置にされる。   The misalignment suppressing protrusion 32 has, for example, a quadrangular prism shape, and at least the surface is formed of an insulating material. The insulating material is preferably a material having slight elasticity or being deformable. When the misalignment suppressing protrusion 32 has a quadrangular prism shape, its four side surfaces are arranged to face the surrounding protruding electrode arrangement region 30.

四角柱状の位置ズレ抑制用突起３２の４つのそれぞれの側面の上から第１の半導体素子３１の第１面上には、図７Ａに示すように第３電極３３が形成されている。第３電極３３は、第１の半導体素子３１内部の半導体集積回路（不図示）に接続される。
また、第３電極３３の表面には、図６Ａに示すように、突起電極配置領域３０の縁に重なる第３の半田層３４が形成されている。
なお、第１の半導体素子３１の第１面には、位置ズレ抑制用突起３２を露出する開口部
を有する絶縁膜（不図示）が形成されている。 As shown in FIG. 7A, the third electrode 33 is formed on the first surface of the first semiconductor element 31 from the four side surfaces of the quadratic columnar misregistration suppressing protrusion 32. The third electrode 33 is connected to a semiconductor integrated circuit (not shown) inside the first semiconductor element 31.
Further, as shown in FIG. 6A, a third solder layer 34 is formed on the surface of the third electrode 33 so as to overlap the edge of the protruding electrode arrangement region 30.
Note that an insulating film (not shown) having an opening exposing the misalignment suppressing protrusion 32 is formed on the first surface of the first semiconductor element 31.

一方、図６Ｂに示す第２の半導体素子１１の第１面上には、第１実施形態と同様に、内部の半導体集積回路に接続される第２電極１３が間隔をおいて縦横に複数形成され、その上にはＣｕから形成される突起電極１４が形成されている。第２電極１３の直径は約３０μｍで、６０μｍのピッチで形成されている。また、第２の半導体素子１１の第１面は、第２電極１３を露出する絶縁膜（不図示）で覆われている。
なお、突起電極１４の上端には半田層が形成されないことが構造的に第１実施形態とは異なる。 On the other hand, on the first surface of the second semiconductor element 11 shown in FIG. 6B, as in the first embodiment, a plurality of second electrodes 13 connected to the internal semiconductor integrated circuit are formed vertically and horizontally at intervals. On top of this, a protruding electrode 14 made of Cu is formed. The diameter of the second electrode 13 is about 30 μm and is formed at a pitch of 60 μm. The first surface of the second semiconductor element 11 is covered with an insulating film (not shown) that exposes the second electrode 13.
Note that the bump electrode 14 is structurally different from the first embodiment in that a solder layer is not formed on the upper end.

次に、第１の半導体素子３１の第３電極３３と第２の半導体素子１１の突起電極１４の接続方法を説明する。
まず、図７Ａに示すように、第１の半導体素子１と第２の半導体素子３１の第１面同士を対向させた状態で、第２の半導体素子１１上の複数の突起電極１４の間に第１の半導体素子１１上の位置ズレ抑制用突起３２を嵌め合わせる。続いて、そのような状態から、第２の半導体素子３１を下降させる。 Next, a method for connecting the third electrode 33 of the first semiconductor element 31 and the protruding electrode 14 of the second semiconductor element 11 will be described.
First, as shown in FIG. 7A, in a state where the first surfaces of the first semiconductor element 1 and the second semiconductor element 31 are opposed to each other, between the plurality of protruding electrodes 14 on the second semiconductor element 11. The misalignment suppressing protrusion 32 on the first semiconductor element 11 is fitted. Subsequently, the second semiconductor element 31 is lowered from such a state.

これにより、図７Ｂに示すように、第１の半導体素子３１上の位置ズレ抑制用突起３２が第２の半導体素子１１上の突起電極１４の間に嵌め込まれるので、位置ズレ抑制用突起３２の側面の第３の半田層３４は突起電極１４の側面に１対１で接触する。この場合、位置ズレ抑制用突起３２は自身の弾性により変形する。以上の操作は、フリップチップボンダを用いて行われる。   As a result, as shown in FIG. 7B, the positional deviation suppressing protrusion 32 on the first semiconductor element 31 is fitted between the protruding electrodes 14 on the second semiconductor element 11. The third solder layer 34 on the side surface contacts the side surface of the protruding electrode 14 on a one-to-one basis. In this case, the positional deviation suppression protrusion 32 is deformed by its own elasticity. The above operation is performed using a flip chip bonder.

その後に、突起電極１４と第３の半田層３４を接触させた状態で、第１、第２の半導体素子１、１１をリフロー炉内に入れて窒素雰囲気に置き、第３の半田層３４をその融点より高い温度で加熱、溶融し、その後に常温に戻す。これにより、図８の拡大平面図に示すように、第２電極１３上の突起電極１４の側部と第３電極３３は、第３の半田層３４を介して互いに接合され、電気的に導通する。
以上により、第１、第２の半導体素子１、３１を有する半導体装置２０が形成される。なお、第３電極３３、第３の半田層３４は電解めっき法により形成されてもよい。 Thereafter, with the protruding electrode 14 and the third solder layer 34 in contact with each other, the first and second semiconductor elements 1 and 11 are placed in a reflow furnace and placed in a nitrogen atmosphere, and the third solder layer 34 is formed. It is heated and melted at a temperature higher than its melting point, and then returned to room temperature. Thus, as shown in the enlarged plan view of FIG. 8, the side portion of the protruding electrode 14 on the second electrode 13 and the third electrode 33 are joined to each other via the third solder layer 34 and are electrically conductive. To do.
Thus, the semiconductor device 20 having the first and second semiconductor elements 1 and 31 is formed. The third electrode 33 and the third solder layer 34 may be formed by an electrolytic plating method.

上記のように本実施形態によれば、第１の半導体素子３１上に形成した位置ズレ抑制用突起３２を第２の半導体素子１１の突起電極１４で囲まれた領域に嵌め込むようにしている。これにより、位置ズレ抑制用突起３２の４つの側面にそれぞれ形成された第３電極３３を第３の半田層３４により突起電極１４の側面に接合することができる。しかも、突起電極１４の側面で半田接合する際に、位置ズレ抑制用突起３２の４つの角で半田層３４の飛び出しが防止されるので、突起電極１４同士のショート不良を抑制することができる。   As described above, according to the present embodiment, the misalignment suppressing protrusion 32 formed on the first semiconductor element 31 is fitted into the region surrounded by the protruding electrode 14 of the second semiconductor element 11. Accordingly, the third electrodes 33 formed on the four side surfaces of the positional deviation suppressing protrusion 32 can be joined to the side surfaces of the protruding electrode 14 by the third solder layer 34. In addition, when solder bonding is performed on the side surfaces of the protruding electrodes 14, the solder layer 34 is prevented from jumping out at the four corners of the misalignment suppressing protrusions 32, so that short-circuit defects between the protruding electrodes 14 can be suppressed.

また、複数の突起電極１４の間の領域に位置ズレ抑制用突起３２を嵌め込むだけで、第１、第２の半導体素子３１，１１の位置合わせが可能になる。しかも、位置ズレ抑制用突起３２により、その周囲の突起電極１４の横方向の移動が規制されるので、第１の半導体素子３１に対して第２の半導体素子１１が横方向に位置ズレしない。また、位置ズレ抑制用突起３２は、突起電極１４を垂直方向に移動させる場合のガイドとなり、第１の半導体素子３１に対して第２の半導体素子１１の傾きを抑制できる。
従って、位置ズレ抑制用突起３２を第１の半導体素子３１上に形成することにより、垂直方向及び水平方向のズレを緩和することができる。 Further, the first and second semiconductor elements 31 and 11 can be aligned only by fitting the misalignment suppressing protrusion 32 into the region between the plurality of protruding electrodes 14. In addition, the lateral displacement of the projecting electrode 14 around it is restricted by the misalignment suppressing projection 32, so that the second semiconductor element 11 is not misaligned laterally with respect to the first semiconductor element 31. Further, the positional deviation suppressing protrusion 32 serves as a guide when the protruding electrode 14 is moved in the vertical direction, and can suppress the inclination of the second semiconductor element 11 with respect to the first semiconductor element 31.
Therefore, by forming the positional deviation suppressing protrusion 32 on the first semiconductor element 31, the vertical and horizontal deviations can be reduced.

本実施形態の半導体装置２０の接合の不良確率について実験を行ったところ、第１の半導体素子３１と第２の半導体素子１１の位置ズレ不良は無く、第３の半田層３４と突起電極１４の接合は良好であった。   When an experiment was conducted on the bonding failure probability of the semiconductor device 20 of the present embodiment, there was no misalignment between the first semiconductor element 31 and the second semiconductor element 11, and the third solder layer 34 and the protruding electrode 14 Bonding was good.

これに対し、第１実施形態に示したと同様に、比較として、位置ズレ抑制用突起３２の無い従来品を用いて第１の半田層４と第２の半田層１５を接合したところ、約１０％の確率で位置ずれ不良が発生した。これらの結果、本実施形態に係る半導体装置２０によれば、従来よりも位置ずれ不良確率を抑制することが可能となった。これにより、薄いチップ状の半導体素子のように反りの大きい半導体素子についても接合不良を低減できる。   On the other hand, as shown in the first embodiment, as a comparison, when the first solder layer 4 and the second solder layer 15 are joined using a conventional product without the misalignment suppressing protrusion 32, about 10 is obtained. Misalignment occurred with a probability of%. As a result, according to the semiconductor device 20 according to the present embodiment, it is possible to suppress the misalignment failure probability as compared with the conventional case. Thereby, it is possible to reduce bonding defects even for a semiconductor element having a large warp such as a thin chip-shaped semiconductor element.

以下に、図９Ａ〜図９Ｈの側断面図、及び図１０Ａ〜図１０Ｄの上面図を参照し、第１の半導体装置３１の位置ズレ抑制用突起３２を形成する工程を説明する。
次に、図９Ａに示す構造を形成するまでの工程を説明する。
まず、上記の第３電極３３の下部となる接続電極３３ａが形成された第１の半導体素子３１を用意する。そして、第１の半導体素子３１の第１面の全面に熱硬化性樹脂、例えば感光性エポキシ樹脂３６をスピンコート法により例えば約５０μｍの厚さに塗布する。この場合、第１の半導体素子３１は、分離前の６インチのウエーハに隣接して複数形成された状態にある。 Hereinafter, a process of forming the misalignment suppressing protrusion 32 of the first semiconductor device 31 will be described with reference to side sectional views of FIGS. 9A to 9H and top views of FIGS. 10A to 10D.
Next, steps required until a structure shown in FIG. 9A is formed will be described.
First, the first semiconductor element 31 in which the connection electrode 33a to be the lower part of the third electrode 33 is formed is prepared. Then, a thermosetting resin, for example, a photosensitive epoxy resin 36 is applied to the entire first surface of the first semiconductor element 31 by a spin coating method to a thickness of, for example, about 50 μm. In this case, a plurality of first semiconductor elements 31 are formed adjacent to the 6-inch wafer before separation.

なお、接続電極３３ａは、図６Ａに示したように、互いに隣り合う突起電極配置領域３０の間の領域内で、突起電極配置領域３０に最も近い位置に接近して形成されている。
次に、図６Ｂに示すように、感光性エポキシ樹脂３６の上にガラスマスク３７を配置した状態で、ガラスマスク３７を通して感光性のエポキシ樹脂３６を露光し、さらに、現像等を行った後に、ポストベークにより硬化させる。 As shown in FIG. 6A, the connection electrode 33a is formed close to the position closest to the bump electrode arrangement region 30 in the region between the bump electrode arrangement regions 30 adjacent to each other.
Next, as shown in FIG. 6B, the photosensitive epoxy resin 36 is exposed through the glass mask 37 in a state where the glass mask 37 is disposed on the photosensitive epoxy resin 36, and further developed and the like. Cure by post-baking.

これにより、図９Ｃに示すように、互いに隣り合う４つの突起電極配置領域３０の間に四角柱状の位置ズレ抑制用突起３２を形成する。位置ズレ抑制用突起３２は、上記のように４０μｍ×４０μｍの平面形状を有し、図６Ａに示すような配置となり、４つの側面の根本から接続電極３３ａの一部を露出させる大きさになっている。   As a result, as shown in FIG. 9C, a quadratic prism-shaped misregistration suppressing protrusion 32 is formed between the four protruding electrode arrangement regions 30 adjacent to each other. As described above, the misregistration suppressing protrusion 32 has a planar shape of 40 μm × 40 μm, and is arranged as shown in FIG. 6A, and has a size that exposes a part of the connection electrode 33a from the roots of the four side surfaces. ing.

次に、図９Ｄに示すように、第１の半導体装置３１の上にフォトレジスト３８を塗布する。その後に、図９Ｅに示すように、ガラスマスク３９を使用してフォトレジスト３８を露光、現像することにより、図９Ｆの側断面図と図１０Ａの平面図に示すように、位置ズレ抑制用突起３２の４つの側面の外側に、接続電極３３ａを露出する開口部３８ａを形成する。開口部３８ａの平面形状は四角形であり、そのうち位置ズレ抑制用突起３２の側面に平行な２辺を約２０μｍ、残りの２辺を１０μｍの大きさとする。   Next, as shown in FIG. 9D, a photoresist 38 is applied on the first semiconductor device 31. Thereafter, as shown in FIG. 9E, by exposing and developing the photoresist 38 using the glass mask 39, as shown in the side sectional view of FIG. 9F and the plan view of FIG. Openings 38a exposing the connection electrodes 33a are formed outside the four side surfaces of 32. The planar shape of the opening 38a is a quadrangle, of which two sides parallel to the side surface of the misalignment suppressing projection 32 are about 20 μm and the remaining two sides are about 10 μm.

次に、図９Ｇと図１０Ｂに示すように、無電解めっき法により、開口部３８ａのうち位置ズレ抑制用突起３２の４つの側面上に厚さ５μｍのＣｕ層４０を形成する。続いて、図９Ｈと図１０Ｃに示すように、無電解めっき法により、開口部３８ａ内でＣｕ層４０の上に厚さ５μｍのＳｎ層４１を形成する。   Next, as shown in FIGS. 9G and 10B, a Cu layer 40 having a thickness of 5 μm is formed on the four side surfaces of the misregistration suppression protrusion 32 in the opening 38a by electroless plating. Subsequently, as shown in FIGS. 9H and 10C, an Sn layer 41 having a thickness of 5 μm is formed on the Cu layer 40 in the opening 38a by electroless plating.

次に、図９Ｉに示すように、フォトレジスト３８を溶剤により除去する。さらに、図９Ｊと図１０Ｄに示すように、Ｓｎ層４０を加熱溶融し、さらに冷却する。これにより、Ｓｎ層４０の表面が曲面になる。この場合、Ｃｕ層４０は、図７Ａに示した第３電極３３として使用され、Ｓｎ層４１は、図７Ａに示した第３の半田層３４として使用される。   Next, as shown in FIG. 9I, the photoresist 38 is removed with a solvent. Further, as shown in FIGS. 9J and 10D, the Sn layer 40 is heated and melted and further cooled. Thereby, the surface of the Sn layer 40 becomes a curved surface. In this case, the Cu layer 40 is used as the third electrode 33 shown in FIG. 7A, and the Sn layer 41 is used as the third solder layer 34 shown in FIG. 7A.

そのように、柱状の位置ズレ抑制用突起３２の側面に第３電極３３、第３の半田層３４を形成することにより、第３電極３３を局所的に高密度化し、電極が配置されない領域を従来よりも広くすることができる。
このため、第１の半導体素子３１の第１面上では、図６Ａに示すように、第３電極３３に接続される配線４３の形成領域が広がるので、配線４３を第３電極３３の４列目まで接続することができ、配線４３の配置設計が容易になる。なお、図１Ｂに示す第１の半導体
装置１上では、第１電極３の２列目まで配線を形成することができる。 As described above, by forming the third electrode 33 and the third solder layer 34 on the side surface of the columnar misregistration suppressing protrusion 32, the third electrode 33 is locally densified, and an area where the electrode is not disposed is formed. It can be made wider than before.
Therefore, on the first surface of the first semiconductor element 31, as shown in FIG. 6A, the formation region of the wiring 43 connected to the third electrode 33 is widened. It is possible to connect to the eyes, and the layout design of the wiring 43 is facilitated. Note that on the first semiconductor device 1 shown in FIG. 1B, wiring can be formed up to the second column of the first electrode 3.

ところで、上記の位置ズレ抑制用突起３２は、四角柱状に形成しているが、円柱状、多角形柱状、その他の柱状に形成してもよい。例えば、図１１に示すように、露光、現像により上面を十字形状にパターニングしてもよい。この場合、位置ズレ抑制用突起３２の側面の凹部が突起電極配置領域３０に最も接近するように配置し、その凹部上に形成される第３電極３３と第３の半田層３４を第２の半導体素子１側の複数の突起電極１４の間に接続するように形成する。   By the way, the above-described misregistration suppression protrusion 32 is formed in a quadrangular column shape, but may be formed in a columnar shape, a polygonal column shape, or other column shapes. For example, as shown in FIG. 11, the upper surface may be patterned into a cross shape by exposure and development. In this case, the concave portion on the side surface of the misregistration suppressing projection 32 is arranged so as to be closest to the protruding electrode arrangement region 30, and the third electrode 33 and the third solder layer 34 formed on the concave portion are arranged as the second electrode. It is formed so as to be connected between the plurality of protruding electrodes 14 on the semiconductor element 1 side.

ところで、上記した実施形態において、位置ズレ抑制用突起５，３４を樹脂により形成したが、図１２に示すように、その中心をＣｕなどの金属ポスト５ｙにより形成し、その表面を絶縁層５ｘでコーティングする構造を採用してもよい。これにより、位置ズレ抑制用突起５，３４が強固になる。この場合、絶縁層５ｘによって突起電極１４間のショートが防止される。また、その他の構造として、図１２に示した金属ポスト５ｙを配線の一部に使用するなど、位置ズレ抑制用突起５，３４内に配線を形成してもよい。   By the way, in the above-described embodiment, the misalignment suppressing protrusions 5 and 34 are formed of resin, but as shown in FIG. 12, the center thereof is formed of a metal post 5y such as Cu, and the surface thereof is formed of an insulating layer 5x. A coating structure may be employed. As a result, the misalignment suppressing protrusions 5 and 34 are strengthened. In this case, a short circuit between the protruding electrodes 14 is prevented by the insulating layer 5x. Further, as another structure, the metal post 5y shown in FIG. 12 may be used as a part of the wiring, and the wiring may be formed in the misalignment suppressing protrusions 5 and 34.

また、図１３に示すように、位置ズレ抑制用突起３２の側面をテーパー状に形成することにより上面を下面よりも狭くしてもよい。位置ズレ抑制用突起３２の側面をテーパー状にする方法として、例えば、図９Ｂ、図９Ｃに示したように、露光された感光性エポキシ樹脂３６を現像する際に現像時間を長くする方法がある。また、感光性エポキシ樹脂３６を現像した後に、プラズマなどで位置ズレ抑制用突起３２を所定時間アッシングすることによりテーパー形状にしてもよい。これにより、位置ズレ抑制用突起３２の上端が比較的狭くなるので、位置ズレ抑制用突起３２を複数の突起電極１４の間に嵌め入れ易くなる。
なお、上記した実施形態では、半導体素子同士を接続する場合について説明したがその他の素子同士の電極の接続部分に上記した構造を採用してもよい。そのような素子として、半導体素子の他、例えば回路基板、パッケージ基板がある。 Further, as shown in FIG. 13, the upper surface may be narrower than the lower surface by forming the side surface of the positional deviation suppressing projection 32 in a tapered shape. For example, as shown in FIGS. 9B and 9C, there is a method of increasing the developing time when developing the exposed photosensitive epoxy resin 36 as a method of making the side surface of the misregistration suppressing protrusion 32 tapered. . Further, after developing the photosensitive epoxy resin 36, the positional deviation suppressing protrusion 32 may be ashed by ashing with plasma or the like for a predetermined time. As a result, the upper end of the misregistration suppression projection 32 becomes relatively narrow, so that the misalignment suppression projection 32 can be easily fitted between the plurality of projection electrodes 14.
In the above-described embodiment, the case where the semiconductor elements are connected to each other has been described. However, the above-described structure may be employed for the connection portion of the electrodes of the other elements. Examples of such an element include a circuit board and a package board in addition to a semiconductor element.

ここで挙げた全ての例および条件的表現は、発明者が技術促進に貢献した発明および概念を読者が理解するのを助けるためのものであり、ここで具体的に挙げたそのような例および条件に限定することなく解釈すべきであり、また、明細書におけるそのような例の編成は本発明の優劣を示すこととは関係ない。本発明の実施形態を詳細に説明したが、本発明の精神および範囲から逸脱することなく、それに対して種々の変更、置換および変形を施すことができると理解すべきである。   All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

１ 第１の半導体素子
３ 第１の電極
４ 第１の半田層
５ 位置ズレ抑制用突起
１０ 半導体装置
１１ 第２の半導体素子
１３ 第１電極
１４ 突起電極
１５ 第２の半田層
２０ 半導体装置
３１ 第１の半導体素子
３２ 位置ズレ抑制用突起
３３ 第３電極
３４ 第３の半田層
４３ 配線 DESCRIPTION OF SYMBOLS 1 1st semiconductor element 3 1st electrode 4 1st solder layer 5 Protrusion 10 for position shift suppression Semiconductor device 11 2nd semiconductor element 13 1st electrode 14 Projection electrode 15 2nd solder layer 20 Semiconductor device 31 1st 1 semiconductor element 32 misalignment suppressing projection 33 third electrode 34 third solder layer 43 wiring

Claims (5)

第１の素子と、
前記第１の素子の上に形成され、少なくとも露出面が絶縁材から形成される柱状突起と、
前記柱状突起の周囲に形成される複数の第１電極と、
を有する電子デバイス。 A first element;
A columnar protrusion formed on the first element and having at least an exposed surface formed of an insulating material;
A plurality of first electrodes formed around the columnar protrusions;
An electronic device. 前記第１の素子に対向して配置される第２の素子と、
前記第２の素子のうち前記第１の素子との対向面の上に、前記柱状突起が嵌め込まれる領域を囲む複数の第２電極上に形成される突起電極と、
を有する請求項１に記載の電子デバイス。 A second element disposed opposite the first element;
A protruding electrode formed on a plurality of second electrodes surrounding a region in which the columnar protrusion is fitted on a surface of the second element facing the first element;
The electronic device according to claim 1, comprising: 前記第１電極は、前記柱状突起の側面に形成され、前記突起電極の側面に半田を介して接続される請求項２に記載の電子デバイス。   The electronic device according to claim 2, wherein the first electrode is formed on a side surface of the columnar protrusion and connected to the side surface of the protruding electrode via solder. 前記第１電極は、前記第１の素子上の前記突起電極の上端が対向する領域に形成され、前記突起電極の前記上端に半田を介して接続される請求項２に記載の電子デバイス。   The electronic device according to claim 2, wherein the first electrode is formed in a region where an upper end of the protruding electrode on the first element is opposed to the upper end of the protruding electrode, and is connected to the upper end of the protruding electrode via solder. 前記第１の素子と前記第２の素子の少なくとも一方は、半導体素子であることを特徴とする請求項２乃至請求項４のいずれか１項に記載の電子デバイス。   5. The electronic device according to claim 2, wherein at least one of the first element and the second element is a semiconductor element. 6.
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