JP2011159661A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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Abstract
【解決手段】複数の第1電極パッド11を第1面に有する半導体チップ10と、第1面上で、複数の第1電極パッド11の各々と接触し、複数の第1電極パッド11の各々を電気的に接続する第1配線テープ20とを具備する。
【選択図】図1
Description
本発明の第1の実施の形態による半導体装置1を説明する。図1は、本発明の第1の実施の形態の半導体装置1を示す平面図である。図1を参照すると、半導体装置1は、半導体チップ10と、配線テープ20と、配線テープ30と、パッケージ端子部40と、接続リード50と、接続リード60と、ワイヤ部70とを具備する。尚、本発明の半導体装置1は、パッケージ端子部40の外端を残して、半導体チップ10等を保護するために樹脂によって封止されるが、図1では封止樹脂は省略されている。
本発明の第2の実施の形態による半導体装置1を説明する。本発明の第2の実施の形態による半導体装置1は、第1の実施の形態の接続リード50と接続リード60とをワイヤに変更したものである。図4は、本発明の第2の実施の形態の半導体装置1を示す平面図である。図4を参照すると、半導体装置1は、半導体チップ10と、配線テープ20と、配線テープ30と、パッケージ端子部40と、ワイヤ部70とを具備する。尚、本発明の第2の実施の形態では、第1の実施の形態と同様の構成には同じ符号を用いて説明する。
10 半導体チップ
11 GND用パッド
12 VDD用パッド
13 信号用パッド
20 配線テープ
30 配線テープ
40 パッケージ端子部
41 GND用パッケージ端子
42 VDD用パッケージ端子
43 信号用パッケージ端子
50 接続リード
60 接続リード
70 ワイヤ部
70a ワイヤ
70b ワイヤ
70c ワイヤ
Claims (14)
- 複数の第1電極パッドを第1面に有する半導体チップと、
前記第1面上で、前記複数の第1電極パッドの各々と接触し、前記複数の第1電極パッドの各々を電気的に接続する第1配線テープと
を具備する
半導体装置。 - 請求項1に記載の半導体装置であって、
前記第1配線テープは、前記第1面上で閉曲線状に配置される
半導体装置。 - 請求項2に記載の半導体装置であって、
前記第1面上に第2配線テープ
を更に具備し、
前記半導体チップは、
前記第1配線テープで囲まれた前記第1面に、複数の第2電極パッド
を更に有し、
前記第2配線テープは、前記複数の第2電極パッドの各々と接触し、前記複数の第2電極パッドの各々を電気的に接続する
半導体装置。 - 請求項3に記載の半導体装置であって、
前記第2配線テープは、前記第1面上で閉曲線状に配置される
半導体装置。 - 請求項1乃至4の何れか一項に記載の半導体装置であって、
前記第1配線テープは、
前記複数の第1電極パッドの各々と接触する第1導体層と、
前記第1導体層の上に形成され、前記第1配線テープの表面に位置する第1絶縁層と
を備える
半導体装置。 - 請求項3又は4に記載の半導体装置であって、
前記第1配線テープは、
前記複数の第1電極パッドの各々と接触する第1導体層と、
前記第1導体層の上に形成され、前記第1配線テープの表面に位置する第1絶縁層と
を備え、
前記第2配線テープは、
前記複数の第2電極パッドの各々と接触する第2導体層と、
前記第2導体層の上に形成され、前記第2配線テープの表面に位置する第2絶縁層と
を備える
半導体装置。 - 請求項3乃至6の何れか一項に記載の半導体装置であって、
外部と接続する第1パッケージ端子と、
外部と接続する第2パッケージ端子と、
前記第1配線テープと、前記第1パッケージ端子とを電気的に接続する第1接続部と、
前記第2配線テープと、前記第2パッケージ端子とを電気的に接続する第2接続部と
を更に具備する
半導体装置。 - 請求項7に記載の半導体装置であって、
前記第1接続部は、
前記第1配線テープと前記第1パッケージ端子とを電気的に接続する第3導体層と、
前記第3導体層の上に形成され、前記第1接続部の表面に位置する第3絶縁層と
を備え、
前記第2接続部は、
前記第2配線テープと前記第2パッケージ端子とを電気的に接続する第4導体層と、
前記第4導体層の上に形成され、前記第2接続部の表面に位置する第4絶縁層と
を備える
半導体装置。 - 請求項7又は8に記載の半導体装置であって、
前記第1パッケージ端子と前記第2パッケージ端子とには、異なる電圧が供給される
半導体装置。 - 半導体チップの第1面に形成された複数の第1電極パッドの各々と電気的に接続するように、第1配線テープを接着する工程と、
外部と接続する第1パッケージ端子と、前記第1配線テープとを第1接続部で電気的に接続する工程と
を具備する
半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法であって、
前記第1配線テープを接着する工程は、
前記第1面上に、前記第1配線テープを閉曲線状に接着する工程
を備える
半導体装置の製造方法。 - 請求項11に記載の半導体装置の製造方法であって、
前記第1面に形成された、前記第1配線テープで囲まれた複数の第2電極パッドの各々と電気的に接続するように、第2配線テープを接着する工程と、
外部と接続する第2パッケージ端子と、前記第2配線テープとを第2接続部で電気的に接続する工程と
を更に具備する
半導体装置の製造方法。 - 請求項11に記載の半導体装置の製造方法であって、
前記第1面に形成された、前記第1配線テープの外側の複数の第2電極パッドの各々と電気的に接続するように、第2配線テープを接着する工程と、
外部と接続する第2パッケージ端子と、前記第2配線テープとを第2接続部で電気的に接続する工程と
を更に具備する
半導体装置の製造方法。 - 請求項12又は13に記載の半導体装置の製造方法であって、
前記第2配線テープを接着する工程は、
前記第1面上に、前記第2配線テープを閉曲線状に接着する工程
を備える
半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010017851A JP5404454B2 (ja) | 2010-01-29 | 2010-01-29 | 半導体装置及び半導体装置の製造方法 |
US13/013,130 US8664776B2 (en) | 2010-01-29 | 2011-01-25 | Interconnection tape providing a serial electrode pad connection in a semiconductor device |
CN201110033215.XA CN102163577B (zh) | 2010-01-29 | 2011-01-28 | 半导体器件和半导体器件的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010017851A JP5404454B2 (ja) | 2010-01-29 | 2010-01-29 | 半導体装置及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2011159661A true JP2011159661A (ja) | 2011-08-18 |
JP5404454B2 JP5404454B2 (ja) | 2014-01-29 |
Family
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JP2010017851A Expired - Fee Related JP5404454B2 (ja) | 2010-01-29 | 2010-01-29 | 半導体装置及び半導体装置の製造方法 |
Country Status (3)
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US (1) | US8664776B2 (ja) |
JP (1) | JP5404454B2 (ja) |
CN (1) | CN102163577B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5891295B2 (ja) * | 2012-03-14 | 2016-03-22 | パナソニック株式会社 | 半導体装置 |
US20220223560A1 (en) * | 2021-01-14 | 2022-07-14 | Changxin Memory Technologies, Inc. | Chip structure, packaging structure and manufacturing method of chip structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0521694A (ja) * | 1991-07-11 | 1993-01-29 | Mitsubishi Electric Corp | 半導体装置 |
JPH11307591A (ja) * | 1998-04-20 | 1999-11-05 | Toshiba Corp | 半導体装置及びその製造方法、並びにtabテープ |
JP2000077559A (ja) * | 1998-08-28 | 2000-03-14 | Toshiba Corp | 半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5815173A (en) * | 1991-01-30 | 1998-09-29 | Canon Kabushiki Kaisha | Nozzle structures for bubblejet print devices |
JPH08288323A (ja) | 1995-04-17 | 1996-11-01 | Toshiba Corp | 半導体装置 |
US6476486B1 (en) * | 1997-10-30 | 2002-11-05 | Agilent Technologies, Inc. | Ball grid array package with supplemental electronic component |
US7613010B2 (en) * | 2004-02-02 | 2009-11-03 | Panasonic Corporation | Stereoscopic electronic circuit device, and relay board and relay frame used therein |
JP4904670B2 (ja) * | 2004-06-02 | 2012-03-28 | 富士通セミコンダクター株式会社 | 半導体装置 |
-
2010
- 2010-01-29 JP JP2010017851A patent/JP5404454B2/ja not_active Expired - Fee Related
-
2011
- 2011-01-25 US US13/013,130 patent/US8664776B2/en active Active
- 2011-01-28 CN CN201110033215.XA patent/CN102163577B/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0521694A (ja) * | 1991-07-11 | 1993-01-29 | Mitsubishi Electric Corp | 半導体装置 |
JPH11307591A (ja) * | 1998-04-20 | 1999-11-05 | Toshiba Corp | 半導体装置及びその製造方法、並びにtabテープ |
JP2000077559A (ja) * | 1998-08-28 | 2000-03-14 | Toshiba Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN102163577A (zh) | 2011-08-24 |
US20110187008A1 (en) | 2011-08-04 |
JP5404454B2 (ja) | 2014-01-29 |
CN102163577B (zh) | 2015-06-17 |
US8664776B2 (en) | 2014-03-04 |
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