JP2011061030A - Crystal silicon-based solar cell - Google Patents
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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Abstract
Description
本発明は、単結晶シリコン基板表面にヘテロ接合を有する結晶シリコン太陽電池に関するものである。 The present invention relates to a crystalline silicon solar cell having a heterojunction on the surface of a single crystal silicon substrate.
結晶シリコン基板を用いた結晶シリコン太陽電池は、光電変換効率が高く、既に太陽光発電システムとして広く一般に実用化されている。中でも単結晶シリコンとはギャップの異なる非晶質シリコン系薄膜を単結晶表面へ製膜し、拡散電位を形成した結晶シリコン太陽電池はヘテロ接合太陽電池と言う。中でも拡散電位を形成するための導電型非晶質シリコン系薄膜と結晶シリコン表面の間に、薄い真性非晶質シリコン層を介在させる太陽電池は、変換効率の最も高い結晶シリコン太陽電池の形態の一つである。結晶表面と導電型非晶質シリコン系薄膜の間に薄い真性な非晶質シリコン層を製膜することで、結晶の表面に存在する欠陥をパッシベートすることができる。また、導電型非晶質シリコン系薄膜を製膜する際の、キャリア導入不純物の結晶シリコン表面への拡散を防止することができる。 A crystalline silicon solar cell using a crystalline silicon substrate has high photoelectric conversion efficiency, and has already been widely put into practical use as a photovoltaic power generation system. Among them, a crystalline silicon solar cell in which an amorphous silicon thin film having a gap different from that of single crystal silicon is formed on the surface of the single crystal and a diffusion potential is formed is called a heterojunction solar cell. Above all, a solar cell in which a thin intrinsic amorphous silicon layer is interposed between a conductive amorphous silicon thin film for forming a diffusion potential and a crystalline silicon surface is a form of a crystalline silicon solar cell having the highest conversion efficiency. One. By forming a thin intrinsic amorphous silicon layer between the crystal surface and the conductive amorphous silicon thin film, defects present on the crystal surface can be passivated. In addition, it is possible to prevent carrier introduced impurities from diffusing to the crystalline silicon surface when the conductive amorphous silicon thin film is formed.
結晶シリコンはその周期構造を反映した電子状態の異方性を有しており、価電子バンドの頂上と伝導帯バンドの底の波数ベクトルが一致しないため、電子の遷移にはフォノンと相互作用が必要となる。これを間接遷移といい、結晶シリコンは間接遷移型半導体と呼ばれている。間接遷移型半導体を太陽電池に用いた場合、フォノンとの相互作用を必要としない直接遷移型半導体と比較して、光吸収係数が低いので光を如何に光電変換層に閉じ込めるかが重要な技術の一つとなる。光を閉じ込めるためには太陽電池の光学特性を制御する必要があり、その光学特性は主に屈折率差を有する界面形状と各層の膜厚によって決定される。 Crystalline silicon has an anisotropy in the electronic state that reflects its periodic structure, and the wave number vectors at the top of the valence band and the bottom of the conduction band do not match. Necessary. This is called indirect transition, and crystalline silicon is called an indirect transition type semiconductor. When using indirect transition type semiconductors for solar cells, the optical absorption coefficient is low compared to direct transition type semiconductors that do not require interaction with phonons, so it is important how to confine light in the photoelectric conversion layer. It becomes one of. In order to confine light, it is necessary to control the optical characteristics of the solar cell, and the optical characteristics are mainly determined by the interface shape having a refractive index difference and the film thickness of each layer.
一般的に結晶シリコン太陽電池は、表面に製膜されている透明電極や金属よりも屈折率が高く、幾何光学上、屈折率の高い媒質中に光が閉じ込められやすい。その光閉じ込め効果を増大させるためには、太陽電池に対して直入射した光の方向を曲げる必要がある。入射面に対して界面へ波長程度の大きさのテクスチャ構造を設けることで、屈折率差を有する界面に対して光を斜入射させることができ、光を屈折させることで光の進行方向を曲げることができる。この効果により、入射光が入射側界面に到達した場合や裏面側界面に到達した場合などに、光が高屈折率側（シリコン側）に閉じ込められる確率が高くなる。 In general, a crystalline silicon solar cell has a refractive index higher than that of a transparent electrode or metal formed on the surface, and light is easily confined in a medium having a high refractive index in terms of geometric optics. In order to increase the light confinement effect, it is necessary to bend the direction of the light directly incident on the solar cell. By providing a texture structure with a size of about the wavelength at the interface with respect to the incident surface, light can be incident obliquely on the interface having a refractive index difference, and the light traveling direction is bent by refracting the light. be able to. This effect increases the probability that the light is confined on the high refractive index side (silicon side) when the incident light reaches the incident side interface or the back side interface.
薄膜によって構成される界面の間隔が波長程度のオーダーである場合、それぞれの界面における反射光が干渉し、波の重ね合わせの原理より反射光の増減が起こる。干渉は一般的に結晶太陽電池においては入射面側のシリコン（屈折率３．９）上に配置する透明電極（屈折率１．９）の膜厚を６０〜１００ｎｍ程度に制御することで、太陽光スペクトルで最も強度の強い波長領域（５００〜７００ｎｍ）の光の反射を低減している。空気／透明電極／シリコンの屈折率構成の場合、透明電極の界面における反射光を干渉させる光学設計が最も有効であり、この干渉の効果を損なわないようなテクスチャ構造が前提となる。但し、太陽電池を現実に用いるためには封止部材で封止する必要があり、封止部材の屈折率は空気よりも高い１．５程度である。つまり、封止を必要とする太陽電池を用いる場合は、透明電極による干渉を利用する光学設計の優先度合いは、封止部材を利用しない場合と比較して低くなる。 When the distance between the interfaces formed by the thin films is on the order of a wavelength, the reflected light at each interface interferes and the reflected light increases or decreases due to the principle of wave superposition. In general, in the case of a crystal solar cell, interference is controlled by controlling the film thickness of a transparent electrode (refractive index 1.9) disposed on silicon (refractive index 3.9) on the incident surface side to about 60 to 100 nm. The reflection of light in the wavelength region (500 to 700 nm) having the strongest intensity in the optical spectrum is reduced. In the case of the refractive index configuration of air / transparent electrode / silicon, an optical design that interferes with reflected light at the interface of the transparent electrode is most effective, and a texture structure that does not impair the effect of this interference is presupposed. However, in order to actually use the solar cell, it is necessary to seal with a sealing member, and the refractive index of the sealing member is about 1.5, which is higher than that of air. That is, when a solar cell that requires sealing is used, the priority of optical design that uses interference by the transparent electrode is lower than when the sealing member is not used.
一般的に結晶シリコン太陽電池のシリコン基板表面には底辺の一辺が５〜２０μｍ程度の四角錐が並んだテクスチャが形成されており、その表面に６０〜１００ｎｍ程度の透明電極が形成されている。このテクスチャサイズは吸収を目的としている光のシリコン中における波長よりも２０〜１５０倍と十分大きく、屈折された光は平面波として結晶シリコン内を進行する。透明電極が空気と界面を構成している場合は問題ないが、樹脂などを用いて封止がなされた場合、平面波として振舞う短波長光の反射率が増大してしまう。一方で、波長に対してテクスチャサイズが０．１倍以下と小さい場合、テクスチャの影響が極めて小さく、屈折されない光が平面波のまま結晶シリコン内を進行し、やはり幾何光学的ロスが大きくなる。テクスチャサイズを、閉じ込めたい光の波長の０．８〜２０倍程度とすることで、光を効率的に散乱させることができ、界面を通過した光が平面波を保てなくすることができ、幾何光学的ロスを低減できる。 In general, a texture in which square pyramids having a base of about 5 to 20 μm are arranged on the surface of a silicon substrate of a crystalline silicon solar cell, and a transparent electrode of about 60 to 100 nm is formed on the surface. This texture size is sufficiently large, 20 to 150 times the wavelength of light intended for absorption in silicon, and the refracted light travels through the crystalline silicon as a plane wave. There is no problem when the transparent electrode forms an interface with air, but when sealing is performed using a resin or the like, the reflectance of short-wavelength light that behaves as a plane wave increases. On the other hand, when the texture size is as small as 0.1 times or less with respect to the wavelength, the influence of the texture is extremely small, and the unrefracted light travels in the crystalline silicon as a plane wave, and the geometrical optical loss is also increased. By setting the texture size to about 0.8 to 20 times the wavelength of the light to be confined, the light can be scattered efficiently, and the light that has passed through the interface can no longer maintain a plane wave. Optical loss can be reduced.
結晶シリコン基板の表面にテクスチャを形成する手法としては、シリコンの（１００）面と（１１１）面のエッチング速度の違いを利用した異方性エッチングによって形成される。シリコン（１００）面をエッチングすると、エッチング速度の極めて遅いシリコン（１１１）面からなる四角錐状のテクスチャが形成される。 As a method for forming a texture on the surface of the crystalline silicon substrate, the texture is formed by anisotropic etching utilizing a difference in etching rate between the (100) plane and the (111) plane of silicon. When the silicon (100) plane is etched, a quadrangular pyramid-like texture consisting of a silicon (111) plane with a very slow etching rate is formed.
特許文献１では、入射面及び側面、裏面周縁部をテクスチャ構造とすることによって、感度を向上させることができるとしている。しかし、入射面にテクスチャを作成する工程は一種類であり、異なる大きさのテクスチャを組み合わせるといった記載は見られず、これでは入射側界面での幾何光学的反射ロスを十分に抑えることができない。 In patent document 1, it is supposed that a sensitivity can be improved by making an incident surface, a side surface, and a back surface peripheral part into a texture structure. However, there is only one type of process for creating a texture on the incident surface, and there is no description of combining textures of different sizes, and this cannot sufficiently suppress the geometric optical reflection loss at the incident side interface.
本発明の目的は、単結晶シリコン基板を用いた光起電力装置において、光電変換効率に優れた光起電力装置を提供することにある。 An object of the present invention is to provide a photovoltaic device having excellent photoelectric conversion efficiency in a photovoltaic device using a single crystal silicon substrate.
本発明者らは上記課題に鑑み鋭意検討した結果、厚みが１５０μｍ以下である単結晶シリコン基板を用いた結晶シリコン太陽電池において、入射面側に、算術平均粗さが１５００ｎｍ以下の四角錐状テクスチャを形成し、３００〜９００ｎｍの光を散乱させ、裏面側に算術平均粗さが２０００ｎｍ以上となるように四角錐状テクスチャを形成することで、裏面に到達した８００ｎｍ以上の長波長光を散乱させることで、広い波長範囲の光をより効率的に閉じ込めることができ、光電変換効率が向上することを見出した。 As a result of intensive studies in view of the above problems, the present inventors have found that in a crystalline silicon solar cell using a single crystal silicon substrate having a thickness of 150 μm or less, a quadrangular pyramid texture having an arithmetic average roughness of 1500 nm or less on the incident surface side. Is formed, a light having a wavelength of 300 to 900 nm is scattered, and a rectangular pyramid-like texture is formed on the back surface side so that the arithmetic average roughness is 2000 nm or more, thereby scattering the long wavelength light of 800 nm or more reaching the back surface. Thus, it was found that light in a wide wavelength range can be confined more efficiently, and the photoelectric conversion efficiency is improved.
すなわち、本発明は、一導電型単結晶シリコン基板を用い、前記基板の一面にｐ型シリコン系薄膜層を有し、前記基板と前記ｐ型シリコン系薄膜層の間に実質的に真正なシリコン系薄膜層を備え、前記基板の他面にｎ型シリコン系薄膜層を有し、前記基板と前記ｎ型シリコン系薄膜層の間に実質的に真正なシリコン系薄膜層を備えた結晶シリコン太陽電池であって、前記基板の厚みが１５０μｍ以下であり、前記基板の入射側表面及び裏面側表面に四角錐で構成されるテクスチャ構造を備え、前記基板の入射側表面における算術平均粗さが１５００ｎｍ以下であり、裏面側表面の算術平均粗さが２０００ｎｍ以上であることを特徴とする結晶シリコン太陽電池に関する。 That is, the present invention uses a single-conductivity type single crystal silicon substrate, has a p-type silicon thin film layer on one surface of the substrate, and is substantially genuine silicon between the substrate and the p type silicon thin film layer. A crystalline silicon solar cell comprising an n-type thin film layer, having an n-type silicon thin film layer on the other surface of the substrate, and a substantially authentic silicon thin film layer between the substrate and the n-type silicon thin film layer The battery has a thickness of the substrate of 150 μm or less, and has a texture structure composed of quadrangular pyramids on the incident side surface and the back side surface of the substrate, and the arithmetic average roughness on the incident side surface of the substrate is 1500 nm. It is below, It is related with the crystalline silicon solar cell characterized by arithmetic mean roughness of the back surface side surface being 2000 nm or more.
好ましい実施態様は、前記基板の入射側表面における算術平均粗さが５００ｎｍ以下であり、裏面側表面の算術平均粗さが２０００ｎｍ以上であることを特徴とする前記の結晶シリコン太陽電池に関する。 A preferred embodiment relates to the above crystalline silicon solar cell, wherein the arithmetic average roughness on the incident-side surface of the substrate is 500 nm or less, and the arithmetic average roughness on the back-side surface is 2000 nm or more.
好ましい実施態様は、前記基板の入射側表面における算術平均粗さが３００ｎｍ以下であり、裏面側表面の算術平均粗さが２０００ｎｍ以上であることを特徴とする前記の結晶シリコン太陽電池に関する。 A preferred embodiment relates to the above crystalline silicon solar cell, wherein the arithmetic average roughness on the incident-side surface of the substrate is 300 nm or less and the arithmetic average roughness on the back-side surface is 2000 nm or more.
本発明は、前記いずれかに記載の結晶シリコン太陽電池の製造方法であって、前記テクスチャ構造を形成する工程と、前記テクスチャ構造の表面を酸化処理する工程と、前記酸化処理する工程によって形成された酸化シリコン層を除去する工程を含むことを特徴とする結晶シリコン太陽電池の製造方法に関する。 The present invention is the method for manufacturing a crystalline silicon solar cell according to any one of the above, wherein the textured structure is formed by the step of forming the texture structure, the step of oxidizing the surface of the texture structure, and the step of oxidizing. The present invention also relates to a method for manufacturing a crystalline silicon solar cell, comprising the step of removing the silicon oxide layer.
好ましい実施態様は、前記テクスチャ構造がエッチングによって形成されることを特徴とする前記の結晶シリコン太陽電池の製造方法に関する。 A preferred embodiment relates to the method for producing a crystalline silicon solar cell, wherein the texture structure is formed by etching.
好ましい実施態様は、２枚の一導電型単結晶シリコン基板を、夫々の片面で合わせた状態で、エッチング能力を有する媒質中に晒すことで、前記２枚の一導電型単結晶シリコン基板の夫々合わさっていない片面にのみ前記テクスチャ構造を形成することを特徴とする前記の結晶シリコン太陽電池の製造方法に関する。 In a preferred embodiment, each of the two single-conductive single-crystal silicon substrates is exposed to a medium having an etching ability in a state where the two single-conductive single-crystal silicon substrates are combined on one side. The present invention relates to the method for producing a crystalline silicon solar cell, wherein the texture structure is formed only on one side that is not combined.
本発明の構造によって、光閉じ込め特性が向上し、主に短絡電流が向上することで高い光電変換効率が得られる。 With the structure of the present invention, the optical confinement characteristics are improved, and high photoelectric conversion efficiency is obtained mainly by improving the short-circuit current.
本発明に係る結晶シリコン太陽電池は、基板の厚みが１５０μｍ以下の一導電型単結晶シリコン基板を用い、前記基板の一面にｐ型シリコン系薄膜層を有し、前記基板と前記ｐ型シリコン系薄膜層の間に実質的に真正なシリコン系薄膜層を備え、前記基板の他面にｎ型シリコン系薄膜層を有し、前記基板と前記ｎ型シリコン系薄膜層の間に実質的に真正なシリコン系薄膜層を備え、前記基板の入射側表面及び裏面側表面に四角錐で構成されるテクスチャ構造を備え、前記基板の入射側表面における算術平均粗さが１５００ｎｍ以下であり、裏面側表面における算術平均粗さが２０００ｎｍ以上であることを特徴としている。 The crystalline silicon solar cell according to the present invention uses a single conductivity type single crystal silicon substrate having a substrate thickness of 150 μm or less, has a p-type silicon thin film layer on one surface of the substrate, and the substrate and the p-type silicon system. A substantially authentic silicon-based thin film layer is provided between the thin film layers, an n-type silicon-based thin film layer is provided on the other surface of the substrate, and the substrate is substantially genuine between the n-type silicon-based thin film layer. A silicon-based thin film layer, a texture structure composed of quadrangular pyramids on the incident side surface and the back side surface of the substrate, the arithmetic average roughness on the incident side surface of the substrate is 1500 nm or less, and the back side surface The arithmetic average roughness in is characterized by being 2000 nm or more.
まず、本発明の結晶シリコン太陽電池における、一導電型単結晶シリコン基板について説明する。 First, the one conductivity type single crystal silicon substrate in the crystalline silicon solar cell of the present invention will be described.
一般的に単結晶シリコン基板は導電性を持たせるために、シリコンに対して電荷を供給する不純物を含有させる。単結晶シリコン基板はＳｉ原子に対して電子を導入するリン原子を供給したｎ型と、ホール（正孔ともいう）を導入するボロン原子を供給したｐ型がある。太陽電池に用いる場合、単結晶シリコン基板へ入射した光が最も多く吸収される入射側のへテロ接合を逆接合として強い電場を設けることで、電子正孔対を効率的に分離回収することができる。よって入射側のヘテロ接合は逆接合とすることが好ましい。一方で、正孔と電子を比較した場合、有効質量及び散乱断面積の小さい電子の方が一般的に移動度は大きくなる。以上の観点から、本発明において使用する一導電型単結晶シリコン基板は、ｎ型単結晶シリコン基板であることがより好ましい。 In general, a single crystal silicon substrate contains impurities for supplying electric charge to silicon in order to have conductivity. Single crystal silicon substrates are classified into an n-type supplied with phosphorus atoms for introducing electrons into Si atoms and a p-type supplied with boron atoms for introducing holes (also called holes). When used in solar cells, electron-hole pairs can be efficiently separated and recovered by providing a strong electric field with the incident-side heterojunction that absorbs the most light incident on the single crystal silicon substrate as the reverse junction. it can. Therefore, the heterojunction on the incident side is preferably a reverse junction. On the other hand, when holes and electrons are compared, the mobility is generally higher for electrons having a smaller effective mass and scattering cross section. From the above viewpoint, it is more preferable that the one conductivity type single crystal silicon substrate used in the present invention is an n type single crystal silicon substrate.
ｎ型単結晶シリコン基板を用いた場合の本発明の好適な構成としては、導電性酸化物層／ｐ型非晶質シリコン系薄膜層／ｉ型非晶質シリコン系薄膜層／ｎ型単結晶シリコン基板／ｉ型非晶質シリコン系薄膜層／ｎ型非晶質シリコン系薄膜層／導電性酸化物層が例示され、この場合は上記理由から裏面をｎ層とすることが好ましい。例えば、酸化亜鉛等を主成分とする導電性酸化物の膜厚は、光閉じ込めの観点から、６０〜１２０ｎｍの範囲であることが好ましい。 As a preferred configuration of the present invention when an n-type single crystal silicon substrate is used, a conductive oxide layer / p-type amorphous silicon thin film layer / i type amorphous silicon thin film layer / n single crystal Examples are silicon substrate / i-type amorphous silicon-based thin film layer / n-type amorphous silicon-based thin film layer / conductive oxide layer. In this case, the back surface is preferably an n-layer for the above reasons. For example, the thickness of the conductive oxide mainly composed of zinc oxide or the like is preferably in the range of 60 to 120 nm from the viewpoint of light confinement.
前記一導電型単結晶シリコン基板の厚みは、原料シリコン節約の観点から、１５０μｍ以下であることが好ましく、更に好ましくは１２０μｍ以下である。一導電型単結晶シリコン基板の厚みが１５０μｍ以下である場合、太陽電池へ入射する光の内、９００ｎｍ以上の長波長光が裏面界面に到達する割合が多くなる。このため、入射側テクスチャで短波長光を散乱し、裏面側テクスチャで長波長光を効果的に散乱できる本発明の構成はより効果的となる。一方、前記単結晶シリコン基板の厚みの下限値は特に制限はないが、製造時の安定性と光吸収の観点から、３０μｍ以上が好ましく、さらには６０μｍ以上がより好ましい。 The thickness of the one conductivity type single crystal silicon substrate is preferably 150 μm or less, more preferably 120 μm or less, from the viewpoint of saving raw material silicon. When the thickness of the single-conductivity-type single crystal silicon substrate is 150 μm or less, among the light incident on the solar cell, the ratio of the long wavelength light of 900 nm or more reaching the back surface interface increases. For this reason, the structure of this invention which can scatter short wavelength light with an incident side texture, and can effectively scatter long wavelength light with a back surface texture becomes more effective. On the other hand, the lower limit of the thickness of the single crystal silicon substrate is not particularly limited, but is preferably 30 μm or more, and more preferably 60 μm or more, from the viewpoint of stability during production and light absorption.
本発明においては、前記単結晶シリコン基板は、基板の入射側表面及び裏面側表面に四角錐で構成されるテクスチャ構造を備えており、当該各表面が特定の算術平均粗さを有することを特徴とする。 In the present invention, the single crystal silicon substrate has a texture structure composed of quadrangular pyramids on the incident-side surface and the back-side surface of the substrate, and each surface has a specific arithmetic average roughness. And
テクスチャ構造を入射面と裏面に夫々設け、入射面と裏面側のテクスチャサイズを制御することで、夫々の主面で波長の異なる光に対する効果的な散乱特性を得ることができる。 By providing a texture structure on each of the incident surface and the back surface and controlling the texture size on the incident surface and the back surface side, it is possible to obtain effective scattering characteristics for light having different wavelengths on the respective main surfaces.
テクスチャ形状は、結晶シリコンを異方性エッチングすることで容易に得られる形状である四角錐状のテクスチャが一般的である。この構造は比較的均一に形成することが可能で、生産性の観点から好ましい。頂点部は光学的な観点からは鋭いほうが好ましいが、非晶質シリコン層製膜及びキャリア回収という観点からは頂点、特に谷部が丸くなっていることが好ましい。丸みの程度としては、製膜する非晶質シリコン層の膜厚と同じオーダーで丸みを帯びていることが好ましい。 The texture shape is generally a quadrangular pyramid texture that is easily obtained by anisotropic etching of crystalline silicon. This structure can be formed relatively uniformly and is preferable from the viewpoint of productivity. The apex is preferably sharp from the optical point of view, but it is preferable that the apex, particularly the valley, is rounded from the viewpoint of amorphous silicon film formation and carrier recovery. The degree of roundness is preferably rounded in the same order as the film thickness of the amorphous silicon layer to be formed.
前記基板の光入射側表面は、光閉じ込めの観点から、上限値が１５００ｎｍ以下、好ましくは５００ｎｍ以下、特に好ましくは３００ｎｍ以下の算術平均粗さとなるように、四角錐で構成されるテクスチャ構造を備えることが好ましい。前記基板の光入射側表面における算術平均粗さの下限値は、短波長光散乱の観点から、４０ｎｍ以上、更には８０ｎｍ以上であることが好ましい。 From the viewpoint of light confinement, the surface of the light incident side of the substrate has a texture structure composed of quadrangular pyramids so that the upper limit is 1500 nm or less, preferably 500 nm or less, particularly preferably 300 nm or less. It is preferable. From the viewpoint of short wavelength light scattering, the lower limit of the arithmetic average roughness on the light incident side surface of the substrate is preferably 40 nm or more, and more preferably 80 nm or more.
次に基板の裏面側表面は、長波長光を散乱させる観点から、下限値が２０００ｎｍ以上、好ましくは２０５０ｎｍ以上、特に好ましくは２１００ｎｍ以上の算術平均粗さとなるように、四角錐で構成されるテクスチャ構造を備えることが好ましい。前記基板の裏面側表面における算術平均粗さの上限値は特に制限はないが、キャリア回収の観点から、３５００ｎｍ以下、更には３０００ｎｍ以下であることが好ましい。 Next, from the viewpoint of scattering long-wavelength light, the back surface of the substrate is a texture composed of quadrangular pyramids such that the lower limit is 2000 nm or more, preferably 2050 nm or more, particularly preferably 2100 nm or more. It is preferable to provide a structure. The upper limit value of the arithmetic average roughness on the back surface of the substrate is not particularly limited, but is preferably 3500 nm or less, more preferably 3000 nm or less, from the viewpoint of carrier recovery.
上記入射側表面および裏面側表面の算術平均粗さについては、例えばＡＦＭで測定される表面形状から算出される。ＡＦＭによって測定された表面の曲線の平均線の方向に基準長さだけ抜き取り、この抜き取り部分の平均線から測定曲線までの偏差の絶対値を合計し平均した値で算出される。 The arithmetic average roughness of the incident side surface and the back side surface is calculated from, for example, the surface shape measured by AFM. A reference length is extracted in the direction of the average line of the surface curve measured by the AFM, and the absolute value of the deviation from the average line of the extracted part to the measurement curve is summed and averaged.
前記基板のテクスチャ構造の形成方法については特に制限はなく、例えば、アルカリ溶液によるウェットエッチング、ラビング、ブラスト処理、プラズマエッチング等の公知の方法により形成することができるが、本発明においては、面内での形状均一性、光閉じ込めの観点から、特にアルカリ水溶液によるウェットエッチングによって形成することが好ましい。 The method for forming the texture structure of the substrate is not particularly limited, and for example, it can be formed by a known method such as wet etching with an alkaline solution, rubbing, blasting, plasma etching, etc. From the viewpoint of shape uniformity and light confinement, it is particularly preferable to form by wet etching with an alkaline aqueous solution.
単結晶シリコン基板をエッチングする場合に（１００）面と（１１１）面のエッチングレートが異なる異方性エッチングによって容易にテクスチャ構造を形成できる観点から、前記単結晶シリコン基板は、その入射面は（１００）面であるように切り出されていることが好ましい。 From the viewpoint that a texture structure can be easily formed by anisotropic etching with different etching rates of the (100) plane and the (111) plane when etching a single crystal silicon substrate, the incident surface of the single crystal silicon substrate is ( It is preferable that it is cut out so that it is a 100) plane.
一般的に、テクスチャサイズはエッチングが進行すればするほど大きくなる傾向がある。例えば、エッチング時間を長くするとテクスチャサイズは大きくなるが、例えば反応速度が大きくなるようにエッチャント濃度、供給速度の増加や液温の上昇等によってもテクスチャサイズを大きくすることができる。また、エッチングが開始される表面状態によってもエッチング速度が異なるため、研磨等の機械的工程を実施した表面とそうでない表面とではテクスチャサイズが異なることを利用してもよい。さらに、（１１１）面で形成された四角錐状の構造が隣接した場合、つまり（１１１）面で表面が覆われた場合、エッチング速度は遅くなる傾向がある。故に、エッチングの起点を設けておくことで、テクスチャ構造の密度を制御でき、テクスチャの大きさを制御できる。また、微細なマスクを用いてエッチングすることで初期に発生するテクスチャ密度を制御することができる。エッチング起点は、例えば、研磨等の機械的工程によって形成することができる。 In general, the texture size tends to increase as etching progresses. For example, when the etching time is lengthened, the texture size increases. However, the texture size can be increased by increasing the etchant concentration, the supply rate, the liquid temperature, or the like so that the reaction rate increases. In addition, since the etching rate varies depending on the surface state where etching is started, it may be used that the texture size is different between the surface subjected to the mechanical process such as polishing and the other surface. Furthermore, when the quadrangular pyramidal structures formed by the (111) plane are adjacent, that is, when the surface is covered by the (111) plane, the etching rate tends to be slow. Therefore, by providing an etching starting point, the density of the texture structure can be controlled and the size of the texture can be controlled. Further, the texture density generated in the initial stage can be controlled by etching using a fine mask. The etching starting point can be formed by a mechanical process such as polishing.
また、テクスチャ形成後に（１１１）面と（１００）面の選択性のない等方性エッチングを行うことで、形状に丸みを帯びさせることができる。これによりキャリア回収特性を向上させることができる観点から好ましい。 Further, by performing isotropic etching with no selectivity on the (111) plane and the (100) plane after texture formation, the shape can be rounded. This is preferable from the viewpoint of improving carrier recovery characteristics.
前記単結晶シリコン基板の入射側表面および裏面側表面へのテクスチャ構造の形成について、例えば、２枚の一導電型単結晶シリコン基板を、夫々の片面で合わせた状態で、エッチング能力を有する媒質中に晒すことで、前記２枚の一導電型単結晶シリコン基板の夫々合わさっていない片面にのみ前記テクスチャ構造を形成することができる。この方法によれば、二枚の基板を同時に処理でき、マスクも不要であるため、好ましい。 Regarding the formation of the texture structure on the incident-side surface and the back-side surface of the single crystal silicon substrate, for example, in a medium having an etching capability in a state where two single-conductive single crystal silicon substrates are combined on one side. By exposing to the above, the texture structure can be formed only on one surface of the two single-conductive single crystal silicon substrates that are not combined. This method is preferable because two substrates can be processed simultaneously and a mask is not required.
なお、上記のエッチング能力を有する媒質とは、例えば、プラズマやアルカリ水溶液が例示され、中でも、面内での形状均質性の観点から、アルカリ水溶液がより好ましい。 Examples of the medium having the above-described etching ability include plasma and alkaline aqueous solution, and among them, alkaline aqueous solution is more preferable from the viewpoint of in-plane shape uniformity.
本発明における結晶シリコン太陽電池の製造方法においては、前記テクスチャ構造を形成する工程に加え、前記テクスチャ構造の表面を酸化処理する工程と、前記酸化処理する工程によって形成された酸化シリコン層を除去する工程を含むことが好ましい。 In the method for producing a crystalline silicon solar cell according to the present invention, in addition to the step of forming the texture structure, the step of oxidizing the surface of the texture structure and the silicon oxide layer formed by the step of oxidizing treatment are removed. It is preferable to include a process.
前記テクスチャ構造の表面を酸化処理する工程については、酸化皮膜を表面に形成することで、前記テクスチャ構造の表面近傍組成を変化させることができる。酸素雰囲気中で熱酸化させると、頂点で厚く、谷部に薄く緻密な酸化皮膜が形成される。酸素プラズマ中で酸化処理を施すと、放電条件にも依るが熱酸化の場合と比較してポーラスな酸化皮膜が形成される。テクスチャ構造の平滑性を保つという観点から緻密な酸化膜が得られる熱酸化処理が好ましい。 About the process of oxidizing the surface of the texture structure, the composition in the vicinity of the surface of the texture structure can be changed by forming an oxide film on the surface. When thermally oxidized in an oxygen atmosphere, a dense oxide film is formed that is thick at the apex and thin at the valleys. When the oxidation treatment is performed in oxygen plasma, a porous oxide film is formed as compared with the case of thermal oxidation although it depends on the discharge conditions. From the viewpoint of maintaining the smoothness of the texture structure, a thermal oxidation treatment that provides a dense oxide film is preferred.
また、前記酸化処理する工程によって形成された酸化シリコン層を除去する工程については、これを行うことでテクスチャ構造において局所的に異なる酸化皮膜の厚みを反映してテクスチャ形状を制御できる。酸化皮膜の厚いところは多く削れ、薄いところは少なく削れるので、四角錐状テクスチャ構造で言うと頂点や斜辺、谷部が丸くなる。酸化皮膜除去方法としては、還元雰囲気中でのプラズマ処理や、ＨＦ水溶液への浸漬等が上げられるが、使用後の表面清浄性、ダメージの少なさという観点からＨＦ水溶液による除去が好ましい。頂点、斜辺及び谷部が丸くなることで表面形状が緩和され、非晶質シリコン層を製膜する際の欠陥の生成が抑制できる。 In addition, with respect to the step of removing the silicon oxide layer formed by the oxidation treatment step, the texture shape can be controlled by reflecting the thickness of the oxide film locally different in the texture structure. Since the thick part of the oxide film can be shaved off and the thin part can be shaved down, the apex, the hypotenuse, and the trough are rounded in the quadrangular pyramid texture structure. As a method for removing the oxide film, plasma treatment in a reducing atmosphere, immersion in an HF aqueous solution, and the like can be raised. However, removal with an HF aqueous solution is preferable from the viewpoint of surface cleanliness after use and little damage. By rounding the apex, the hypotenuse and the trough, the surface shape is relaxed, and the generation of defects when forming the amorphous silicon layer can be suppressed.
上記の如く、単結晶シリコン基板表面に特定のテクスチャ構造を形成後、単結晶シリコン基板表面にシリコン系薄膜を製膜する。製膜方法としては、例えばプラズマＣＶＤ法が好ましい。 As described above, after a specific texture structure is formed on the surface of the single crystal silicon substrate, a silicon-based thin film is formed on the surface of the single crystal silicon substrate. As a film forming method, for example, a plasma CVD method is preferable.
前記シリコン系薄膜の形成条件としては、例えば、基板温度１００〜３００℃、圧力２０〜２６００Ｐａ、高周波パワー密度０．００４〜０．８Ｗ／ｃｍ2が好ましく用いられ、必要に応じて適宜調整することができる。前記シリコン系薄膜の形成に使用する原料ガスとしては、例えば、ＳｉＨ4、Ｓｉ2Ｈ6等のシリコン含有ガス、またはそれらのガスとＨ2を混合したものが好適に用いられる。光電変換ユニットにおけるｐ型またはｎ型層を形成するためのドーパントガスとしては公知のものが使用できるが、例えば、Ｂ2Ｈ6またはＰＨ3等が好ましく用いられる。また、ＰやＢといった不純物の添加量は微量でよいため、予めＳｉＨ4やＨ2で希釈された混合ガスを用いることが好ましい。また、ＣＨ4、ＣＯ2、ＮＨ3、ＧｅＨ4等といった異種元素を含むガスを添加することで、合金化しエネルギーギャップを変更することもできる。 As the formation conditions of the silicon-based thin film, for example, a substrate temperature of 100 to 300 ° C., a pressure of 20 to 2600 Pa, and a high frequency power density of 0.004 to 0.8 W / cm 2 are preferably used and adjusted as necessary. Can do. As the source gas used for forming the silicon-based thin film, for example, a silicon-containing gas such as SiH 4 or Si 2 H 6 or a mixture of these gases and H 2 is preferably used. As the dopant gas for forming the p-type or n-type layer in the photoelectric conversion unit, a known gas can be used. For example, B 2 H 6 or PH 3 is preferably used. Further, since the addition amount of impurities such as P and B may be small, it is preferable to use a mixed gas diluted with SiH 4 or H 2 in advance. Further, by adding a gas containing a different element such as CH 4 , CO 2 , NH 3 , GeH 4 or the like, it is possible to alloy and change the energy gap.
本発明の結晶シリコン太陽電池は、単結晶シリコン基板の一面にｐ型シリコン系薄膜層を有し、前記基板と前記ｐ型シリコン系薄膜層の間に実質的に真正なシリコン系薄膜層を備え、前記基板の他面にｎ型シリコン系薄膜層を有し、前記基板と前記ｎ型シリコン系薄膜層の間に実質的に真正なシリコン系薄膜層を備えたものである。 The crystalline silicon solar cell of the present invention has a p-type silicon thin film layer on one surface of a single crystal silicon substrate, and a substantially authentic silicon thin film layer is provided between the substrate and the p type silicon thin film layer. The other surface of the substrate has an n-type silicon thin film layer, and a substantially authentic silicon thin film layer is provided between the substrate and the n-type silicon thin film layer.
前記の実質的に真正なｉ型シリコン系薄膜層は、例えばｉ型微結晶シリコン、ｉ型水素化非晶質シリコン、ｉ型微結晶酸化シリコンが例示されるが、中でもシリコンと水素で構成されるｉ型水素化非晶質シリコンであることが好ましい。ｉ型水素化非晶質シリコン層のＣＶＤ製膜時において、単結晶シリコン基板への不純物拡散を抑えつつ、表面パッシベーションを有効に行うことができるからである。また、膜中の水素量を変化させることで、エネルギーギャップにキャリア回収を行う上で有効なプロファイルを持たせることもできる。 Examples of the substantially authentic i-type silicon thin film layer include i-type microcrystalline silicon, i-type hydrogenated amorphous silicon, and i-type microcrystalline silicon oxide. I-type hydrogenated amorphous silicon is preferable. This is because surface passivation can be effectively performed while suppressing impurity diffusion into the single crystal silicon substrate during CVD deposition of the i-type hydrogenated amorphous silicon layer. In addition, by changing the amount of hydrogen in the film, it is possible to give the energy gap an effective profile for carrier recovery.
前記ｐ型シリコン系薄膜層は、ｐ型水素化非晶質シリコン層かｐ型酸化非晶質シリコン層であることが好ましい。不純物拡散や直列抵抗の観点では、ｐ型水素化非晶質シリコン層が好ましい。一方で、ｐ型酸化非晶質シリコン層はワイドギャップの低屈折率層として光学的なロスを低減できる点において好ましい。 The p-type silicon thin film layer is preferably a p-type hydrogenated amorphous silicon layer or a p-type oxidized amorphous silicon layer. From the viewpoint of impurity diffusion and series resistance, a p-type hydrogenated amorphous silicon layer is preferable. On the other hand, the p-type oxide amorphous silicon layer is preferable as a wide-gap low refractive index layer in terms of reducing optical loss.
前記ｎ型シリコン系薄膜層は、例えばｎ型水素化非晶質シリコン、ｎ型微結晶シリコン、ｎ型シリコンナイトライドが例示されるが、ｉ型シリコン系薄膜層への製膜ダメージや不純物拡散の低減の観点から、中でもｎ型水素化非晶質シリコンが好ましい。 Examples of the n-type silicon thin film layer include n-type hydrogenated amorphous silicon, n-type microcrystalline silicon, and n-type silicon nitride. However, film formation damage and impurity diffusion to the i-type silicon thin film layer are exemplified. Of these, n-type hydrogenated amorphous silicon is particularly preferable.
電極層としては、入射側に関しては光に対して透明な透明電極である必要があり、透明電極の種類としては酸化錫、酸化亜鉛、酸化インジウム、酸化チタン等が上げられる。製膜温度及び抵抗／膜厚比、湿熱耐久性という観点から酸化インジウムが好ましい。裏面側に関しては金属からなる電極層を形成してもよいが、薄い基板の両面での応力を一致させるという観点から、入射側と略同等の透明電極を製膜することが好ましい。 The electrode layer needs to be a transparent electrode transparent to light on the incident side, and examples of the transparent electrode include tin oxide, zinc oxide, indium oxide, and titanium oxide. Indium oxide is preferable from the viewpoints of film forming temperature, resistance / film thickness ratio, and wet heat durability. An electrode layer made of metal may be formed on the back side, but it is preferable to form a transparent electrode substantially equivalent to that on the incident side from the viewpoint of matching the stress on both sides of the thin substrate.
前記電極層上には集電極が形成されうる。集電極は、インクジェット、スクリーン印刷、導線接着、スプレー等の公知技術によって作製できるが、生産性の観点からスクリーン印刷が好ましい。スクリーン印刷は金属粒子と樹脂バインダーからなる導電ペーストをスクリーン印刷によって印刷し、集電極を形成する工程が好ましく用いられうる。 A collecting electrode may be formed on the electrode layer. The collector electrode can be produced by a known technique such as ink jet, screen printing, wire bonding, spraying, etc., but screen printing is preferred from the viewpoint of productivity. For the screen printing, a process of forming a collecting electrode by printing a conductive paste composed of metal particles and a resin binder by screen printing can be preferably used.
集電極に用いられうる導電ペーストの固化も兼ねて、セルのアニールを行ってもよい。アニールによって、透明電極層（ＴＣＯ）の透過率／抵抗率比の向上、接触抵抗や界面準位の低減といった各界面特性の向上なども得られる。アニール温度としては非晶質シリコン系薄膜の製膜温度から１００℃前後の温度領域に留めることが好ましい。温度が高すぎると、導電型非晶質シリコン系薄膜層から真性非晶質シリコン系薄膜層へのドーパントの拡散、ＴＣＯからシリコン領域への異種元素の拡散による不純物準位の形成、非晶質シリコン中での欠陥準位の形成などによって、特性が悪化してしまう虞がある。 The cell may be annealed to solidify the conductive paste that can be used for the collector electrode. By annealing, improvement of the transmittance / resistivity ratio of the transparent electrode layer (TCO) and improvement of each interface characteristic such as reduction of contact resistance and interface state can be obtained. The annealing temperature is preferably kept within a temperature range of about 100 ° C. from the deposition temperature of the amorphous silicon thin film. If the temperature is too high, dopant diffusion from the conductive amorphous silicon thin film layer to the intrinsic amorphous silicon thin film layer, formation of impurity levels by diffusion of different elements from the TCO to the silicon region, amorphous There is a possibility that the characteristics deteriorate due to the formation of defect levels in silicon.
以下、本発明を実施例により具体的に説明するが、本発明は以下の実施例に限定されるものではない。 EXAMPLES Hereinafter, although an Example demonstrates this invention concretely, this invention is not limited to a following example.
（実施例１）
図１は、本発明に従う実施例１の結晶シリコン太陽電池を示す模式的断面図である。本実施例の結晶シリコン太陽電池はヘテロ接合太陽電池であり、ｎ型単結晶シリコン基板１の両面にそれぞれテクスチャを備えている。基板１表面の算術平均粗さは入射側で１４００ｎｍ、裏面側で２１００ｎｍである。本実施例における算術平均粗さはＡＦＭ（原子間力顕微鏡）によって確認するものである。ｎ型単結晶シリコン基板１の入射面にはｉ型非晶質シリコン層２／ｐ型非晶質シリコン層３／酸化インジウム層７が製膜されている。一方、基板１の裏面にはｉ型非晶質シリコン層４／ｎ型非晶質シリコン層５／酸化インジウム層６が製膜されている。酸化インジウム層６、７の上には集電極９、８が形成されている。
Example 1
FIG. 1 is a schematic cross-sectional view showing a crystalline silicon solar cell of Example 1 according to the present invention. The crystalline silicon solar cell of this example is a heterojunction solar cell, and has a texture on each side of the n-type single crystal silicon substrate 1. The arithmetic average roughness of the surface of the substrate 1 is 1400 nm on the incident side and 2100 nm on the back side. The arithmetic average roughness in this example is confirmed by AFM (atomic force microscope). An i-type amorphous silicon layer 2 / p-type amorphous silicon layer 3 / indium oxide layer 7 is formed on the incident surface of the n-type single crystal silicon substrate 1. On the other hand, an i-type amorphous silicon layer 4 / n-type amorphous silicon layer 5 / indium oxide layer 6 are formed on the back surface of the substrate 1. Collector electrodes 9 and 8 are formed on the indium oxide layers 6 and 7.
図１に示す実施例１の結晶シリコン太陽電池を以下のようにして製造した。 A crystalline silicon solar cell of Example 1 shown in FIG. 1 was produced as follows.
入射面の面方位が（１００）で、厚みが１５０μｍのｎ型単結晶シリコン基板を用いた。基板の入射面を粒度４０００の研磨シートで研磨した。次にアセトン中で洗浄した後、２重量％のＨＦ水溶液に５分間浸漬し、表面の酸化シリコン層を除去し、超純水によるリンスを２回行った。こうして準備した基板１を２枚用意し、１回目のエッチング工程として、研磨した入射面を貼り合わせ、７５℃に保持した５／１５重量％のＫＯＨ／イソプロピルアルコール水溶液に１５分間浸漬した。次に超純水によるリンスを２回行った後、張り合わせた二つの基板１を分離し２回目のエッチング工程として、７０℃に保持した５／２０重量％のＫＯＨ／イソプロピルアルコール水溶液に２０分間浸漬した。最後に、２重量％のＨＦ水溶液に５分間浸漬し、超純水によるリンスを２回行い、常温で乾燥させた。ＡＦＭ（パシフィックｎａｎｏｔｅｃｈ社製ｎａｎｏ―Ｒ）による単結晶シリコン基板１の表面観察を行ったところ、基板入射面には（１１１）面が露出した四角錐状のテクスチャ構造が形成されており、その算術平均粗さは１４００ｎｍであった。裏面も同様に（１１１）面で構成される四角錐状のテクスチャ構造が形成されていたが、算術平均粗さは２１００ｎｍであった。 An n-type single crystal silicon substrate having a plane orientation of the incident surface of (100) and a thickness of 150 μm was used. The incident surface of the substrate was polished with a polishing sheet having a particle size of 4000. Next, after washing in acetone, it was immersed in a 2% by weight HF aqueous solution for 5 minutes to remove the silicon oxide layer on the surface, and rinsed with ultrapure water twice. Two substrates 1 thus prepared were prepared, and as a first etching step, the polished incident surfaces were bonded together and immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 75 ° C. for 15 minutes. Next, after rinsing with ultrapure water twice, the two bonded substrates 1 are separated and immersed in a 5/20 wt% KOH / isopropyl alcohol aqueous solution kept at 70 ° C. for 20 minutes as a second etching step. did. Finally, it was immersed in a 2% by weight HF aqueous solution for 5 minutes, rinsed with ultrapure water twice, and dried at room temperature. When the surface of the single crystal silicon substrate 1 was observed by AFM (Nano-R manufactured by Pacific Nanotech), a square pyramid-like texture structure with an exposed (111) plane was formed on the substrate incident surface. The average roughness was 1400 nm. Similarly, a tetragonal pyramid texture structure composed of (111) planes was formed on the back surface, but the arithmetic average roughness was 2100 nm.
エッチングが終了した単結晶シリコン基板１をＣＶＤ装置へ導入し、入射面にｉ型非晶質シリコン層２を３ｎｍ製膜した。ｉ型非晶質シリコン層２の製膜条件は、基板温度が１７０℃、圧力１２０Ｐａ、ＳｉＨ4／Ｈ2流量比が３／１０、投入パワー密度が０．０３Ｗ／ｃｍ-2であった。ｉ型非晶質シリコン層２の上にｐ型非晶質シリコン層３を４ｎｍ製膜した。ｐ型非晶質シリコン層３の製膜条件は基板温度が１７０℃、圧力１３０Ｐａ、ＳｉＨ4／Ｈ2／Ｂ2Ｈ6流量比が１／１０／３、投入パワー密度が０．０４Ｗ／ｃｍ-2であった。なお、上記でいうＢ2Ｈ6ガスは、Ｂ2Ｈ6濃度を５０００ｐｐｍまでＨ2で希釈したガスを用いた。 After the etching, the single crystal silicon substrate 1 was introduced into a CVD apparatus, and an i-type amorphous silicon layer 2 was formed to a thickness of 3 nm on the incident surface. The film forming conditions for the i-type amorphous silicon layer 2 were a substrate temperature of 170 ° C., a pressure of 120 Pa, a SiH 4 / H 2 flow rate ratio of 3/10, and an input power density of 0.03 W / cm −2 . A p-type amorphous silicon layer 3 was formed to 4 nm on the i-type amorphous silicon layer 2. The deposition conditions of the p-type amorphous silicon layer 3 are as follows: the substrate temperature is 170 ° C., the pressure is 130 Pa, the SiH 4 / H 2 / B 2 H 6 flow rate ratio is 1/10/3, and the input power density is 0.04 W / cm. -2 . The B 2 H 6 gas used above was a gas diluted with H 2 to a B 2 H 6 concentration of 5000 ppm.
次に裏面側にｉ型非晶質シリコン層４を５ｎｍ製膜した。ｉ型非晶質シリコン層４の製膜条件は、基板温度が１７０℃、圧力１２０Ｐａ、ＳｉＨ4／Ｈ2流量比が３／１０、投入パワー密度が０．０３Ｗ／ｃｍ-2であった。ｉ型非晶質シリコン層４上にｎ型非晶質シリコン層５を７ｎｍ製膜した。ｎ型非晶質シリコン層５の製膜条件は、基板温度が１７０℃、圧力６０Ｐａ、ＳｉＨ4／ＰＨ3流量比が１／２、投入パワー密度が０．０２Ｗ／ｃｍ-2であった。なお、上記でいうＰＨ3ガスは、ＰＨ3濃度を５０００ｐｐｍまでＨ2で希釈したガスを用いた。次にｐ型非晶質シリコン層３とｎ型非晶質シリコン層５上へ酸化インジウム層７、６をスパッタリング法によって、それぞれ８０ｎｍと１００ｎｍ製膜した。スパッタリングターゲットはＩｎ2Ｏ3へＳｎを５％添加したものを用いた。両面の酸化インジウム層６、７上に、銀ペーストをスクリーン印刷し、櫛形電極を形成し、集電極８、９とした。 Next, 5 nm of i-type amorphous silicon layers 4 were formed on the back surface side. The film forming conditions for the i-type amorphous silicon layer 4 were a substrate temperature of 170 ° C., a pressure of 120 Pa, a SiH 4 / H 2 flow rate ratio of 3/10, and an input power density of 0.03 W / cm −2 . An n-type amorphous silicon layer 5 was formed on the i-type amorphous silicon layer 4 by 7 nm. The film forming conditions of the n-type amorphous silicon layer 5 were a substrate temperature of 170 ° C., a pressure of 60 Pa, a SiH 4 / PH 3 flow rate ratio of 1/2, and an input power density of 0.02 W / cm −2 . The PH 3 gas used above was a gas diluted with H 2 to a PH 3 concentration of 5000 ppm. Next, indium oxide layers 7 and 6 were formed on the p-type amorphous silicon layer 3 and the n-type amorphous silicon layer 5 by sputtering, respectively, with a thickness of 80 nm and 100 nm. As the sputtering target, In 2 O 3 added with 5% Sn was used. A silver paste was screen-printed on the indium oxide layers 6 and 7 on both sides to form comb-shaped electrodes.
（実施例２）
実施例２では、２回目のエッチング工程において、７０℃に保持した５／２５重量％のＫＯＨ／イソプロピルアルコール水溶液に３０分間浸漬した点、及びエッチング終了後の入射側表面の算術平均粗さが５００ｎｍであった点において実施例１と異なっていた。
(Example 2)
In Example 2, in the second etching step, the film was immersed in a 5/25 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 30 minutes, and the arithmetic average roughness of the incident side surface after etching was 500 nm. This was different from Example 1.
（実施例３）
実施例３では、２回目のエッチング工程において、７０℃に保持した５／２７重量％のＫＯＨ／イソプロピルアルコール水溶液に２０分間浸漬した点、及びエッチング終了後の入射側表面の算術平均粗さが２１０ｎｍであった点において実施例１と異なっていた。
(Example 3)
In Example 3, in the second etching step, the surface was immersed in a 5/27 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 20 minutes, and the arithmetic average roughness of the incident-side surface after etching was 210 nm. This was different from Example 1.
（実施例４）
実施例４では、基板の入射面を粒度６０００の研磨シートで研磨した点、２回目のエッチング工程において、７０℃に保持した５／２９重量％のＫＯＨ／イソプロピルアルコール水溶液に３０分間浸漬した点、及びエッチング終了後の入射側表面の算術平均粗さが１３０ｎｍであった点において実施例１と異なっていた。
Example 4
In Example 4, the incident surface of the substrate was polished with a polishing sheet having a particle size of 6000, and immersed in a 5/29 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 30 minutes in the second etching step. In addition, it was different from Example 1 in that the arithmetic average roughness of the incident side surface after etching was 130 nm.
（実施例５）
実施例５では、２回目のエッチング工程において、７０℃に保持した５／２７重量％のＫＯＨ／イソプロピルアルコール水溶液に２０分間浸漬した点、２重量％のＨＦ水溶液に浸漬させる前に純粋で２回リンスを行い酸素雰囲気中にて８９０℃で２時間焼成し表面を熱酸化させた点、エッチング終了後の入射側表面の算術平均粗さが１９０ｎｍで裏面側表面の算術平均粗さが２０８０ｎｍであった点において実施例１と異なっていた。
(Example 5)
In Example 5, in the second etching step, the sample was immersed in a 5/27 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 20 minutes, and purely twice before being immersed in a 2 wt% HF aqueous solution. The surface was thermally oxidized by rinsing at 890 ° C. for 2 hours in an oxygen atmosphere, the arithmetic average roughness of the incident side surface after the etching was 190 nm, and the arithmetic average roughness of the back side surface was 2080 nm. This was different from Example 1.
（比較例１）
比較例１では、研磨を行わなかった点、１回目のエッチング工程において、基板を張り合わせずに、７５℃に保持した５／１５重量％のＫＯＨ／イソプロピルアルコール水溶液に１３分間浸漬した点、２回目のエッチングを行わなかった点、エッチング終了後の算術平均粗さは入射面、裏面とも２１００ｎｍであった点においてのみ実施例１と異なっていた。なお、１回目のエッチング時間を変更しているのは、エッチング後の基板の厚みを同じにするためである。
(Comparative Example 1)
In Comparative Example 1, polishing was not performed, and in the first etching step, the substrates were not bonded to each other and immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 75 ° C. for 13 minutes. The arithmetic average roughness after the etching was different from that of Example 1 only in that the etching was not performed and the arithmetic average roughness after the etching was 2100 nm on both the incident surface and the back surface. The reason for changing the first etching time is to make the thickness of the substrate after etching the same.
（比較例２）
比較例２では、１４５μｍの基板を使用した点、両面を研磨した点、１回目のエッチング工程を行わなかった点、基板を張り合わせない状態で７０℃に保持した５／２７重量％のＫＯＨ／イソプロピルアルコール水溶液に２０分間浸漬した点、エッチング終了後の算術平均粗さは入射面、裏面とも２１０ｎｍであった点においてのみ実施例１と異なっていた。なお、厚みの異なる基盤を使用しているのは、エッチング後の基板の厚みを同じにするためである。
(Comparative Example 2)
In Comparative Example 2, 145 μm substrate was used, both surfaces were polished, the first etching step was not performed, and 5/27 wt% KOH / isopropyl held at 70 ° C. without bonding the substrates. Example 1 was different from Example 1 only in that it was immersed in an aqueous alcohol solution for 20 minutes and the arithmetic average roughness after completion of etching was 210 nm on both the incident surface and the back surface. The reason why the substrates having different thicknesses are used is to make the thickness of the substrate after etching the same.
（比較例３）
比較例３では、１４５μｍの基板を使用した点、研磨を行わなかった点、１回目のエッチング工程において、基板の周縁部２ｍｍを除く裏面側表面にマスクを用いて酸化シリコンからなるレジスト膜を製膜した後に７５℃に保持した５／１５重量％のＫＯＨ／イソプロピルアルコール水溶液に１５分間浸漬した点、２回目のエッチングを行わなかった点、エッチング終了後の算術平均粗さは入射面、及び裏面周縁部２ｍｍにおいて２１００ｎｍであった点においてのみ実施例１と異なっていた。なお、１回目のエッチング時間を変更しているのは、エッチング後の基板の厚みを同じにするためである。
(Comparative Example 3)
In Comparative Example 3, a 145 μm substrate was used, polishing was not performed, and in the first etching process, a resist film made of silicon oxide was manufactured using a mask on the back side surface excluding the peripheral edge 2 mm of the substrate. The film was immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 75 ° C. for 15 minutes, the second etching was not performed, and the arithmetic average roughness after the etching was calculated from the incident surface and the back surface It was different from Example 1 only in that it was 2100 nm at the peripheral part 2 mm. The reason for changing the first etching time is to make the thickness of the substrate after etching the same.
（比較例４）
比較例４では、１４０μｍの基板を使用した点、入射面及び側面周縁部を研磨した点、１回目のエッチング工程を行わなかった点、２回目のエッチングにおいて基板の周縁部２ｍｍを除く裏面側表面にマスクを用いて酸化シリコンからなるレジスト膜を製膜した後に７０℃に保持した５／２７重量％のＫＯＨ／イソプロピルアルコール水溶液に２０分間浸漬した点、エッチング終了後の算術平均粗さは入射面、及び裏面周縁部２ｍｍにおいて２１０ｎｍであった点においてのみ実施例１と異なっていた。なお、１回目のエッチング時間を変更しているのは、エッチング後の基板の厚みを同じにするためである。
(Comparative Example 4)
In Comparative Example 4, a point using a 140 μm substrate, a point where the incident surface and the side surface peripheral part were polished, a point where the first etching process was not performed, and a back side surface excluding the peripheral part 2 mm of the substrate in the second etching A resist film made of silicon oxide was formed using a mask and immersed in a 5/27 wt% KOH / isopropyl alcohol aqueous solution kept at 70 ° C. for 20 minutes. And the difference from Example 1 only in that it was 210 nm at the peripheral edge 2 mm of the back surface. The reason for changing the first etching time is to make the thickness of the substrate after etching the same.
（比較例５）
比較例５では、研磨を行わなかった点、１回目のエッチング工程において、基板を張り合わせずに、７５℃に保持した５／１５重量％のＫＯＨ／イソプロピルアルコール水溶液に１３分間浸漬した点、２回目のエッチングを行わなかった点、２重量％のＨＦ水溶液に浸漬させる前に純粋で２回リンスを行い酸素雰囲気中にて８９０℃で２時間焼成し表面を熱酸化させた点、エッチング終了後の算術平均粗さは入射面、裏面とも２０８０ｎｍであった点においてのみ実施例１と異なっていた。なお、１回目のエッチング時間を変更しているのは、エッチング後の基板の厚みを同じにするためである。
(Comparative Example 5)
In Comparative Example 5, polishing was not performed, and in the first etching step, the substrates were not bonded to each other and immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 75 ° C. for 13 minutes. The point where the etching was not performed, the surface was thermally oxidized at 890 ° C. for 2 hours by rinsing twice before being immersed in a 2 wt% HF aqueous solution, and the surface was thermally oxidized. The arithmetic average roughness was different from Example 1 only in that the incident surface and the back surface were 2080 nm. The reason for changing the first etching time is to make the thickness of the substrate after etching the same.
上記実施例及び比較例の太陽電池セルを充填材としてのＥＶＡ樹脂１０、保護ガラス板１２を基板として、保護フィルムとしてのＰＥＴフィルム１１をラミネートした上で光電変換特性の評価を行った。評価結果を表１に示す。 Photovoltaic conversion characteristics were evaluated after laminating a PET film 11 as a protective film with the EVA resin 10 as a filler and the protective glass plate 12 as a substrate using the solar cells of the above examples and comparative examples. The evaluation results are shown in Table 1.
実施例１〜４及び比較例１〜４を比較すると入射面の算術平均粗さが２１０ｎｍのときに変換効率（Ｅｆｆ）が最大となり、いずれの実施例も変換効率でどの比較例よりも高い値を示している。開放電圧（Ｖｏｃ）と曲線因子（ＦＦ）は算術平均粗さが小さいほど高い値を示しており、入射側の算術平均粗さの影響の方が強い。これは、四角錐状のテクスチャ構造で構成される領域では、入射面に対して法線方向に存在する内部電位の勾配が特に弱くなるためである。入射側界面では短波長光のキャリアの生成が集中するので入射側界面の形状は裏面と比較して影響が強い。 When Examples 1-4 and Comparative Examples 1-4 are compared, when the arithmetic mean roughness of the incident surface is 210 nm, the conversion efficiency (Eff) is maximized, and any of the Examples has a higher conversion efficiency than any of the comparative examples. Is shown. The open circuit voltage (Voc) and the fill factor (FF) show higher values as the arithmetic mean roughness is smaller, and the influence of the arithmetic mean roughness on the incident side is stronger. This is because the gradient of the internal potential existing in the normal direction with respect to the incident surface is particularly weak in a region constituted by a quadrangular pyramid texture structure. Since the generation of short wavelength light carriers is concentrated at the incident side interface, the shape of the incident side interface has a stronger influence than the back side.
入射側算術平均粗さが２１０ｎｍである実施例３、比較例２、比較例４を比較すると、裏面側算術平均粗さが２１０ｎｍか０ｎｍの比較例２及び４において、実施例３よりも短絡電流（Ｉｓｃ）が１．５ｍＡ程度減少しており、変換効率もこれに伴い低下している。これは長波長光が散乱されずにセル外へ放出されるためである。 Comparing Example 3, Comparative Example 2, and Comparative Example 4 where the incident-side arithmetic average roughness is 210 nm, in Comparative Examples 2 and 4 where the back-side arithmetic average roughness is 210 nm or 0 nm, the short-circuit current is higher than that of Example 3. (Isc) has decreased by about 1.5 mA, and the conversion efficiency has also decreased. This is because long wavelength light is emitted outside the cell without being scattered.
実施例１、２、３、４、５と比較例１、３と比較すると、開放電圧と短絡電流が実施例において向上している。開放電圧は上記と同様に入射側算術平均粗さによるキャリア回収効率の差を反映しており、短絡電流の違いは屈折率１．５のＥＶＡ樹脂と屈折率１．９の酸化インジウムで構成される界面の形状の違いによる光学特性の違いを反映している。ＥＶＡ樹脂／酸化インジウム／シリコンからなる屈折率構成では干渉による反射率低減効果は十分得られない。そして短波長光は算術平均粗さの大きい界面では幾何光学的に振る舞うため、波長によっては反射が生じてしまい短絡電流が低下するのである。その一方で実施例に用いられている、入射側算術平均粗さの小さい界面形状では、短波長光が界面を認識できないため広い波長域に渡って反射を低減できる。 Compared with Examples 1, 2, 3, 4, 5 and Comparative Examples 1, 3, the open-circuit voltage and the short-circuit current are improved in the Examples. The open-circuit voltage reflects the difference in carrier recovery efficiency due to the incident side arithmetic mean roughness as described above, and the short-circuit current difference is composed of EVA resin with a refractive index of 1.5 and indium oxide with a refractive index of 1.9. This reflects the difference in optical characteristics due to the difference in the shape of the interface. In the refractive index configuration composed of EVA resin / indium oxide / silicon, the reflectance reduction effect due to interference cannot be obtained sufficiently. Short-wavelength light behaves geometrically at the interface with a large arithmetic average roughness, so that reflection occurs depending on the wavelength and the short-circuit current decreases. On the other hand, in the interface shape having a small incident side arithmetic average roughness used in the embodiment, since the short wavelength light cannot recognize the interface, reflection can be reduced over a wide wavelength range.
特に実施例３〜５と比較例１、５を比較すると、実施例３、４に対する実施例５の開放電圧の向上幅が比較例１に対する比較例５の向上幅よりも大きい。実施例５が入射側算術平均粗さのより小さい実施例４よりも開放電圧が向上していること、比較例５がほぼ同じ入射側算術平均粗さである比較例１よりも開放電圧が向上していることを鑑みると、入射側算術平均粗さが小さくなる以外の効果で開放電圧が向上している。またこの開放電圧向上効果は実施例での向上幅と比較例での向上幅の違いから、実施例のように入射側算術平均粗さの小さいほど効果があるといえる。実施例５は実施例３に、比較例５は比較例１にそれぞれテクスチャ形成後に熱酸化工程を加えたもので、形成された熱酸化皮膜は最後のＨＦ水溶液への浸漬工程で取り除かれている。この熱酸化皮膜の形成及び除去工程を経ることで、表面に形成された熱酸化皮膜の厚みがテクスチャ頂点で厚く、谷部で薄くなる厚み分布によって、熱酸化皮膜除去後の四角錐状のテクスチャ構造の辺、頂点、谷部が丸みを帯びる。この結果、丸みを帯びる辺の長さ及び頂点の数は酸化皮膜形成・除去工程の前の初期算術平均粗さに反比例する。四角錐状のテクスチャ構造の辺で、特に四角錐の底面を構成する谷部の辺では、非晶質シリコン膜を製膜する際に局所的に製膜速度が変動し、欠陥が生じやすい。この谷部を構成する辺の長さは、上述したように算術平均粗さの小さい、つまり四角錐状のテクスチャ構造の平均サイズが小さい表面ほど長いので、非晶質シリコン層を製膜する際の欠陥発生点が多いと考えられる。酸化皮膜の形成・除去工程を経ることで、欠陥発生点が低減できその度合いはテクスチャ構造の小さい実施例では比較的大きい。 In particular, when Examples 3 to 5 are compared with Comparative Examples 1 and 5, the improvement width of the open circuit voltage of Example 5 with respect to Examples 3 and 4 is larger than the improvement width of Comparative Example 5 with respect to Comparative Example 1. Example 5 shows that the open-circuit voltage is improved over Example 4 with a smaller incident-side arithmetic average roughness, and the open-circuit voltage is improved over Comparative Example 1 where Comparative Example 5 has substantially the same incident-side arithmetic average roughness. In view of this, the open-circuit voltage is improved by an effect other than the reduction of the incident side arithmetic average roughness. Moreover, it can be said that the effect of improving the open circuit voltage is more effective as the incident side arithmetic average roughness is smaller as in the embodiment, because of the difference between the improvement width in the embodiment and the improvement width in the comparative example. Example 5 is the same as Example 3, and Comparative Example 5 is the same as Comparative Example 1 except that a thermal oxidation step is added after texture formation, and the formed thermal oxide film is removed in the final immersion step in HF aqueous solution. . Through this thermal oxide film formation and removal process, the thickness of the thermal oxide film formed on the surface is thick at the top of the texture and thinned at the valleys, resulting in a square pyramid texture after removal of the thermal oxide film. The sides, vertices, and valleys of the structure are rounded. As a result, the length of the rounded side and the number of vertices are inversely proportional to the initial arithmetic average roughness before the oxide film formation / removal step. When the amorphous silicon film is formed on the sides of the quadrangular pyramid-shaped texture structure, particularly on the sides of the valleys that form the bottom of the quadrangular pyramid, defects are likely to occur. As described above, the length of the side constituting the valley is longer as the surface has a smaller arithmetic average roughness, that is, a smaller average size of the square pyramid texture structure. It is thought that there are many defect occurrence points. Through the oxide film formation / removal step, the number of defect occurrence points can be reduced, and the degree thereof is relatively large in an embodiment having a small texture structure.
このように屈折率が約１．５のＥＶＡ樹脂で太陽電池を封止した状態で、光電変換特性を評価した結果より、本発明によって太陽電池の開放電圧と短絡電流がバランスよく改善し、変換効率が向上することがわかる。 As a result of evaluating photoelectric conversion characteristics in a state where the solar cell is sealed with an EVA resin having a refractive index of about 1.5 as described above, the open voltage and short-circuit current of the solar cell are improved in a balanced manner according to the present invention. It can be seen that the efficiency is improved.
１．ｎ型単結晶シリコン基板
２．ｉ型非晶質シリコン層
３．ｐ型非晶質シリコン層
４．ｉ型非晶質シリコン層
５．ｎ型非晶質シリコン層
６．酸化インジウム層
７．酸化インジウム層
８．集電極
９．集電極
１０．ＥＶＡ樹脂
１１．ＰＥＴフィルム
１２．保護ガラス
1. 1. n-type single crystal silicon substrate 2. i-type amorphous silicon layer 3. p-type amorphous silicon layer 4. i-type amorphous silicon layer n-type amorphous silicon layer 6. 6. Indium oxide layer Indium oxide layer 8. Collector electrode 9. Collector electrode 10. EVA resin 11. PET film 12. Protective glass
Claims (6)
前記基板の厚みが１５０μｍ以下であり、前記基板の入射側表面及び裏面側表面に四角錐で構成されるテクスチャ構造を備え、前記基板の入射側表面における算術平均粗さが１５００ｎｍ以下であり、裏面側表面の算術平均粗さが２０００ｎｍ以上であることを特徴とする結晶シリコン太陽電池。 A single conductivity type single crystal silicon substrate, a p-type silicon thin film layer on one surface of the substrate, and a substantially authentic silicon thin film layer between the substrate and the p-type silicon thin film layer; A crystalline silicon solar cell having an n-type silicon-based thin film layer on the other surface of the substrate, and a substantially authentic silicon-based thin film layer between the substrate and the n-type silicon thin film layer;
The substrate has a thickness of 150 μm or less, has a texture structure composed of quadrangular pyramids on the incident side surface and the back side surface of the substrate, and has an arithmetic average roughness of 1500 nm or less on the incident side surface of the substrate, An arithmetic average roughness of the side surface is 2000 nm or more.
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012133692A1 (en) * | 2011-03-31 | 2012-10-04 | 京セラ株式会社 | Solar cell element and solar cell module |
| JP2013518425A (en) * | 2010-01-27 | 2013-05-20 | コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブ | Method for producing photovoltaic cell including pretreatment of the surface of a crystalline silicon substrate |
| KR101335082B1 (en) * | 2012-02-01 | 2013-12-03 | 현대중공업 주식회사 | Method for fabricating bi-facial solar cell |
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| WO2015159456A1 (en) * | 2014-04-16 | 2015-10-22 | 三菱電機株式会社 | Solar cell and solar cell manufacturing method |
| JP2016072522A (en) * | 2014-09-30 | 2016-05-09 | 株式会社カネカ | Manufacturing method of silicon substrate for solar cell, manufacturing method of solar cell, and manufacturing method of solar cell module |
| JP2016139834A (en) * | 2011-07-25 | 2016-08-04 | 日立化成株式会社 | Solar cell substrate, manufacturing method of the same, solar cell element, and solar cell |
| JP2018113462A (en) * | 2013-02-26 | 2018-07-19 | パナソニックＩｐマネジメント株式会社 | Solar cell module |
| KR101923728B1 (en) | 2013-02-06 | 2018-11-29 | 한국전자통신연구원 | Solar cell |
| US10276738B2 (en) | 2010-01-27 | 2019-04-30 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Photovoltaic cell, including a crystalline silicon oxide passivation thin film, and method for producing same |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145816A (en) * | 1987-12-04 | 1989-06-07 | Nissan Motor Co Ltd | Wet etching |
| JPH01154570A (en) * | 1987-12-10 | 1989-06-16 | Mitsubishi Electric Corp | Photovoltaic element |
| JPH0766437A (en) * | 1993-08-30 | 1995-03-10 | Tonen Corp | Manufacture of substrate for photoelectric transducer |
| JPH10150209A (en) * | 1996-09-19 | 1998-06-02 | Canon Inc | Photoelectric conversion element |
| JP2001023947A (en) * | 1999-07-05 | 2001-01-26 | Canon Inc | Method for etching semiconductor wafer, manufacture of semiconductor thin film and apparatus for holding semiconductor wafer |
| JP2001345460A (en) * | 2000-03-29 | 2001-12-14 | Sanyo Electric Co Ltd | Solar cell device |
| JP2002222969A (en) * | 2001-01-25 | 2002-08-09 | Sharp Corp | Laminated solar battery |
| JP2002319688A (en) * | 2001-04-20 | 2002-10-31 | Sharp Corp | Laminated solar battery |
| JP2003069061A (en) * | 2001-08-24 | 2003-03-07 | Sharp Corp | Laminated photovoltaic transducer device |
| JP2005142268A (en) * | 2003-11-05 | 2005-06-02 | Canon Inc | Photovoltaic element and its manufacturing method |
| JP2005311222A (en) * | 2004-04-26 | 2005-11-04 | Toppan Printing Co Ltd | Substrate for solar battery, thin film solar battery and electronic equipment |
| JP2007141967A (en) * | 2005-11-15 | 2007-06-07 | Sanyo Electric Co Ltd | Photovoltaic element, photovoltaic module, and method of manufacturing photovoltaic element |
| JP2008034686A (en) * | 2006-07-31 | 2008-02-14 | Toppan Printing Co Ltd | Photoelectric conversion device and manufacturing method thereof |
-
2009
- 2009-09-10 JP JP2009209557A patent/JP5537101B2/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145816A (en) * | 1987-12-04 | 1989-06-07 | Nissan Motor Co Ltd | Wet etching |
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