JP2011014681A - 半導体装置の製造方法 - Google Patents
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Abstract
【解決手段】半導体基板35に検査用パターン37及び半導体チップ11を形成し、次いで、検査用端子接続面39A、電極パッド23の接続面23A、及び保護膜25上に、感光性レジスト膜41を形成し、次いで、感光性レジスト膜41を、マスク(図示せず)を介して露光し、その後、現像処理することで、感光性レジスト膜41に、検査用パターン37及び切断領域Cよりも幅広形状とされた貫通溝43を形成し、次いで、感光性レジスト膜を41介したウエットブラスト処理により、検査用パターン37を除去すると共に、貫通溝43と対向する部分の保護膜25、及び貫通溝51と対向する部分の半導体基板35に溝51を一括形成する。
【選択図】図14
Description
前記スクライブ領域に対応する部分の前記半導体基板の第1の面に配置され、検査用端子接続面を有し、電気特性を検査するための検査用パターンと、複数の前記半導体チップ形成領域に対応する部分の前記半導体基板の第1の面に配置される半導体素子、該半導体素子と電気的に接続され、接続面を有する電極パッド、及び前記半導体素子を覆うと共に、前記電極パッドの接続面及び前記検査用端子接続面を露出する保護膜を有する半導体チップと、を形成する検査用パターン及び半導体チップ形成工程と、
前記検査用端子接続面、前記電極パッドの接続面、及び前記保護膜上に、レジスト膜を形成するレジスト膜形成工程と、
前記レジスト膜に、前記スクライブ領域よりも幅が狭く、かつ前記検査用パターン及び前記切断領域よりも幅広形状とされた貫通溝を形成する貫通溝形成工程と、
前記貫通溝形成工程後に、前記レジスト膜を介したウエットブラスト処理により、前記検査用パターンを除去すると共に、前記貫通溝と対向する部分の前記保護膜、及び前記貫通溝と対向する部分の前記半導体基板に溝を一括形成する検査パターン除去及び溝形成工程と、
前記検査パターン除去及び溝形成工程後に前記レジスト膜を除去するレジスト膜除去工程と、
前記レジスト膜除去工程後に前記電極パッドの接続面に内部接続端子を形成する内部接続端子形成工程と、
シート状絶縁樹脂を前記内部接続端子、前記保護膜、及び前記溝に圧着させることで、前記内部接続端子に平坦な接続面を形成すると共に、前記シート状絶縁樹脂で充填して、前記シート状絶縁樹脂を母材とする絶縁樹脂層を形成する絶縁樹脂層形成工程と、
前記内部接続端子の接続面が露出するまで前記絶縁樹脂層を除去することで、前記絶縁樹脂層に配線形成面を形成する配線形成面形成工程と、
前記配線形成面に前記内部接続端子の接続面と接続された配線パターンを形成する配線パターン形成工程と、
前記配線パターン形成工程後に、複数の前記半導体素子を個片化する切断工程と、を含むことを特徴とする半導体装置の製造方法が提供される。
図9は、本発明の実施の形態に係る半導体装置の断面図である。
11 半導体チップ
13 内部接続端子
13A 接続面
14 絶縁樹脂層
15 配線パターン
17 ソルダーレジスト層
18 外部接続端子
21 半導体基板
21A 素子形成面
22 半導体素子
22A,25A,41A 上面
22B 側面
23 電極パッド
23A 接続面
25 保護膜
27 切り欠き部
31 外部接続用パッド部
31A 端子接続面
33 開口部
35 半導体基板
35A,35B,53A 面
37 検査パターン
38 検査用パターン本体
39 検査用電極
39A 検査用端子接続面
43 貫通溝
45 ウエットブラスト装置
46 噴射ノズル
47 液体
48 粒子
51 溝
53 平板
A 半導体チップ形成領域
B スクライブ領域
C 切断領域
D,E,F 幅
Claims (5)
- 複数の半導体チップ形成領域と、複数の前記半導体チップ形成領域を囲むスクライブ領域と、該スクライブ領域に設けられ、該スクライブ領域よりも幅の狭い切断領域とを備えた半導体基板を準備する半導体基板準備工程と、
前記スクライブ領域に対応する部分の前記半導体基板の第1の面に配置され、検査用端子接続面を有し、電気特性を検査するための検査用パターンと、複数の前記半導体チップ形成領域に対応する部分の前記半導体基板の第1の面に配置される半導体素子、該半導体素子と電気的に接続され、接続面を有する電極パッド、及び前記半導体素子を覆うと共に、前記電極パッドの接続面及び前記検査用端子接続面を露出する保護膜を有する半導体チップと、を形成する検査用パターン及び半導体チップ形成工程と、
前記検査用端子接続面、前記電極パッドの接続面、及び前記保護膜上に、レジスト膜を形成するレジスト膜形成工程と、
前記レジスト膜に、前記スクライブ領域よりも幅が狭く、かつ前記検査用パターン及び前記切断領域よりも幅広形状とされた貫通溝を形成する貫通溝形成工程と、
前記貫通溝形成工程後に、前記レジスト膜を介したウエットブラスト処理により、前記検査用パターンを除去すると共に、前記貫通溝と対向する部分の前記保護膜、及び前記貫通溝と対向する部分の前記半導体基板に溝を一括形成する検査パターン除去及び溝形成工程と、
前記検査パターン除去及び溝形成工程後に前記レジスト膜を除去するレジスト膜除去工程と、
前記レジスト膜除去工程後に前記電極パッドの接続面に内部接続端子を形成する内部接続端子形成工程と、
シート状絶縁樹脂を前記内部接続端子、前記保護膜、及び前記溝に圧着させることで、前記内部接続端子に平坦な接続面を形成すると共に、前記シート状絶縁樹脂で充填して、前記シート状絶縁樹脂を母材とする絶縁樹脂層を形成する絶縁樹脂層形成工程と、
前記内部接続端子の接続面が露出するまで前記絶縁樹脂層を除去することで、前記絶縁樹脂層に配線形成面を形成する配線形成面形成工程と、
前記配線形成面に前記内部接続端子の接続面と接続された配線パターンを形成する配線パターン形成工程と、
前記配線パターン形成工程後に、複数の前記半導体素子を個片化する切断工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記レジスト膜は、感光性レジスト膜であり、
前記貫通溝形成工程では、前記感光性レジスト膜を、マスクを介して露光し、その後、露光された前記感光性レジスト膜を現像処理することで、前記貫通溝を形成することを特徴とする請求項1記載の半導体装置の製造方法。 - 前記溝は、連続する1つの溝であることを特徴とする請求項1または2記載の半導体装置の製造方法。
- 前記配線パターンは、外部接続端子が配設させる端子接続面を有した外部接続用パッド部を有しており、
前記配線パターン形成工程と前記切断工程との間に、前記配線パターン形成面に、前記端子接続面を露出する開口部を有したソルダーレジスト層を形成するソルダーレジスト層形成工程と、
前記ソルダーレジスト層形成工程後、前記端子接続面に前記外部接続端子を形成する外部接続端子形成工程と、を設け、
前記切断工程では、前記切断領域に対応する部分の前記半導体基板、前記絶縁樹脂層、及び前記ソルダーレジスト層を切断することを特徴とする請求項1ないし3のうち、いずれか1項記載の半導体装置の製造方法。 - 前記外部接続端子形成工程と前記切断工程との間に、前記半導体基板の第1の面の反対側に位置する前記半導体基板の第2の面側から前記半導体基板を薄板化する半導体基板薄板化工程をさらに設けたことを特徴とする請求項4記載の半導体装置。
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