JP2010238747A - 不揮発性半導体記憶装置 - Google Patents
不揮発性半導体記憶装置 Download PDFInfo
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- JP2010238747A JP2010238747A JP2009082346A JP2009082346A JP2010238747A JP 2010238747 A JP2010238747 A JP 2010238747A JP 2009082346 A JP2009082346 A JP 2009082346A JP 2009082346 A JP2009082346 A JP 2009082346A JP 2010238747 A JP2010238747 A JP 2010238747A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 230000015654 memory Effects 0.000 claims abstract description 243
- 239000013078 crystal Substances 0.000 claims abstract description 60
- 230000007547 defect Effects 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 claims description 134
- 239000011229 interlayer Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 11
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- SFXFPRFVFALOCV-UHFFFAOYSA-N silicon;tetraethyl silicate Chemical compound [Si].CCO[Si](OCC)(OCC)OCC SFXFPRFVFALOCV-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】
下部半導体層100と、下部半導体層100上に形成された複数のメモリセルM100−M116から構成されるセルストリングCS100と、下部半導体層100上に形成された上部半導体層200と、上部半導体層200上に形成された複数のメモリセルM200−M216から構成されるセルストリングCS200とを備え、データ書き込み動作時及び読み出し動作時に、セルストリングCS200を構成する複数のメモリセルM200−M216のうち、上部半導体層200の結晶欠陥50a上に形成されたメモリセルM208をダミーセルとして動作させることを特徴とする。
【選択図】 図2
Description
20 素子分離領域
50a、50b 結晶欠陥
60 絶縁膜
61 多結晶シリコン層
62 パット窒化膜
M100−M116、M200−M216、M100−M118、M200−M218 メモリセル
SG201、SG202 選択ゲートトランジスタ
WL200−WL216 ワード線
GL201、GL202 選択ゲート線
CS100、CS200 セルストリング
100 下部半導体層
200 上部半導体層
110 N型拡散層
121 ゲート絶縁膜
122 浮遊ゲート電極
123 ゲート間絶縁膜
124 制御ゲート電極
125 シリサイド層
126 側壁絶縁膜
122s、124s ゲート電極
140,240 層間絶縁膜
150、160、250、260 開口部
300 ソース線
310 ビット線
Claims (4)
- 下部半導体層と、
前記下部半導体層上に形成された複数のメモリセルを有する第1セルストリングと、
前記下部半導体層上に層間絶縁膜を介して形成された少なくとも1層以上の上部半導体層と、
前記上部半導体層上に形成された複数のメモリセルを有する第2セルストリングとを備え、
データ書き込み動作時及び読み出し動作時に、前記第2セルストリングを構成する複数のメモリセルのうち、前記上部半導体層の結晶欠陥上に形成されたメモリセルをダミーセルとして動作させることを特徴とする不揮発性半導体記憶装置。 - 前記上部半導体層の結晶欠陥上に形成されダミーセルとして動作するメモリセルが、前記第2セルストリングの中央に配置されたメモリセルであることを特徴とする請求項1記載の不揮発性半導体記憶装置。
- 前記上部半導体層の結晶欠陥上に形成されダミーセルとして動作するメモリセルと対応する、前記下部半導体層上に形成されたメモリセルを、データ書き込み動作時及び読み出し動作時に、ダミーセルとして動作させることを特徴とする請求項1または2記載の不揮発性半導体記憶装置。
- データ書き込み動作時及び読み出し動作時に、前記第1セルストリング及び前記第2セルストリングの両端に配置されたメモリセルをダミーセルとして動作させることを特徴とする請求項1乃至3いずれか1項に記載の不揮発性半導体記憶装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009082346A JP2010238747A (ja) | 2009-03-30 | 2009-03-30 | 不揮発性半導体記憶装置 |
US12/748,743 US20100246256A1 (en) | 2009-03-30 | 2010-03-29 | Nonvolatile semiconductor memory |
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JP2009082346A JP2010238747A (ja) | 2009-03-30 | 2009-03-30 | 不揮発性半導体記憶装置 |
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JP2010238747A true JP2010238747A (ja) | 2010-10-21 |
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JP2009082346A Pending JP2010238747A (ja) | 2009-03-30 | 2009-03-30 | 不揮発性半導体記憶装置 |
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US (1) | US20100246256A1 (ja) |
JP (1) | JP2010238747A (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004127346A (ja) * | 2002-09-30 | 2004-04-22 | Toshiba Corp | 不揮発性半導体メモリ装置 |
JP2007329366A (ja) * | 2006-06-09 | 2007-12-20 | Toshiba Corp | 半導体記憶装置 |
JP2008098641A (ja) * | 2006-10-11 | 2008-04-24 | Samsung Electronics Co Ltd | Nandフラッシュメモリー装置及びその製造方法 |
JP2008159804A (ja) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | 不揮発性半導体メモリ |
JP2009010041A (ja) * | 2007-06-26 | 2009-01-15 | Toshiba Corp | 半導体記憶装置の製造方法 |
-
2009
- 2009-03-30 JP JP2009082346A patent/JP2010238747A/ja active Pending
-
2010
- 2010-03-29 US US12/748,743 patent/US20100246256A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004127346A (ja) * | 2002-09-30 | 2004-04-22 | Toshiba Corp | 不揮発性半導体メモリ装置 |
JP2007329366A (ja) * | 2006-06-09 | 2007-12-20 | Toshiba Corp | 半導体記憶装置 |
JP2008098641A (ja) * | 2006-10-11 | 2008-04-24 | Samsung Electronics Co Ltd | Nandフラッシュメモリー装置及びその製造方法 |
JP2008159804A (ja) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | 不揮発性半導体メモリ |
JP2009010041A (ja) * | 2007-06-26 | 2009-01-15 | Toshiba Corp | 半導体記憶装置の製造方法 |
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