JP2010147051A - Semiconductor integrated circuit device, and method of manufacturing the same - Google Patents

Semiconductor integrated circuit device, and method of manufacturing the same Download PDF

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Publication number
JP2010147051A
JP2010147051A JP2008319355A JP2008319355A JP2010147051A JP 2010147051 A JP2010147051 A JP 2010147051A JP 2008319355 A JP2008319355 A JP 2008319355A JP 2008319355 A JP2008319355 A JP 2008319355A JP 2010147051 A JP2010147051 A JP 2010147051A
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Prior art keywords
film
integrated circuit
semiconductor integrated
circuit device
item
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JP2008319355A
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JP2010147051A5 (en
Inventor
Hiroshi Tsukamoto
博 塚本
Hiromi Abe
宏美 阿部
Katsunari Iwama
克成 岩間
Akira Yajima
明 矢島
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2008319355A priority Critical patent/JP2010147051A/en
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Publication of JP2010147051A5 publication Critical patent/JP2010147051A5/ja
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Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a device having a rewiring structure above an aluminum-based bonding pad on a semiconductor chip principally adopts external connections with bump electrodes but, with prevailing needs for external connections by wire bonding for such a device, a technique of forming an electroless-plated gold-plating surface film for bonding on an electroless-plated metal rewiring lamination to bond a wire to the surface film is conceived, and this electroless plating based technique does not ensure resistance against diffusion and impact, so that reliable devices and processes can not be provided without difficulty. <P>SOLUTION: A device includes a rewiring structure above an aluminum-based bonding pad on a semiconductor chip 1. An electroless-plated wire bonding gold pad layer 15 is formed on the rewiring structure. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体集積回路装置（または半導体装置）のデバイス構造および半導体集積回路装置（または半導体装置）の製造方法における外部接続技術に適用して有効な技術に関する。   The present invention relates to a technology effective when applied to a device structure of a semiconductor integrated circuit device (or a semiconductor device) and an external connection technology in a method for manufacturing the semiconductor integrated circuit device (or a semiconductor device).

日本特開２００７−７３６１１号公報（特許文献１）には、半導体チップ上のアルミニウム系ボンディング・パッド上方の再配線最上層である無電界メッキによるニッケル膜上に、無電界メッキによる金層を形成し、そこにボンディング・ワイヤを接続する技術が開示されている。   In Japanese Unexamined Patent Publication No. 2007-73611 (Patent Document 1), a gold layer by electroless plating is formed on a nickel film by electroless plating, which is the uppermost layer of a rewiring above an aluminum-based bonding pad on a semiconductor chip. And the technique of connecting a bonding wire there is disclosed.

特開２００７−７３６１１号公報JP 2007-73611 A

半導体チップ上のアルミニウム系等のボンディング・パッド上方に再配線構造を有するデバイスにおいては、一般にバンプ電極による外部接続が主要な構造である。一方、このようなデバイスにおいても、ワイヤ・ボンディングにより外部接続をとりたいというニーズが広く存在する。そこで、日本特開２００７−７３６１１号公報（特許文献１）に開示されたように、無電界メッキによる積層金属再配線上に更に無電界メッキによってボンディング用の金メッキ表面膜を設け、そこにワイヤをボンディングする技術が考えられている。   In a device having a rewiring structure above an aluminum-based bonding pad on a semiconductor chip, external connection by a bump electrode is generally the main structure. On the other hand, even in such a device, there is a wide need for external connection by wire bonding. Therefore, as disclosed in Japanese Patent Application Laid-Open No. 2007-73611 (Patent Document 1), a gold-plated surface film for bonding is further provided by electroless plating on the multilayer metal rewiring by electroless plating, and a wire is provided there. A bonding technique is considered.

しかし、このような無電界メッキ・ベースの技術では、耐拡散性および耐衝撃性等を十分に確保することができず、高信頼性のデバイス及びプロセスを提供することが困難である。   However, such electroless plating-based technology cannot sufficiently secure diffusion resistance and impact resistance, and it is difficult to provide a highly reliable device and process.

本願発明は、これらの課題を解決するためになされたものである。   The present invention has been made to solve these problems.

本発明の目的は、高信頼性の半導体集積回路装置または半導体集積回路装置の製造プロセスを提供することにある。   An object of the present invention is to provide a highly reliable semiconductor integrated circuit device or a manufacturing process of a semiconductor integrated circuit device.

本発明の前記並びにその他の目的と新規な特徴は本明細書の記述及び添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば下記の通りである。   The following is a brief description of an outline of typical inventions disclosed in the present application.

すなわち、本願発明は半導体チップ上のアルミニウム系等のボンディング・パッド上方に再配線構造を有するデバイスにおいて、再配線上に電解メッキによるワイヤ・ボンディング用の金パッド層を形成するものである。   That is, according to the present invention, in a device having a rewiring structure above an aluminum-based bonding pad on a semiconductor chip, a gold pad layer for wire bonding by electrolytic plating is formed on the rewiring.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記のとおりである。   The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

すなわち、半導体チップ上のアルミニウム系等のボンディング・パッド上方に再配線構造を有するデバイスにおいて、再配線上に電解メッキによるワイヤ・ボンディング用の金パッド層を形成するので、膜質が良好で十分に厚いパッド膜とすることができる。   That is, in a device having a rewiring structure above an aluminum-based bonding pad on a semiconductor chip, a gold pad layer for wire bonding by electrolytic plating is formed on the rewiring, so that the film quality is good and sufficiently thick It can be a pad film.

〔実施の形態の概要〕
先ず、本願において開示される発明の代表的な実施の形態について概要を説明する。 [Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

１．以下の工程を含む半導体集積回路装置の製造方法：
（ａ）半導体ウエハのデバイス面上の多層配線層上に、第1のパッド電極を形成する工程；
（ｂ）前記工程（ａ）の後、前記半導体ウエハの前記デバイス面側を第1の絶縁膜で被覆する工程；
（ｃ）前記工程（ｂ）の後、前記第1のパッド電極上の前記第1の絶縁膜にパッド開口を形成する工程；
（ｄ）前記工程（ｃ）の後、前記半導体ウエハの前記デバイス面側にシード・メタル層を形成する工程；
（ｅ）前記工程（ｄ）の後、前記シード・メタル層上に、前記パッド開口を内部に含む第1のレジスト膜開口を有する第1のレジスト膜パターンを形成する工程；
（ｆ）前記工程（ｅ）の後、前記シード・メタル層上の前記第1のレジスト膜開口内に、電解メッキにより、再配線金属層を形成する工程；
（ｇ）前記工程（ｆ）の後、前記再配線金属層上に第２のレジスト膜開口を有する第２のレジスト膜パターンを、前記シード・メタル層および前記再配線金属層上に、形成する工程；
（ｈ）前記工程（ｇ）の後、前記再配線金属層上の前記第２のレジスト膜開口内に、電解メッキにより、金を主要な成分とする第２のパッド電極を形成する工程；
（ｉ）前記工程（ｈ）の後、前記第２のレジスト膜パターンを除去する工程。 1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a first pad electrode on the multilayer wiring layer on the device surface of the semiconductor wafer;
(B) After the step (a), a step of coating the device surface side of the semiconductor wafer with a first insulating film;
(C) after the step (b), forming a pad opening in the first insulating film on the first pad electrode;
(D) a step of forming a seed metal layer on the device surface side of the semiconductor wafer after the step (c);
(E) After the step (d), forming a first resist film pattern having a first resist film opening including the pad opening on the seed metal layer;
(F) After the step (e), a step of forming a redistribution metal layer in the first resist film opening on the seed metal layer by electrolytic plating;
(G) After the step (f), a second resist film pattern having a second resist film opening is formed on the redistribution metal layer on the seed metal layer and the redistribution metal layer. Process;
(H) After the step (g), forming a second pad electrode containing gold as a main component by electrolytic plating in the opening of the second resist film on the redistribution metal layer;
(I) A step of removing the second resist film pattern after the step (h).

２．前記１項の半導体集積回路装置の製造方法において、更に以下の工程を含む：
（ｊ）前記工程（ｉ）の後、前記半導体ウエハを半導体チップに分割する工程；
（ｋ）前記工程（ｊ）の後、前記半導体チップの裏面を配線基板上に固定する工程；
（ｌ）前記工程（ｋ）の後、前記半導体チップの前記第２のパッド電極と前記半導体チップの外部の電極間を金を主要な成分とするボンディング・ワイヤで接続する工程。 2. The method for manufacturing a semiconductor integrated circuit device according to the item 1, further includes the following steps:
(J) After the step (i), dividing the semiconductor wafer into semiconductor chips;
(K) After the step (j), a step of fixing the back surface of the semiconductor chip on the wiring board;
(L) After the step (k), a step of connecting the second pad electrode of the semiconductor chip and an electrode outside the semiconductor chip with a bonding wire containing gold as a main component.

３．前記１または２項の半導体集積回路装置の製造方法において、前記再配線金属層は、銅を主要な成分とする第1の再配線金属膜を有する。   3. In the method for manufacturing a semiconductor integrated circuit device according to the item 1 or 2, the redistribution metal layer has a first redistribution metal film containing copper as a main component.

４．前記３項の半導体集積回路装置の製造方法において、前記再配線金属層は、前記第1の再配線金属膜上に、ニッケルを主要な成分とする第２の再配線金属膜を有する。   4). In the method for manufacturing a semiconductor integrated circuit device according to the item 3, the redistribution metal layer has a second redistribution metal film containing nickel as a main component on the first redistribution metal film.

５．前記１から４項のいずれか一つの半導体集積回路装置の製造方法において、前記再配線金属層と前記第２のパッド電極の間には、ニッケルを主要な成分とし、第２のレジスト膜開口内に電解メッキにより形成されたパッド下地膜がある。   5. 5. In the method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 4, nickel is a main component between the redistribution metal layer and the second pad electrode, and the second resist film opening is formed. There is a pad base film formed by electrolytic plating.

６．前記１から５項のいずれか一つの半導体集積回路装置の製造方法において、前記第1のパッド電極は、アルミニウム系の膜を主要な構成要素とする。   6). 6. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 5, the first pad electrode includes an aluminum-based film as a main component.

７．前記１から６項のいずれか一つの半導体集積回路装置の製造方法において、前記シード・メタル層は、以下を含む：
（１）スパッタリングにより形成された下層の拡散バリア・メタル膜；
（２）スパッタリングにより形成された上層の銅シード膜。 7). 7. The method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 6, wherein the seed metal layer includes:
(1) Lower diffusion barrier metal film formed by sputtering;
(2) An upper copper seed film formed by sputtering.

８．前記７項の半導体集積回路装置の製造方法において、前記下層の拡散バリア・メタル膜は、クロムを主要な成分とする。   8). 8. The manufacturing method of a semiconductor integrated circuit device according to the item 7, wherein the lower diffusion barrier metal film contains chromium as a main component.

９．前記１から３および６から８項のいずれか一つの半導体集積回路装置の製造方法において、前記再配線金属層と前記第２のパッド電極の間には、ニッケルを主要な成分とし、第２のレジスト膜開口内の前記第1の再配線金属膜上に直接、電解メッキにより形成されたパッド下地膜がある。   9. In the method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 3 and 6 to 8, nickel is a main component between the redistribution metal layer and the second pad electrode, There is a pad base film formed by electrolytic plating directly on the first redistribution metal film in the resist film opening.

１０．前記１から９項のいずれか一つの半導体集積回路装置の製造方法において、前記第1の絶縁膜よりも上には、他の絶縁膜が実質的に存在しない。   10. 10. In the method for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 9, there is substantially no other insulating film above the first insulating film.

１１．前記１から１０項のいずれか一つの半導体集積回路装置の製造方法において、前記第1の絶縁膜は以下を含む：
（１）下層の無機系絶縁膜；
（２）上層の有機系絶縁膜。 11. 11. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 10, wherein the first insulating film includes:
(1) Underlying inorganic insulating film;
(2) Upper organic insulating film.

１２．前記１１項の半導体集積回路装置の製造方法において、前記下層の無機系絶縁膜は、窒化シリコンを主要な成分とする膜を含む。   12 12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the underlying inorganic insulating film includes a film containing silicon nitride as a main component.

１３．前記１１または１２項の半導体集積回路装置の製造方法において、前記上層の有機系絶縁膜は、ポリイミドを主要な成分とする膜を含む。   13. In the method for manufacturing a semiconductor integrated circuit device according to the item 11 or 12, the upper organic insulating film includes a film containing polyimide as a main component.

１４．以下を含む半導体集積回路装置：
（ａ）デバイス面を有する半導体基板；
（ｂ）前記デバイス面上の多層配線層；
（ｃ）前記多層配線層上の第1のパッド電極；
（ｄ）前記多層配線層および前記第1のパッド電極上のファイナル・パッシベーション膜；
（ｅ）前記ファイナル・パッシベーション膜の前記第1のパッド電極上のパッド開口；
（ｆ）前記パッド開口を通して、前記第1のパッド電極に接続された再配線金属層；
（ｇ）前記再配線金属層の上面の一部に設けられた電解メッキによる金を主要な成分とする第２のパッド電極。 14 Semiconductor integrated circuit devices including:
(A) a semiconductor substrate having a device surface;
(B) a multilayer wiring layer on the device surface;
(C) a first pad electrode on the multilayer wiring layer;
(D) a final passivation film on the multilayer wiring layer and the first pad electrode;
(E) a pad opening on the first pad electrode of the final passivation film;
(F) a redistribution metal layer connected to the first pad electrode through the pad opening;
(G) A second pad electrode mainly composed of gold by electrolytic plating provided on a part of the upper surface of the redistribution metal layer.

１５．前記１４項の半導体集積回路装置において、前記第1のパッド電極は、アルミニウム系の膜を主要な構成要素とする。   15. 15. In the semiconductor integrated circuit device according to item 14, the first pad electrode includes an aluminum-based film as a main component.

１６．前記１４または１５項の半導体集積回路装置において、前記再配線金属層は、以下を含む：
（１）銅を主要な成分とする第1の再配線金属膜；
（２）前記第1の再配線金属膜上に設けられた、ニッケルを主要な成分とする第２の再配線金属膜。 16. 16. The semiconductor integrated circuit device according to item 14 or 15, wherein the redistribution metal layer includes:
(1) A first redistribution metal film mainly composed of copper;
(2) A second redistribution metal film, which is provided on the first redistribution metal film and contains nickel as a main component.

１７．前記１６項の半導体集積回路装置において、前記第２の再配線金属膜と前記第２のパッド電極との間には、ニッケルを主要な成分とし、電解メッキにより形成されたパッド下地膜が設けられている。   17. 16. In the semiconductor integrated circuit device according to the item 16, a pad base film made of electrolytic plating and containing nickel as a main component is provided between the second redistribution metal film and the second pad electrode. ing.

１８．前記１４または１５項の半導体集積回路装置において、前記再配線金属層は、以下を含む：
（１）銅を主要な成分とする第1の再配線金属膜。 18. 16. The semiconductor integrated circuit device according to item 14 or 15, wherein the redistribution metal layer includes:
(1) A first redistribution metal film containing copper as a main component.

１９．前記１８項の半導体集積回路装置において、前記第１の再配線金属膜と前記第２のパッド電極との間には、ニッケルを主要な成分とし、電解メッキにより形成されたパッド下地膜が設けられている。   19. 19. In the semiconductor integrated circuit device according to the item 18, a pad base film formed by electrolytic plating and including nickel as a main component is provided between the first redistribution metal film and the second pad electrode. ing.

２０．前記１４から１９項のいずれか一つの半導体集積回路装置において、前記ファイナル・パッシベーション膜上には、他の絶縁膜がない。   20. 20. In the semiconductor integrated circuit device according to any one of Items 14 to 19, there is no other insulating film on the final passivation film.

〔本願における記載形式・基本的用語・用法の説明〕
１．本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクションに分けて記載する場合もあるが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しを省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。 [Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

２．同様に実施の態様等の記載において、材料、組成等について、「ＡからなるＸ」等といっても、特にそうでない旨明示した場合および文脈から明らかにそうでない場合を除き、Ａ以外の要素を主要な構成要素のひとつとするものを排除するものではない。たとえば、成分についていえば、「Ａを主要な成分として含むＸ」等の意味である。   2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”.

たとえば、「アルミニウム」、「銅」、「ニッケル」、「金」、「クロム」等といっても、これらの単独の純粋なメタル材料を意味するものではなく、当該材料成分を主要な構成成分とし、必要に応じて他の副次的成分を配合又は添加して合金を形成したものも含むことは言うまでもない。   For example, “aluminum”, “copper”, “nickel”, “gold”, “chromium” and the like do not mean these single pure metal materials, but the material components are the main constituent components. Needless to say, an alloy is formed by blending or adding other secondary components as necessary.

更に、「シリコン部材」等といっても、純粋なシリコンに限定されるものではなく、SiGe合金やその他シリコンを主要な成分とする多元合金、その他の添加物等を含む部材も含むものであることはいうまでもない。同様に、「酸化シリコン膜」、「酸化シリコン系絶縁膜」等と言っても、比較的純粋な非ドープ酸化シリコン(Undoped Silicon Dioxide)だけでなく、FSG（Fluorosilicate Glass）、TEOSベース酸化シリコン(TEOS-based silicon oxide)、SiOC(Silicon Oxicarbide)またはカーボンドープ酸化シリコン(Carbon-doped Silicon oxide)またはOSG(Organosilicate glass)、PSG(Phosphorus Silicate Glass)、BPSG(Borophosphosilicate Glass)等の熱酸化膜、CVD酸化膜、SOG(Spin ON Glass)、ナノ・クラスタリング・シリカ（Nano-Clustering Silica:NSC）等の塗布系酸化シリコン、これらと同様な部材に空孔を導入したシリカ系Low-k絶縁膜（ポーラス系絶縁膜）、およびこれらを主要な構成要素とする他のシリコン系絶縁膜との複合膜等を含むことは言うまでもない。   Furthermore, the term “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NSC), etc., coated silicon oxide, silica-based low-k insulating film (porous) with pores introduced in the same materials Needless to say, it includes a composite insulating film and other silicon-based insulating films having these as main components.

３．同様に、図形、位置、属性等に関して、好適な例示をするが、特にそうでない旨明示した場合および文脈から明らかにそうでない場合を除き、厳密にそれに限定されるものではないことは言うまでもない。   3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

４．さらに、特定の数値、数量に言及したときも、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、その特定の数値を超える数値であってもよいし、その特定の数値未満の数値でもよい。   4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

５．「ウエハ」というときは、通常は半導体集積回路装置（半導体装置、電子装置も同じ）をその上に形成する単結晶シリコンウエハを指すが、エピタキシャルウエハ、ＳＯＩ基板、ＬＣＤガラス基板等の絶縁基板と半導体層等の複合ウエハ等も含むことは言うまでもない。   5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

〔実施の形態の詳細〕
実施の形態について更に詳述する。各図中において、同一または同様の部分は同一または類似の記号または参照番号で示し、説明は原則として繰り返さない。 [Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

１．本願の一実施の形態の半導体集積回路装置の製造方法におけるアルミニウム系パッド形成から再配線等のウエハ・プロセスの説明（主に図１から図１６）
以下では、図１から図１６に基づいて、主に半導体集積回路装置のウエハ・プロセスにおけるアルミニウム系パッド（銅系パッドその他でもよい）形成工程周辺以降を説明する。アルミニウム系パッド層より下層には、通常、銅系ダマシン多層配線層またはアルミニウム系通常多層配線層（一般に３層から１０層程度）がある。以下の説明する図面では、ウエハについて説明する際も、簡潔性を確保するために、原則として単位チップ領域のみを表示する。 1. Description of wafer process from aluminum-based pad formation to rewiring in the method of manufacturing a semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 1 to 16)
In the following, based on FIG. 1 to FIG. 16, a description will be given mainly after the vicinity of an aluminum pad (copper pad or other) forming step in a wafer process of a semiconductor integrated circuit device. Below the aluminum-based pad layer, there is usually a copper-based damascene multilayer wiring layer or an aluminum-based ordinary multilayer wiring layer (generally about 3 to 10 layers). In the drawings to be described below, only the unit chip area is displayed as a rule in order to ensure simplicity when the wafer is described.

図１に示すように、半導体ウエハ１（チップ領域１ｃ）のデバイス面１ａ（裏面１ｂに対向する主面）には、多数のアルミニウム系ボンディング・パッド２（第1のパッド電極）が形成されている。パッド周辺部CのＸ−Ｘ’断面を図２に示す。以下に平面構造とともに製造プロセスを説明する。   As shown in FIG. 1, a large number of aluminum-based bonding pads 2 (first pad electrodes) are formed on the device surface 1a (main surface facing the back surface 1b) of the semiconductor wafer 1 (chip region 1c). Yes. An X-X ′ cross section of the pad peripheral portion C is shown in FIG. 2. The manufacturing process will be described together with the planar structure.

図２に示すように、ボンディング・パッド２下の多層配線層を含む半導体基板１ｐ（本来の基板部分は通常、たとえば３００ファイのｐ型の単結晶シリコン・ウエハである）のデバイス面１ａ側には、ファイナル・パッシベーション膜４が形成されている。ボンディング・パッド２を構成するアルミニウム系パッド層は、最上層配線層を兼ねてもよい。ボンディング・パッド２およびファイナル・パッシベーション膜４の形成については、以下のように形成する。まず、多層配線層上にスパッタリングにより、アルミニウム系メタル膜（通常、中間のアルミニウムを主要な成分とし、銅その他を数パーセント程度添加した主配線金属層の上下にＴｉＮ等の薄膜を有する）を成膜する。通常のリソグラフィにより、アルミニウム系メタル膜をパターニングし、ボンディング・パッド２を形成する。次に、半導体ウエハ１のデバイス面１ａ側のほぼ全面に、たとえば、下層の無機ファイナル・パッシベーション膜となる酸化シリコン系絶縁膜をプラズマＣＶＤ法により成膜する。続いて、その上に、たとえば、上層の無機ファイナル・パッシベーション膜となる窒化シリコン系絶縁膜をプラズマＣＶＤ法により成膜する。次に、この２層からなる無機ファイナル・パッシベーション膜に通常のリソグラフィにより、パッド開口３を形成する。この後、一般に主配線金属層上のＴｉＮ等が自己整合的にエッチング除去される。次に、半導体ウエハ１のデバイス面１ａ側のほぼ全面に、たとえば、有機ファイナル・パッシベーション膜となるポリイミド膜を塗布する。続いて、先とほぼ同じ開口位置に再び通常のリソグラフィにより、パッド開口３を形成する。従って、最終的なファイナル・パッシベーション膜４（第1の絶縁膜）は、下層から酸化シリコン膜、窒化シリコン膜、およびポリイミド膜の三層重ね膜となる。これで、図２のような断面形態となる。このように、再配線パターン１６上に、第２のポリイミド膜等の別のパッシベーション膜がないので、簡易な構造とすることができる。また、製造プロセスは大幅に簡素化される。このような簡素化が可能な理由は、最上層が膜質の良好な非腐食性の電解メッキによる金パッド膜１５と成っているからである。   As shown in FIG. 2, on the device surface 1a side of a semiconductor substrate 1p including a multilayer wiring layer under a bonding pad 2 (the original substrate portion is usually a 300-type p-type single crystal silicon wafer). The final passivation film 4 is formed. The aluminum-based pad layer constituting the bonding pad 2 may also serve as the uppermost wiring layer. The bonding pad 2 and the final passivation film 4 are formed as follows. First, an aluminum-based metal film (usually having a thin film such as TiN above and below a main wiring metal layer containing intermediate aluminum as a main component and adding copper or the like by several percent) is sputtered on the multilayer wiring layer. Film. The aluminum-based metal film is patterned by ordinary lithography to form the bonding pad 2. Next, for example, a silicon oxide insulating film to be a lower inorganic final passivation film is formed on almost the entire surface of the semiconductor wafer 1 on the device surface 1a side by a plasma CVD method. Subsequently, for example, a silicon nitride insulating film to be an upper inorganic final passivation film is formed thereon by plasma CVD. Next, a pad opening 3 is formed in the inorganic final passivation film composed of the two layers by ordinary lithography. Thereafter, TiN and the like on the main wiring metal layer are generally etched away in a self-aligning manner. Next, for example, a polyimide film serving as an organic final passivation film is applied to almost the entire surface of the semiconductor wafer 1 on the device surface 1a side. Subsequently, the pad opening 3 is formed again by ordinary lithography at substantially the same opening position as before. Therefore, the final final passivation film 4 (first insulating film) is a three-layered film including a silicon oxide film, a silicon nitride film, and a polyimide film from the lower layer. Thus, the cross-sectional form as shown in FIG. 2 is obtained. Thus, since there is no other passivation film such as the second polyimide film on the rewiring pattern 16, a simple structure can be obtained. Also, the manufacturing process is greatly simplified. The reason why such simplification is possible is that the uppermost layer is a gold pad film 15 by non-corrosive electrolytic plating with good film quality.

次に、図３に示すように、半導体ウエハ１のデバイス面１ａ側のほぼ全面に、スパッタリングにより、拡散バリア・メタル膜５（たとえば７５ｎｍ程度の厚さのクロム膜）を成膜する。バリア・メタルとしては、他にチタン、窒化チタン、および窒化タングステン等を主要な成分とするものが好適なものとして例示できる。   Next, as shown in FIG. 3, a diffusion barrier metal film 5 (for example, a chromium film having a thickness of about 75 nm) is formed on almost the entire surface of the semiconductor wafer 1 on the device surface 1a side by sputtering. Other examples of suitable barrier metals include titanium, titanium nitride, tungsten nitride and the like as main components.

その上に、図４に示すように、銅の電解メッキのためのシード膜６（たとえば２５０ｎｍ程度の厚さの銅膜）をスパッタリングにより、成膜する。   On top of this, as shown in FIG. 4, a seed film 6 (for example, a copper film having a thickness of about 250 nm) for electrolytic plating of copper is formed by sputtering.

次に、図５に示すように、半導体ウエハ１のデバイス面１ａ側のほぼ全面に、レジスト膜７（たとえば厚さ１２マイクロ・メートル程度）を形成する。続いて、レジスト膜７を通常のリソグラフィにより、パターニングすることにより、第1のレジスト膜開口１０を有する第1のレジスト膜パターン７を形成する。   Next, as shown in FIG. 5, a resist film 7 (for example, a thickness of about 12 micrometers) is formed on almost the entire surface of the semiconductor wafer 1 on the device surface 1a side. Subsequently, the resist film 7 is patterned by normal lithography to form a first resist film pattern 7 having a first resist film opening 10.

次に、図６に示すように、電解メッキにより、第1のレジスト膜開口１０内に、選択的に第1の再配線金属膜８（たとえば、厚さ７．５マイクロ・メートル程度の銅メッキ膜）を形成する。   Next, as shown in FIG. 6, the first redistribution metal film 8 (for example, copper plating having a thickness of about 7.5 μm) is selectively formed in the first resist film opening 10 by electrolytic plating. Film).

更に、その上に、図７に示すように、電解メッキにより、第1のレジスト膜開口１０内に、選択的に第２の再配線金属膜９（たとえば、厚さ２．３マイクロ・メートル程度のニッケル・メッキ膜）を形成する。この膜は、必須ではないが、付加することでデバイスの信頼性を向上させることができる。拡散または反応バリア膜として作用する。この第1の再配線金属膜８と第２の再配線金属膜９で再配線金属層１６を構成している。   Further, as shown in FIG. 7, a second redistribution metal film 9 (for example, a thickness of about 2.3 μm) is selectively formed in the first resist film opening 10 by electrolytic plating as shown in FIG. Nickel plating film). Although this film is not essential, the reliability of the device can be improved by adding it. Acts as a diffusion or reaction barrier film. The first redistribution metal film 8 and the second redistribution metal film 9 constitute a redistribution metal layer 16.

次に、図８および図９に示すように、レジスト膜７（第1のレジスト膜パターン）を有する半導体ウエハ１のデバイス面１ａ側のほぼ全面に、レジスト膜１１（たとえば厚さ１２マイクロ・メートル程度）を形成する。続いて、レジスト膜１１を通常のリソグラフィにより、パターニングすることにより、第２のレジスト膜開口１２を有する第２のレジスト膜パターン１１を形成する。   Next, as shown in FIGS. 8 and 9, a resist film 11 (for example, a thickness of 12 micrometers) is formed on almost the entire surface of the semiconductor wafer 1 having the resist film 7 (first resist film pattern) on the device surface 1a side. Degree). Subsequently, the resist film 11 is patterned by normal lithography to form a second resist film pattern 11 having a second resist film opening 12.

次に、図１０に示すように、電解メッキにより、第２のレジスト膜開口１２内に、選択的にパッド下地膜１４（たとえば、厚さ０．７マイクロ・メートル程度のニッケル・メッキ膜）を形成する。この膜は必須ではないが、付加することで、後の金メッキの膜質を良好にするメリットがある。   Next, as shown in FIG. 10, a pad base film 14 (for example, a nickel plating film having a thickness of about 0.7 micrometer) is selectively formed in the second resist film opening 12 by electrolytic plating. Form. Although this film is not indispensable, adding it has the advantage of improving the film quality of the subsequent gold plating.

更に、その上に、図１１に示すように、電解メッキにより、第２のレジスト膜開口１２内に、選択的に第２のパッド電極１５（たとえば、厚さ１．０マイクロ・メートル程度の金メッキ膜）を形成する。メッキ液としては、たとえば、亜硫酸金ナトリウム系のメッキ液等が好適なものとして例示できる。   Further, as shown in FIG. 11, a second pad electrode 15 (for example, a gold plating having a thickness of about 1.0 micrometer is selectively formed in the second resist film opening 12 by electrolytic plating, as shown in FIG. Film). As the plating solution, for example, a gold sulfite-based plating solution can be exemplified as a suitable one.

次に、図１２に示すように、不要になった第２のレジスト膜パターン１１を除去溶剤・アッシング等により除去する。   Next, as shown in FIG. 12, the unnecessary second resist film pattern 11 is removed by a removing solvent, ashing or the like.

更に、図１３に示すように、再配線金属層１６の直下以外のシード・メタル層２１（下層のクロム膜５および上層の銅シード膜６）を、たとえばウエット・エッチングにより除去する。まず、上層の銅シード膜６を自己整合的に、除去し（処理としては、たとえば、摂氏２５度程度の過酸化水素水による１０秒程度のウエット・エッチング処理を例示することができる）、続いて、下層のクロム膜５を除去する（処理としては、たとえば、摂氏２５度程度の過マンガン酸カリウムとメタケイ酸ナトリウムの混合液等による２０分程度のウエット・エッチング処理を例示することができる）。なお、以下の工程では、シード・メタル層２１も含めて再配線金属層または再配線パターン等ということがある。   Further, as shown in FIG. 13, the seed metal layer 21 (the lower chromium film 5 and the upper copper seed film 6) other than just below the redistribution metal layer 16 is removed by, for example, wet etching. First, the upper copper seed film 6 is removed in a self-aligning manner (as a process, for example, a wet etching process of about 10 seconds with a hydrogen peroxide solution of about 25 degrees Celsius can be exemplified), and then Then, the lower chromium film 5 is removed (for example, a wet etching process of about 20 minutes with a mixed solution of potassium permanganate and sodium metasilicate of about 25 degrees Celsius can be exemplified) . In the following processes, the redistribution metal layer or the redistribution pattern including the seed metal layer 21 may be referred to.

以上により、図１４に示すように、ここで、半導体ウエハ１のデバイス面１ａ側に、分離した再配線金属層または再配線パターン１６が形成される。図１５に図１４のパッド周辺部Cの拡大平面図を示す。図１６は、図１５のＸ−Ｘ’断面でカットしたデバイスの斜視図である。   As a result, as shown in FIG. 14, the separated rewiring metal layer or rewiring pattern 16 is formed on the device surface 1 a side of the semiconductor wafer 1. FIG. 15 is an enlarged plan view of the pad peripheral portion C of FIG. 16 is a perspective view of the device cut along the X-X ′ section of FIG. 15.

２．本願の一実施の形態の半導体集積回路装置の製造方法における実装プロセスの説明（主に図１７および図１８）
ここでは、セクション1で説明したプロセスの、その後のプロセス（実装プロセス）を説明する。 2. Description of mounting process in manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 17 and 18)
Here, the subsequent process (implementation process) of the process described in Section 1 is described.

図１７に示すように、ダイシング等により、個々のチップ１ｃに分割する。次に、チップ１ｃを配線基板１７上にダイ・ボンディングする。その後、金を主要な成分とするボンディング・ワイヤ１９を用いて、キャピラリを用いたボール・ボンディング（たとえばサーモ・ソニック・ボンディング）により、チップ１ｃ上の金パッド１５（第２のパッド電極）とチップ１ｃ外の電極（たとえば配線基板１７上の外部リード１８）間を接続する。図１８に図１７の破線部分の斜視図（図１６に続く）を示す。   As shown in FIG. 17, it is divided into individual chips 1c by dicing or the like. Next, the chip 1 c is die-bonded on the wiring board 17. Thereafter, the gold pad 15 (second pad electrode) on the chip 1c and the chip are formed by ball bonding (for example, thermosonic bonding) using a capillary using a bonding wire 19 containing gold as a main component. The electrodes (for example, external leads 18 on the wiring board 17) outside 1c are connected. FIG. 18 shows a perspective view of the broken line portion of FIG. 17 (continuing from FIG. 16).

なお、この場合、いずれの電極にボールを配置してもよい。   In this case, the ball may be disposed on any electrode.

３．図１から図１８について説明した半導体集積回路装置およびその製造方法に対する変形例の説明（主に図１９）
この例は、セクション１および２に説明したプロセスにおいて、図７で説明した電解メッキ・ニッケル再配線層９（第２の再配線金属膜）の形成を省略したものである。これにより、再配線構造の簡略化が可能となる。電解メッキ・ニッケル再配線層９がなくとも、ニッケル・パッド膜１４がバリア・メタル膜として作用するので、特性上の問題は比較的少ないと考えられる。 3. Description of Modifications to the Semiconductor Integrated Circuit Device and the Method of Manufacturing the Semiconductor Integrated Circuit Device Explained with reference to FIGS.
In this example, the formation of the electrolytic plating / nickel redistribution layer 9 (second redistribution metal film) described with reference to FIG. 7 is omitted in the processes described in sections 1 and 2. As a result, the rewiring structure can be simplified. Even if the electroplating / nickel rewiring layer 9 is not provided, the nickel pad film 14 acts as a barrier metal film, so that it is considered that there are relatively few problems in characteristics.

４．サマリ
以上本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。 4). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

例えば、前記実施の形態においては、主に銅層とニッケル層の重ね膜を再配線の主要な構成部分とする例について、具体的に説明したが、本願発明はそれに限定されるものではなく、銅層単層を再配線の主要な構成部分とするもの等にも適用できることは言うまでもない。   For example, in the above-described embodiment, an example in which an overlapping film of a copper layer and a nickel layer is mainly used as a main constituent part of rewiring has been specifically described, but the present invention is not limited thereto, Needless to say, the present invention can also be applied to a structure in which a single copper layer is a main component of rewiring.

本願の一実施の形態の半導体集積回路装置の製造方法におけるパッド開口工程以降のプロセスの流れを示すための半導体ウエハの単位チップ領域の上面図（パッド開口工程完了時点）である。It is a top view (at the time of completion of a pad opening process) of a unit chip area of a semiconductor wafer for showing a process flow after a pad opening process in a manufacturing method of a semiconductor integrated circuit device of one embodiment of this application. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（パッド開口工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of a pad opening step) corresponding to X-X ′ of a broken line portion C in FIG. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（クロム膜スパッタ工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of a chromium film sputtering step) corresponding to X-X ′ of a broken line portion C in FIG. 1. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（銅シード膜スパッタ工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of a copper seed film sputtering step) corresponding to X-X ′ of a broken line portion C in FIG. 1. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（第1のレジスト膜パターン形成工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of a first resist film pattern formation step) corresponding to X-X ′ of a broken line portion C in FIG. 1. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（銅再配線電解メッキ工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of a copper rewiring electrolytic plating process) corresponding to X-X ′ of a broken line portion C in FIG. 1. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（ニッケル再配線電解メッキ工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of a nickel rewiring electrolytic plating process) corresponding to X-X ′ of a broken line portion C in FIG. 1. 図1の破線部分Ｃに対応するデバイス上面図（第２のレジスト膜パターン形成工程完了時点）である。FIG. 3 is a top view of a device corresponding to a broken line portion C in FIG. 1 (at the time when a second resist film pattern forming step is completed). 図1または図８の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（第２のレジスト膜パターン形成工程完了時点）である。FIG. 9 is a device cross-sectional view (at the time of completion of a second resist film pattern forming step) corresponding to X-X ′ of a broken line portion C in FIG. 1 or FIG. 8; 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（ニッケル・パッド電解メッキ工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of a nickel pad electroplating step) corresponding to X-X ′ of a broken line portion C in FIG. 1. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（金パッド電解メッキ工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of a gold pad electroplating step) corresponding to X-X ′ of a broken line portion C in FIG. 1. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（第２のレジスト膜パターン除去工程完了時点）である。FIG. 6 is a device cross-sectional view (at the time of completion of a second resist film pattern removal step) corresponding to X-X ′ of a broken line portion C in FIG. 1. 図1の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（パッド上シード＆バリア・メタル層除去工程完了時点）である。FIG. 2 is a device cross-sectional view (at the time of completion of the on-pad seed & barrier metal layer removal step) corresponding to X-X ′ of a broken line portion C in FIG. 1. 本願の一実施の形態の半導体集積回路装置の製造方法における金パッド形成工程以降のプロセスの流れを示すための半導体ウエハの単位チップ領域の上面図（金パッド形成工程完了時点）である。It is a top view (at the time of completion of a gold pad formation process) of a unit chip area of a semiconductor wafer for showing a process flow after a gold pad formation process in a manufacturing method of a semiconductor integrated circuit device of one embodiment of this application. 図1４の破線部分Ｃの拡大上面図（金パッド形成工程完了時点）である。FIG. 15 is an enlarged top view of a broken line portion C in FIG. 14 (at the time when the gold pad forming process is completed). 図１５に対応するデバイス斜視図（金パッド形成工程完了時点）である。FIG. 16 is a device perspective view corresponding to FIG. 15 (at the time of completion of the gold pad forming step). 図1４および１５の破線部分ＣのＸ−Ｘ’に対応するデバイス断面図（ワイヤ・ボンディング工程完了時点）である。FIG. 16 is a device cross-sectional view (at the time of completion of a wire bonding step) corresponding to X-X ′ of a broken line portion C in FIGS. 14 and 15. 図１７に対応するデバイス斜視図（ワイヤ・ボンディング工程完了時点）である。FIG. 18 is a perspective view of the device corresponding to FIG. 17 (at the time of completion of the wire bonding process). 図１から図１８（特に図１７）に対応するデバイスまたは同プロセスに対する変形例（図７の工程が省略されている）を示すデバイス断面図（ワイヤ・ボンディング工程完了時点）である。FIG. 19 is a device cross-sectional view (at the time of completion of the wire bonding step) showing a device corresponding to FIG. 1 to FIG. 18 (particularly FIG. 17) or a modification to the process (step of FIG. 7 is omitted);

符号の説明Explanation of symbols

１ 半導体基板（半導体ウエハまたは半導体チップ）
１ａ 半導体基板の表主面（デバイス面または第1の主面）
１ｂ 半導体基板の裏面（第２の主面）
１ｃ チップ領域または半導体チップ
１ｐ ボンディング・パッド下の配線層を含む半導体基板
２ アルミニウム系または銅系ボンディング・パッド（第1のパッド電極）
３ パッド開口
４ ファイナル・パッシベーション膜または第1の絶縁膜（下層から酸化シリコン膜、窒化シリコン膜、ポリイミド膜）
５ アルミニウム系パッド上バリア・メタル膜または下層の拡散バリア・メタル膜（クロム膜）
６ 銅シード膜（上層の銅シード膜）
７ レジスト膜（第1のレジスト膜パターン）
８ 電解メッキ銅再配線層（第1の再配線金属膜）
９ 電解メッキ・ニッケル再配線層（第２の再配線金属膜）
１０ レジスト膜の開口（第1のレジスト膜開口）
１１ レジスト膜（第２のレジスト膜パターン）
１２ レジスト膜の開口（第２のレジスト膜開口）
１４ ニッケル・パッド膜（パッド下地膜）
１５ 金パッドまたは金パッド膜（第２のパッド電極）
１６ 再配線金属層または再配線パターン（下層銅、上層ニッケル）
１７ 配線基板
１８ 外部リード
１９ ボンディング・ワイヤ
２１ パッド上シード＆バリア・メタル層（シード・メタル層）
Ｃ パッド周辺部 1 Semiconductor substrate (semiconductor wafer or semiconductor chip)
1a Main surface of the semiconductor substrate (device surface or first main surface)
1b Back surface of semiconductor substrate (second main surface)
1c Chip region or semiconductor chip 1p Semiconductor substrate including wiring layer under bonding pad 2 Aluminum-based or copper-based bonding pad (first pad electrode)
3 Pad opening 4 Final passivation film or first insulating film (from the bottom layer silicon oxide film, silicon nitride film, polyimide film)
5 Barrier metal film on aluminum pad or diffusion barrier metal film (chromium film) below
6 Copper seed film (upper copper seed film)
7 resist film (first resist film pattern)
8 Electrolytically plated copper redistribution layer (first redistribution metal film)
9 Electrolytic plating / nickel rewiring layer (second rewiring metal film)
10 Resist film opening (first resist film opening)
11 resist film (second resist film pattern)
12 Opening of resist film (second resist film opening)
14 Nickel pad film (pad base film)
15 Gold pad or gold pad film (second pad electrode)
16 Rewiring metal layer or rewiring pattern (lower layer copper, upper layer nickel)
17 Wiring Board 18 External Lead 19 Bonding Wire 21 Seed & Barrier Metal Layer on Pad (Seed Metal Layer)
C pad periphery

Claims (20)

以下の工程を含む半導体集積回路装置の製造方法：
（ａ）半導体ウエハのデバイス面上の多層配線層上に、第1のパッド電極を形成する工程；
（ｂ）前記工程（ａ）の後、前記半導体ウエハの前記デバイス面側を第1の絶縁膜で被覆する工程；
（ｃ）前記工程（ｂ）の後、前記第1のパッド電極上の前記第1の絶縁膜にパッド開口を形成する工程；
（ｄ）前記工程（ｃ）の後、前記半導体ウエハの前記デバイス面側にシード・メタル層を形成する工程；
（ｅ）前記工程（ｄ）の後、前記シード・メタル層上に、前記パッド開口を内部に含む第1のレジスト膜開口を有する第1のレジスト膜パターンを形成する工程；
（ｆ）前記工程（ｅ）の後、前記シード・メタル層上の前記第1のレジスト膜開口内に、電解メッキにより、再配線金属層を形成する工程；
（ｇ）前記工程（ｆ）の後、前記再配線金属層上に第２のレジスト膜開口を有する第２のレジスト膜パターンを、前記シード・メタル層および前記再配線金属層上に、形成する工程；
（ｈ）前記工程（ｇ）の後、前記再配線金属層上の前記第２のレジスト膜開口内に、電解メッキにより、金を主要な成分とする第２のパッド電極を形成する工程；
（ｉ）前記工程（ｈ）の後、前記第２のレジスト膜パターンを除去する工程。 A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) forming a first pad electrode on the multilayer wiring layer on the device surface of the semiconductor wafer;
(B) After the step (a), a step of coating the device surface side of the semiconductor wafer with a first insulating film;
(C) after the step (b), forming a pad opening in the first insulating film on the first pad electrode;
(D) a step of forming a seed metal layer on the device surface side of the semiconductor wafer after the step (c);
(E) After the step (d), forming a first resist film pattern having a first resist film opening including the pad opening on the seed metal layer;
(F) After the step (e), a step of forming a redistribution metal layer in the first resist film opening on the seed metal layer by electrolytic plating;
(G) After the step (f), a second resist film pattern having a second resist film opening is formed on the redistribution metal layer on the seed metal layer and the redistribution metal layer. Process;
(H) After the step (g), forming a second pad electrode containing gold as a main component by electrolytic plating in the opening of the second resist film on the redistribution metal layer;
(I) A step of removing the second resist film pattern after the step (h). 前記１項の半導体集積回路装置の製造方法において、更に以下の工程を含む：
（ｊ）前記工程（ｉ）の後、前記半導体ウエハを半導体チップに分割する工程；
（ｋ）前記工程（ｊ）の後、前記半導体チップの裏面を配線基板上に固定する工程；
（ｌ）前記工程（ｋ）の後、前記半導体チップの前記第２のパッド電極と前記半導体チップの外部の電極間を金を主要な成分とするボンディング・ワイヤで接続する工程。 The method for manufacturing a semiconductor integrated circuit device according to the item 1, further includes the following steps:
(J) After the step (i), dividing the semiconductor wafer into semiconductor chips;
(K) After the step (j), a step of fixing the back surface of the semiconductor chip on the wiring board;
(L) After the step (k), a step of connecting the second pad electrode of the semiconductor chip and an electrode outside the semiconductor chip with a bonding wire containing gold as a main component. 前記１項の半導体集積回路装置の製造方法において、前記再配線金属層は、銅を主要な成分とする第1の再配線金属膜を有する。     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the redistribution metal layer has a first redistribution metal film containing copper as a main component. 前記３項の半導体集積回路装置の製造方法において、前記再配線金属層は、前記第1の再配線金属膜上に、ニッケルを主要な成分とする第２の再配線金属膜を有する。     In the method for manufacturing a semiconductor integrated circuit device according to the item 3, the redistribution metal layer has a second redistribution metal film containing nickel as a main component on the first redistribution metal film. 前記４項の半導体集積回路装置の製造方法において、前記再配線金属層と前記第２のパッド電極の間には、ニッケルを主要な成分とし、第２のレジスト膜開口内に電解メッキにより形成されたパッド下地膜がある。     5. The method for manufacturing a semiconductor integrated circuit device according to item 4, wherein nickel is a main component between the redistribution metal layer and the second pad electrode and is formed by electrolytic plating in the second resist film opening. There is a pad base film. 前記１項の半導体集積回路装置の製造方法において、前記第1のパッド電極は、アルミニウム系の膜を主要な構成要素とする。     In the method of manufacturing a semiconductor integrated circuit device according to the item 1, the first pad electrode is mainly composed of an aluminum-based film. 前記６項の半導体集積回路装置の製造方法において、前記シード・メタル層は、以下を含む：
（１）スパッタリングにより形成された下層の拡散バリア・メタル膜；
（２）スパッタリングにより形成された上層の銅シード膜。 In the method of manufacturing a semiconductor integrated circuit device according to the item 6, the seed metal layer includes:
(1) Lower diffusion barrier metal film formed by sputtering;
(2) An upper copper seed film formed by sputtering. 前記７項の半導体集積回路装置の製造方法において、前記下層の拡散バリア・メタル膜は、クロムを主要な成分とする。     8. The manufacturing method of a semiconductor integrated circuit device according to the item 7, wherein the lower diffusion barrier metal film contains chromium as a main component. 前記３項の半導体集積回路装置の製造方法において、前記再配線金属層と前記第２のパッド電極の間には、ニッケルを主要な成分とし、第２のレジスト膜開口内の前記第1の再配線金属膜上に直接、電解メッキにより形成されたパッド下地膜がある。     4. In the method of manufacturing a semiconductor integrated circuit device according to the item 3, nickel is a main component between the redistribution metal layer and the second pad electrode, and the first re-growth in the second resist film opening is formed. There is a pad base film formed by electrolytic plating directly on the wiring metal film. 前記１項の半導体集積回路装置の製造方法において、前記第1の絶縁膜よりも上には、他の絶縁膜が実質的に存在しない。     In the method of manufacturing a semiconductor integrated circuit device according to the item 1, there is substantially no other insulating film above the first insulating film. 前記１項の半導体集積回路装置の製造方法において、前記第1の絶縁膜は以下を含む：
（１）下層の無機系絶縁膜；
（２）上層の有機系絶縁膜。 In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the first insulating film includes:
(1) Underlying inorganic insulating film;
(2) Upper organic insulating film. 前記１１項の半導体集積回路装置の製造方法において、前記下層の無機系絶縁膜は、窒化シリコンを主要な成分とする膜を含む。     12. In the method for manufacturing a semiconductor integrated circuit device according to the item 11, the underlying inorganic insulating film includes a film containing silicon nitride as a main component. 前記１２項の半導体集積回路装置の製造方法において、前記上層の有機系絶縁膜は、ポリイミドを主要な成分とする膜を含む。     In the method for manufacturing a semiconductor integrated circuit device according to the item 12, the upper organic insulating film includes a film containing polyimide as a main component. 以下を含む半導体集積回路装置：
（ａ）デバイス面を有する半導体基板；
（ｂ）前記デバイス面上の多層配線層；
（ｃ）前記多層配線層上の第1のパッド電極；
（ｄ）前記多層配線層および前記第1のパッド電極上のファイナル・パッシベーション膜；
（ｅ）前記ファイナル・パッシベーション膜の前記第1のパッド電極上のパッド開口；
（ｆ）前記パッド開口を通して、前記第1のパッド電極に接続された再配線金属層；
（ｇ）前記再配線金属層の上面の一部に設けられた電解メッキによる金を主要な成分とする第２のパッド電極。 Semiconductor integrated circuit devices including:
(A) a semiconductor substrate having a device surface;
(B) a multilayer wiring layer on the device surface;
(C) a first pad electrode on the multilayer wiring layer;
(D) a final passivation film on the multilayer wiring layer and the first pad electrode;
(E) a pad opening on the first pad electrode of the final passivation film;
(F) a redistribution metal layer connected to the first pad electrode through the pad opening;
(G) A second pad electrode mainly composed of gold by electrolytic plating provided on a part of the upper surface of the redistribution metal layer. 前記１４項の半導体集積回路装置において、前記第1のパッド電極は、アルミニウム系の膜を主要な構成要素とする。     15. In the semiconductor integrated circuit device according to item 14, the first pad electrode includes an aluminum-based film as a main component. 前記１５項の半導体集積回路装置において、前記再配線金属層は、以下を含む：
（１）銅を主要な成分とする第1の再配線金属膜；
（２）前記第1の再配線金属膜上に設けられた、ニッケルを主要な成分とする第２の再配線金属膜。 16. The semiconductor integrated circuit device according to the item 15, wherein the redistribution metal layer includes:
(1) A first redistribution metal film mainly composed of copper;
(2) A second redistribution metal film, which is provided on the first redistribution metal film and contains nickel as a main component. 前記１６項の半導体集積回路装置において、前記第２の再配線金属膜と前記第２のパッド電極との間には、ニッケルを主要な成分とし、電解メッキにより形成されたパッド下地膜が設けられている。     16. In the semiconductor integrated circuit device according to the item 16, a pad base film made of electrolytic plating and containing nickel as a main component is provided between the second redistribution metal film and the second pad electrode. ing. 前記１５項の半導体集積回路装置において、前記再配線金属層は、以下を含む：
（１）銅を主要な成分とする第1の再配線金属膜。 16. The semiconductor integrated circuit device according to the item 15, wherein the redistribution metal layer includes:
(1) A first redistribution metal film containing copper as a main component. 前記１８項の半導体集積回路装置において、前記第１の再配線金属膜と前記第２のパッド電極との間には、ニッケルを主要な成分とし、電解メッキにより形成されたパッド下地膜が設けられている。     19. In the semiconductor integrated circuit device according to the item 18, a pad base film formed by electrolytic plating and including nickel as a main component is provided between the first redistribution metal film and the second pad electrode. ing. 前記１４項の半導体集積回路装置において、前記ファイナル・パッシベーション膜上には、他の絶縁膜がない。     15. In the semiconductor integrated circuit device according to the item 14, there is no other insulating film on the final passivation film.
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JP2016152328A (en) * 2015-02-18 2016-08-22 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of the same
EP3067923A1 (en) * 2015-02-18 2016-09-14 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US10586777B2 (en) 2015-02-18 2020-03-10 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

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