JP2010141126A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2010141126A
JP2010141126A JP2008315925A JP2008315925A JP2010141126A JP 2010141126 A JP2010141126 A JP 2010141126A JP 2008315925 A JP2008315925 A JP 2008315925A JP 2008315925 A JP2008315925 A JP 2008315925A JP 2010141126 A JP2010141126 A JP 2010141126A
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layer
circuit board
metal support
printed circuit
conductor
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JP5135194B2 (en
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Shigenori Morita
成紀 森田
Takashi Oda
高司 小田
Naoko Yoshida
直子 吉田
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Nitto Denko Corp
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Nitto Denko Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Abstract

<P>PROBLEM TO BE SOLVED: To reuse a metal support substrate by removing the metal support substrate without the use of a method to disappear the substrate by troublesome etching after mounting chips on a flexible printed-circuit board supported by the metal support substrate. <P>SOLUTION: The printed-circuit board 2 having a conductor 21 for connection which is connected to an electrode 31 of the semiconductor chip 3 is formed on a metal support body layer 1 to be exfoliated from the support body layer 1 so that the conductor 21 for connection is exposed on the upper surface of the printed-circuit board 2. The conductor 21 for connection of the printed-circuit board 2 is connected with the electrode 31 of the semiconductor chip 3, and the semiconductor chip 3 is mounted on the printed-circuit board 2. After the mounting, the metal support body layer 1 is exfoliated from the printed-circuit board 2 to provide a semiconductor device by conducting a dicing if required. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体チップが配線回路基板に実装されてなる半導体装置を製造する方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip is mounted on a printed circuit board.

シリコン半導体を用いたＩＣや、有機半導体を用いた有機ＥＬ素子など、種々の半導体材料にて構成される半導体素子（以下、単に「素子」とも言う）は、通常、ウェハ基板面に素子をマトリクス状に多数繰り返して形成した後、ダイシングによって個々の素子である半導体チップ（ベアチップとも呼ばれる）へと分断することによって製造される。
以下の説明では、ウェハ基板上に半導体素子が形成された段階（ダイシング前の段階）のものを「半導体ウェハ」と呼ぶ。また、半導体チップを、単に「チップ」とも呼んで説明する。 Semiconductor elements (hereinafter also simply referred to as “elements”) composed of various semiconductor materials such as ICs using silicon semiconductors and organic EL elements using organic semiconductors are usually arranged in a matrix on the wafer substrate surface. After being repeatedly formed in a shape, the semiconductor chip is manufactured by dividing into individual semiconductor chips (also referred to as bare chips) by dicing.
In the following description, a stage where a semiconductor element is formed on a wafer substrate (stage before dicing) is referred to as a “semiconductor wafer”. Further, the semiconductor chip is simply referred to as “chip” for explanation.

近年、チップを外部の配線回路基板に接続（実装）する方法として、該チップの電極位置に配線回路基板の導体部分を対応させて両者を接続する方法（例えば、フリップチップボンディング）が用いられるようになっている。外部の配線回路基板とは、チップと共に封止されるパッケージ用回路基板や、他の素子が多数実装される一般的な回路基板などである。
また、チップとパッケージ用回路基板との接続には、インターポーザと称される接点付きのフレキシブル配線回路基板を間に介在させる場合もある（特許文献１、２）。 In recent years, as a method of connecting (mounting) a chip to an external wiring circuit board, a method of connecting the two by associating the conductor portion of the wiring circuit board with the electrode position of the chip (for example, flip chip bonding) has been used. It has become. The external printed circuit board is a package circuit board sealed together with a chip, a general circuit board on which many other elements are mounted, or the like.
In addition, a flexible printed circuit board with contacts called an interposer may be interposed between the chip and the package circuit board (Patent Documents 1 and 2).

前記のようなインターポーザなどのフレキシブルな配線回路基板は、そのフレキシブルな性質のために、チップ実装などの製造工程での取り扱い性は良好ではない。
よって、従来では、特許文献１、２などに示されているとおり、先ず、金属支持基板上にフレキシブルな配線回路基板を形成して適当な剛性を持った該配線回路基板とし、工程での取り扱い性を改善した状態でチップ実装を行ない、剛体であるチップが実装された後に金属支持基板を除去するといった方法が用いられている。 Such a flexible printed circuit board such as an interposer is not easy to handle in a manufacturing process such as chip mounting because of its flexible nature.
Therefore, conventionally, as shown in Patent Documents 1 and 2, etc., first, a flexible printed circuit board is formed on a metal support board to obtain the wired circuit board having appropriate rigidity, and is handled in the process. A method is used in which chip mounting is performed with improved performance, and the metal support substrate is removed after the chip that is a rigid body is mounted.

チップが配線回路基板に実装され、金属支持基板が除去された状態のものは、電極パッドが露出しただけのベアチップと比べて、外部導体（外部回路など）との接続や実装を容易とする接続用導体を備えた１つの半導体装置となっている。
特開２０００−３４９１９８号公報 特開２００１−４４５８９号公報 In the state where the chip is mounted on the printed circuit board and the metal support board is removed, the connection with the external conductor (external circuit, etc.) is easier than the bare chip with the electrode pads exposed. It is one semiconductor device provided with a conductor.
JP 2000-349198 A JP 2001-44589 A

本発明者等が、上記のような従来のフレキシブルな配線回路基板への実装の工程について検討したところ、次に述べる問題が存在することを見出し、これを解決すべき課題とした。
即ち、従来では、上記説明のとおり、金属支持基板上にフレキシブルな配線回路基板を形成し、チップ実装された後に金属支持基板を除去するといった加工を行っている。ここで、金属支持基板と配線回路基板とは、一体不可分な積層体として形成され、チップ実装の後、該金属支持基板を除去する際には、エッチングが用いられている。
本発明者等が見出した問題点は、エッチングによって金属支持基板を除去すると、該金属支持基板が消失するので、該金属支持基板を再利用することができないという点である。また、従来では特に問題とはされていなかったが、エッチングによって金属支持基板を除去する工程があるために、レジストの付与と除去など、製造工程が煩雑になっており、製造コストが高くなっていることも問題である。 When the present inventors examined the process of mounting on the conventional flexible printed circuit board as described above, the present inventors found that the following problems existed and made this a problem to be solved.
That is, conventionally, as described above, a flexible printed circuit board is formed on a metal support substrate, and the metal support substrate is removed after chip mounting. Here, the metal support substrate and the printed circuit board are formed as an integral inseparable laminate, and etching is used to remove the metal support substrate after chip mounting.
The problem found by the present inventors is that when the metal support substrate is removed by etching, the metal support substrate disappears, so that the metal support substrate cannot be reused. In addition, although there has been no particular problem in the past, since there is a process of removing the metal support substrate by etching, the manufacturing process such as application and removal of resist becomes complicated, and the manufacturing cost increases. It is also a problem.

本発明の課題は、本発明者等が着目した上記問題を解消することであって、金属支持基板によって支持されたフレキシブルな配線回路基板にチップを実装した後、エッチングなどの煩雑で該基板を消滅させるような手法を用いることなく該金属支持基板を除去し、該金属支持基板を再利用可能とすることにある。   An object of the present invention is to solve the above-mentioned problem that the present inventors have paid attention to, and after mounting a chip on a flexible printed circuit board supported by a metal support substrate, the substrate is removed by complicated processes such as etching. An object of the present invention is to remove the metal support substrate without using a technique for eliminating the metal support substrate and make the metal support substrate reusable.

本発明者等は、上記課題を解決すべく鋭意研究を行なった結果、配線回路基板に金属製支持体層を剥離可能に付与しておくことによって（即ち、金属製支持体層上に、配線回路基板を該金属製支持体層から剥離可能に形成しておくことによって）、上記課題を解決し得ることを見出し、本発明を完成させた。   As a result of diligent research to solve the above problems, the present inventors have provided a metal support layer in a detachable manner to the printed circuit board (that is, wiring on the metal support layer). The present invention has been completed by finding that the above problem can be solved by forming the circuit board so as to be peelable from the metal support layer.

即ち、本発明は、次の特徴を有するものである。
（１）半導体チップが配線回路基板上に実装された構造を有する半導体装置の製造方法であって、
半導体チップの電極に接続し得る接続用導体部を持った配線回路基板を、金属製支持体層上に、該支持体層から剥離可能となるように、かつ、接続用導体部が該配線回路基板の上面に露出するように形成する工程と、
前記配線回路基板の接続用導体部と半導体チップの電極とを接続して、該配線回路基板に半導体チップを実装する工程と、
前記実装の後、金属製支持体層を配線回路基板から剥離する工程とを、
有することを特微とする、前記半導体装置の製造方法。
（２）金属製支持体層と配線回路基板との間に剥離層が形成されており、それによって、金属製支持体層から配線回路基板が剥離可能となっている、上記（１）記載の製造方法。
（３）剥離層がポリイミドからなる層である、上記（２）に記載の製造方法。
（４）剥離層が、金属、金属酸化物、および、無機酸化物から選ばれる１つの材料からなる層である、上記（２）に記載の製造方法。 That is, the present invention has the following characteristics.
(1) A method of manufacturing a semiconductor device having a structure in which a semiconductor chip is mounted on a printed circuit board,
A wiring circuit board having a connecting conductor portion that can be connected to an electrode of a semiconductor chip can be peeled from the support layer on a metal support layer, and the connecting conductor portion is connected to the wiring circuit. Forming to be exposed on the upper surface of the substrate;
Connecting the conductor part for connection of the wired circuit board and the electrode of the semiconductor chip, and mounting the semiconductor chip on the wired circuit board;
After the mounting, the step of peeling the metal support layer from the printed circuit board,
A method for manufacturing the semiconductor device, characterized by comprising:
(2) The peeling layer is formed between the metal support layer and the wiring circuit board, whereby the wiring circuit board can be peeled from the metal support layer. Production method.
(3) The production method according to (2), wherein the release layer is a layer made of polyimide.
(4) The production method according to (2), wherein the release layer is a layer made of one material selected from a metal, a metal oxide, and an inorganic oxide.

本発明の製造方法によれば、チップを配線回路基板に実装した後、金属製支持体層をエッチングによらず、剥離して除去することができ、金属製支持体層を再利用することが可能になり、製造コストを低減することができる。
また、金属製支持体層の剛直性（スティフネス性）によって、実装される半導体チップ直下の配線回路基板の変形を防止することができる。 According to the manufacturing method of the present invention, after the chip is mounted on the printed circuit board, the metal support layer can be removed without being etched, and the metal support layer can be reused. It becomes possible, and manufacturing cost can be reduced.
In addition, due to the rigidity (stiffness) of the metal support layer, deformation of the printed circuit board directly under the semiconductor chip to be mounted can be prevented.

以下に、具体例に沿って、本発明による製造方法を説明する。尚、本発明で用いている「上面」、「下面」など、上下を示す語句は、あくまで層の位置関係を説明するためのものであって、配線回路層や半導体装置の実際の上下の姿勢を限定するものではない。
図１は、当該製造方法を説明するために、各工程で形成されていく製品の様子を模式的に示した図である。同図に示す配線回路基板内の層構造や接続パターンは説明のために簡略化したものであって、詳細は後述する。
当該製造方法は、先ず、図１（ａ）に示すように、金属製支持体層１の上に、配線回路基板２を、該金属製支持体層１から剥離可能に形成する工程を有する。該配線回路基板２は、接続対象である半導体チップ３の電極３１に接続し得る接続用導体部２１を持っている。本例では、接続用導体部２１は、半導体チップ３の電極３１を直接的に接続し得るように（即ち、ベアチップ実装が可能なように）、金属製支持体層１の側の面とは反対側の面に露出している。実際の製造工程では、接続用導体部２１が露出している面を、さらに剥離ライナーで覆い、半導体チップとの接続に臨んで該剥離ライナーを剥がして用いてもよい。
図１（ａ）では、接続用導体部２１や電極３１などを実際よりも大きく突き出しているように描いているが、これは位置を明確に示すためである。また、同図では、説明のために１つのチップに２つ電極があるように描いているが、実際には、数個〜数万個など、チップの規模や集積度によって電極の数は様々であり、チップの電極面を見たときの電極の配置パターンも様々である。
また、チップの電極には、金スタッドバンプやアンダーバンプメタル（ＵＢＭ）などが形成される。該ＵＢＭとしては、無電解めっきにより形成されるＮｉ／Ａｕ層（Ｎｉが下地側である。他も同様であり、積層の下地側を先に記載している）や、スパッタリング法によるＴｉ／Ｃｕ層、Ｔｉ／Ｗ／Ｃｕ層、Ｔｉ／Ｎｉ／Ｃｕ層などが挙げられる。
また、図１では、配線回路基板２に１つのチップが実装される状態を拡大して描いているが、該配線回路基板は、多数のチップが実装できるものであってよく、そのままアレイとして、または、個々の半導体装置へと分断し得るものであってよい。 Below, the manufacturing method by this invention is demonstrated along a specific example. Note that the terms “upper surface”, “lower surface”, and the like used in the present invention are only for explaining the positional relationship between layers, and are the actual vertical postures of the wiring circuit layer and the semiconductor device. It is not intended to limit.
FIG. 1 is a diagram schematically showing a state of a product formed in each step in order to explain the manufacturing method. The layer structure and connection pattern in the printed circuit board shown in the figure are simplified for the sake of explanation and will be described in detail later.
First, as shown in FIG. 1A, the manufacturing method includes a step of forming a printed circuit board 2 on the metal support layer 1 so as to be peelable from the metal support layer 1. The wired circuit board 2 has a connecting conductor portion 21 that can be connected to the electrode 31 of the semiconductor chip 3 to be connected. In this example, the connecting conductor portion 21 is a surface on the metal support layer 1 side so that the electrode 31 of the semiconductor chip 3 can be directly connected (that is, the bare chip mounting is possible). It is exposed on the opposite side. In the actual manufacturing process, the surface on which the connecting conductor portion 21 is exposed may be further covered with a release liner, and the release liner may be peeled off for connection with the semiconductor chip.
In FIG. 1A, the connecting conductor portion 21, the electrode 31, and the like are drawn so as to protrude larger than actual, but this is for clearly showing the position. Also, in the figure, for the sake of explanation, the drawing is shown such that there are two electrodes on one chip, but in actuality, the number of electrodes varies depending on the size and degree of integration, such as several to tens of thousands. There are various electrode arrangement patterns when the electrode surface of the chip is viewed.
Further, a gold stud bump, an under bump metal (UBM) or the like is formed on the chip electrode. As the UBM, a Ni / Au layer formed by electroless plating (Ni is the base side. The other is the same, and the base side of the laminate is described above), or Ti / Cu by sputtering method. Layer, Ti / W / Cu layer, Ti / Ni / Cu layer and the like.
In FIG. 1, the state in which one chip is mounted on the printed circuit board 2 is illustrated in an enlarged manner. However, the printed circuit board may be one on which a large number of chips can be mounted. Alternatively, it may be divided into individual semiconductor devices.

次に、当該製造方法は、図１（ｂ）に示すように、金属製支持体層１の上に形成された配線回路基板２に対して、ダイシングされた半導体チップ３を実装する工程（実装工程）を有する。この実装工程において、配線回路基板２の接続用導体部２１と、チップ３の電極３１とが接続される。
尚、図１（ｂ）では、実装後の接続用導体部２１、電極３１のそれぞれの突起を省略して描いている。実際の工程においても、半導体チップ３と配線回路基板２とは加圧によって隙間無く密着する。 Next, as shown in FIG. 1B, the manufacturing method includes a step of mounting the diced semiconductor chip 3 on the printed circuit board 2 formed on the metal support layer 1 (mounting). Step). In this mounting process, the connecting conductor portion 21 of the printed circuit board 2 and the electrode 31 of the chip 3 are connected.
In FIG. 1B, the projections of the connecting conductor portion 21 and the electrode 31 after mounting are omitted. Also in the actual process, the semiconductor chip 3 and the printed circuit board 2 are in close contact with each other by pressing.

さらに、当該製造方法は、図１（ｃ）に示すように、金属製支持体層を配線回路基板から剥離する工程（剥離工程）を有する。この剥離工程によって、半導体チップ３が配線回路基板２に実装されてなる半導体装置４が得られる。
尚、該配線回路基板が、ダイシング等による分断を前提とした大面積のものであって、その上に複数のチップが整列的に実装されている場合には、剥離工程の後に、分断工程が加えられて、個々の半導体装置となる。また、金属製支持体層を剥離した配線回路基板に対して、ハンダボールを付与するといった加工を施してもよい。 Further, as shown in FIG. 1C, the manufacturing method includes a step (peeling step) of peeling the metal support layer from the printed circuit board. By this peeling process, a semiconductor device 4 in which the semiconductor chip 3 is mounted on the printed circuit board 2 is obtained.
When the printed circuit board has a large area on the premise of dividing by dicing or the like, and a plurality of chips are mounted in an aligned manner, the dividing step is performed after the peeling step. In addition, individual semiconductor devices are obtained. Moreover, you may perform the process of providing a solder ball with respect to the printed circuit board which peeled the metal support layer.

本発明でいう半導体素子は、配線回路基板に実装し接続し得る素子構造を有するものであればよく、例えば、単一の発光素子のような単純な構造のものやそれを集合させたアレイ、有機半導体素子、ＩＣ、種々の演算回路を集積したプロセッサ、メモリー、フォトセンサー、イメージセンサーなどの従来公知の素子の他、マルチチップモジュール、ＭＥＭＳ（Micro Electro Mechanical Systems；機械要素部品、センサー、アクチュエータ、電子回路などを基板上に集積化したデバイス）などが挙げられる。
半導体素子を形成するためのウェハ基板は、シリコンなどの半導体結晶基板の他、絶縁性の結晶基板、ガラス基板、有機化合物からなる基板など、半導体素子のためのあらゆる基板であってよい。これらの基板のなかでも、最も汎用的なものはシリコン結晶基板（シリコンウェハ）である。
また、半導体素子は、半導体ウェハの段階で再配線層が形成されたものであってもよく、また、素子の基板を貫通するスルーホールビア（導通路）が形成されて、チップ本来の電極とは反対側の面（素子の基板の裏面）まで電極が延伸している態様であってもよい。 The semiconductor element referred to in the present invention may be any element as long as it has an element structure that can be mounted and connected to a printed circuit board. For example, a simple structure such as a single light emitting element or an array in which it is assembled, In addition to conventionally known elements such as organic semiconductor elements, ICs, processors integrating various arithmetic circuits, memories, photosensors, image sensors, etc., multichip modules, MEMS (Micro Electro Mechanical Systems; mechanical element parts, sensors, actuators, A device in which an electronic circuit or the like is integrated on a substrate).
A wafer substrate for forming a semiconductor element may be any substrate for a semiconductor element, such as a semiconductor crystal substrate such as silicon, an insulating crystal substrate, a glass substrate, and a substrate made of an organic compound. Among these substrates, the most general one is a silicon crystal substrate (silicon wafer).
Further, the semiconductor element may be one in which a redistribution layer is formed at the stage of the semiconductor wafer, and a through-hole via (conduction path) that penetrates the substrate of the element is formed, so that the original electrode of the chip and May be an aspect in which the electrode extends to the opposite surface (the back surface of the element substrate).

配線回路基板は、半導体チップが実装されることによって、外部導体への接続に介在するインターポーザとして機能するものであってもよい。
また、上記のように、素子の基板にスルーホールビア（導通路）が設けられ、半導体チップの電極が裏面側へと連絡し得る構造となっている場合には、配線回路基板の接続用導体部を該スルーホールビアの端子に接続してもよい。また、その場合には、配線回路基板を、チップ側において、チップの電極とスルーホールビアとを接続するために用いてもよく、裏面側およびチップ側の両方に配線回路基板を積層してもよい。
チップの電極と配線回路基板の接続用導体部との接続は、ワイヤーボンディングであってもよいが、フリップチップ実装などのように、チップの電極を接続用導体部に直接的に接合する実装態様が好ましい。
フリップチップ実装の場合の接合方法としては、公知の方法を用いることができ、例えば、Ａｕ−Ａｕ接合、Ａｕスタッドバンプ−はんだ接合、はんだバンプ接合、Ａｇペーストを用いた接合、ＡＣＦ（異方導電性フィルム）やＮＣＦ（非導電性フィルム）を用いた接合が挙げられる。ファインピッチに対応するために、Ａｕスタッドバンプ−はんだ接合が好適に用いられる。また、チップと当該配線回路基板との間に、バンプ高さなどの為に間隙が生じる場合には、アンダーフィル材料などを充填してもよい。 The printed circuit board may function as an interposer interposed for connection to an external conductor by mounting a semiconductor chip.
In addition, as described above, when a through-hole via (conduction path) is provided in the substrate of the element and the electrode of the semiconductor chip can be connected to the back side, the connection conductor of the printed circuit board The portion may be connected to the terminal of the through hole via. In that case, the printed circuit board may be used on the chip side to connect the electrode of the chip and the through-hole via, or the printed circuit board may be laminated on both the back side and the chip side. Good.
The connection between the chip electrode and the connection conductor portion of the printed circuit board may be wire bonding, but the mounting mode in which the chip electrode is directly joined to the connection conductor portion, such as flip chip mounting, etc. Is preferred.
As a bonding method in the case of flip chip mounting, a known method can be used, for example, Au-Au bonding, Au stud bump-solder bonding, solder bump bonding, bonding using Ag paste, ACF (anisotropic conductivity) Conductive film) and NCF (non-conductive film). In order to cope with fine pitch, Au stud bump-solder bonding is preferably used. Further, when a gap is generated between the chip and the printed circuit board due to bump height or the like, an underfill material or the like may be filled.

上記したように、配線回路基板は、ダイシングを前提として、複数のチップを実装し得るよう、個々のチップに対応した配線回路基板が１つの平面内に必要数だけ並んで連なり、大面積の配線回路基板となった態様（単品のシート状、ロールから送りだされた帯状の態様など）が量産的であり好ましい。また、チップを多段に積み重ねた態様がパッケージの高密度化には好ましい。また、配線回路基板は複数のチップを実装して１つの半導体装置となるものであってもよい。   As described above, the wiring circuit board is connected to a required number of wiring circuit boards corresponding to each chip in a single plane so that a plurality of chips can be mounted on the premise of dicing. Aspects of a circuit board (single sheet form, strip-like form fed from a roll, etc.) are mass-productive and preferable. Further, an aspect in which chips are stacked in multiple stages is preferable for increasing the density of the package. Further, the printed circuit board may be a semiconductor device in which a plurality of chips are mounted.

配線回路基板の内部構造、導体の接続構造は、特に限定はされないが、有用な基本構造としては、図１（ａ）に示すように、絶縁層の一方の面にチップの電極との接続のための接続用導体部２１を有し、他方の面に外部の導体（当該半導体装置を実装すべき外部回路のパッド等）との接続のための外部接続用導体部が形成され、これらが該絶縁層内に設けられた導体層を通じて互いに接続された構造が挙げられる。
このような典型的な構造例以外に、例えば、図２（ａ）に示すように、特定の接続用導体部２１ａ、２１ｂ同士が互いに接続された構造や、逆に、１つの接続用導体部が複数の外部接続用導体部と接続された構造（図示せず）、また、図２（ｂ）に示すように、特定の接続用導体部２１ａ、２１ｂ同士が層内で互いに接続されているだけで、下面の外部接続用導体部とは接続されていない構造など、その接続構造のパターンは用途に応じて自由に変更し、組合せてよい。
配線回路基板内の配線（層内を横方向に延びる導体層）は、図１、図２に示すように単層であってもよいし、図７に示すように多層であってもよい。 The internal structure of the printed circuit board and the connection structure of the conductor are not particularly limited, but as a useful basic structure, as shown in FIG. 1 (a), the connection of the chip electrode to one surface of the insulating layer is possible. A connecting conductor portion for connecting to an external conductor (such as a pad of an external circuit on which the semiconductor device is to be mounted) is formed on the other surface. Examples include a structure in which they are connected to each other through a conductor layer provided in the insulating layer.
In addition to such a typical structure example, for example, as shown in FIG. 2A, a structure in which specific connection conductor portions 21a and 21b are connected to each other, or conversely, one connection conductor portion. Is connected to a plurality of external connection conductor portions (not shown), and as shown in FIG. 2B, specific connection conductor portions 21a and 21b are connected to each other within the layer. However, the pattern of the connection structure, such as a structure not connected to the external connection conductor on the lower surface, may be freely changed and combined depending on the application.
The wiring in the printed circuit board (the conductor layer extending in the lateral direction in the layer) may be a single layer as shown in FIGS. 1 and 2, or may be a multilayer as shown in FIG.

図３は、配線回路層の内部構造の例をより詳しく示す模式図である。
図３（ａ）に示す例では、絶縁層２０の内部に導体層２３が所定の接続パターンにて形成されており、該導体層２３から素子側へ延びた導通路（金属柱）２４の先端部が接続用導体部２１となっており、逆に、該導体層２３から金属製支持基板側へ延びた導通路（金属柱）２５の先端部が外部接続用導体部２２となっている。図の例では、それぞれの導通路の先端部には、電気的な接続をより好ましく行い耐食性を高めるための金属膜が形成されている。
図３（ｂ）に示す例では、絶縁層２０の内部に、素子側の導体層２６と、金属製支持基板側の導体層２７とが、上下２段に分離した状態にて設けられている。素子側の導体層２６は、絶縁層内に埋没しており（図の例では、接着剤層２０ｂによって覆われている）、金属製支持基板側の導体層２７は、図の例では、剥離層５に直接隣接して設けられている。これら導体層２６、２７は、それらの間の所定位置に設けられた導通路２８によって互いに接続されている。接着剤層２０ｂの上面には、所定の位置に開口が設けられて導体層２６が露出しており、その開口内の露出部分が、素子との接続用導体部２１となっている。一方、図の例では、金属製支持基板側の導体層２７の下面は、全面的に絶縁層の下面に露出しており、金属製支持基板１の下面の所定位置に開口（貫通孔ｈ）が設けられ、剥離層５が除去されて、導体層２７の下面が露出しており、その開口内の露出部分が、外部接続用導体部２２となっている。それぞれの開口内の露出部分は、単に導体層が露出しただけの態様であってもよいが、図の例では、電気的な接続をより好ましく行い耐食性を高めるための金属膜が各露出部分の表面に形成されている。
前記した金属膜の形成方法はメッキが好ましく、該金属膜の材料としては、銅、金、銀、白金、鉛、錫、ニッケル、コバルト、インジウム、ロジウム、クロム、タングステン、ルテニウムなどの単独金属、またはこれら２種類以上からなる合金などが挙げられる。これらの中でも好ましい材料としては、金、錫、ニッケルなどが挙げられ、下地層をＮｉとし、表層をＡｕとする２層構造などが好ましい金属膜の態様として挙げられる。
また、図３（ａ）、（ｂ）に示すように、金属製支持基板に対して、外部接続用導体部２２の位置に開口（貫通孔ｈ）を設けることによって、外部接続用導体部２２の先端部を絶縁層２０ａの下面から突起させることが可能となっている。 FIG. 3 is a schematic diagram showing an example of the internal structure of the wiring circuit layer in more detail.
In the example shown in FIG. 3A, a conductor layer 23 is formed in a predetermined connection pattern inside the insulating layer 20, and the leading end of a conduction path (metal column) 24 extending from the conductor layer 23 to the element side. This portion is a connecting conductor portion 21, and conversely, the leading end portion of a conduction path (metal column) 25 extending from the conductor layer 23 toward the metal support substrate side is an external connecting conductor portion 22. In the example shown in the drawing, a metal film is formed at the tip of each conduction path for more preferable electrical connection and improved corrosion resistance.
In the example shown in FIG. 3B, the element-side conductor layer 26 and the metal support substrate-side conductor layer 27 are provided in the insulating layer 20 in a state of being separated into two upper and lower stages. . The element-side conductor layer 26 is buried in the insulating layer (in the example shown, covered with the adhesive layer 20b), and the metal support substrate-side conductor layer 27 is peeled off in the example shown in the figure. It is provided directly adjacent to layer 5. The conductor layers 26 and 27 are connected to each other by a conduction path 28 provided at a predetermined position between them. An opening is provided at a predetermined position on the upper surface of the adhesive layer 20b to expose the conductor layer 26, and an exposed portion in the opening serves as a conductor portion 21 for connection to the element. On the other hand, in the example of the figure, the lower surface of the conductor layer 27 on the metal support substrate side is exposed entirely on the lower surface of the insulating layer, and is opened at a predetermined position on the lower surface of the metal support substrate 1 (through hole h). , The peeling layer 5 is removed, the lower surface of the conductor layer 27 is exposed, and the exposed portion in the opening serves as the external connection conductor portion 22. The exposed portion in each opening may be a mode in which the conductor layer is simply exposed. However, in the example shown in the figure, a metal film for better electrical connection and improved corrosion resistance is provided in each exposed portion. It is formed on the surface.
The method for forming the metal film is preferably plating, and the metal film is made of a single metal such as copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium, Or the alloy which consists of these 2 types or more is mentioned. Among these, preferable materials include gold, tin, nickel, and the like. A preferable example of the metal film includes a two-layer structure in which the base layer is Ni and the surface layer is Au.
Further, as shown in FIGS. 3A and 3B, the external connection conductor portion 22 is formed by providing an opening (through hole h) at the position of the external connection conductor portion 22 in the metal support substrate. Can be projected from the lower surface of the insulating layer 20a.

配線回路層の絶縁層２０は、同一のポリマーからなる単一層であってもよいが、図３（ａ）、（ｂ）に示すように、金属製支持基板側のベース絶縁層２０ａと、素子に接着するための接着剤層２０ｂとを有する積層構造であってもよい。また、素子の電極と配線回路基板の接続用導体部との接合によって、両者が充分な機械的強度にて一体化する場合は、接着剤層を省略し、接着性の無い公知の絶縁層であってもよい。
ベース絶縁層の材料としては、特に限定はされないが、例えば、ポリイミド樹脂、アクリル樹脂、ポリエーテルニトリル樹脂、ポリエーテルスルホン樹脂、エポキシ樹脂、ポリエチレンテレフタレート樹脂、ポリエチレンナフタレート樹脂、ポリ塩化ビニル樹脂などの公知の合成樹脂や、それらの樹脂と、合成繊維布、ガラス布、ガラス不織布、並びに、ＴｉＯ２、ＳｉＯ２、ＺｒＯ２や鉱物、粘土などの微粒子との複合した樹脂などが挙げられる。特に、金属製支持体層を剥離した後、より薄く、より大きな機械的強度を有し、より好ましい電気的特性（絶縁特性など）を有するフレキシブルな絶縁層となる点からは、ポリイミド樹脂、エポキシ樹脂、ガラス布複合エポキシ樹脂が好ましい材料として挙げられる。
ベース絶縁層の厚さは、３〜５０μｍが好ましい。
接着剤層の材料としては、特に限定はされないが、ポリスルホン、ポリエーテルスルホン、ポリヒダントイン、ポリエーテルイミド、ポリエステル、ポリイミドシロキサン、シロキサン変性ポリアミドイミドなどの熱可塑性樹脂、エポキシ系樹脂、アクリル系樹脂、シリコーン系樹脂、ポリイミド樹脂などが好ましいものとして挙げられ、これらをブレンドして用いてもよい。
尚、エポキシ系樹脂としては、特に限定はされないが、熱可塑性樹脂またはゴムまたはエラストマーなどとブレンドしたエポキシ樹脂や、シリカハイブリッド、ナノ粒子分散型エポキシ樹脂などが挙げられる。
また、アクリル系樹脂としては、特に限定はされないが、例えば、エポキシアクリレート、ウレタンアクリレート、シリコーンアクリレートなどが挙げられる。
接着剤層の厚さは、１〜１００μｍが好ましい。 The insulating layer 20 of the wiring circuit layer may be a single layer made of the same polymer. However, as shown in FIGS. 3A and 3B, the base insulating layer 20a on the metal support substrate side and the element It may be a laminated structure having an adhesive layer 20b for adhering to. In addition, when the electrodes of the element and the connecting conductor portion of the printed circuit board are integrated with sufficient mechanical strength, the adhesive layer is omitted and a known insulating layer having no adhesiveness is used. There may be.
The material of the base insulating layer is not particularly limited, and examples thereof include polyimide resin, acrylic resin, polyether nitrile resin, polyether sulfone resin, epoxy resin, polyethylene terephthalate resin, polyethylene naphthalate resin, and polyvinyl chloride resin. Well-known synthetic resins, and those resins and synthetic fiber cloths, glass cloths, glass nonwoven fabrics, and composite resins of fine particles such as TiO 2 , SiO 2 , ZrO 2 , minerals, and clays can be used. In particular, after peeling off the metal support layer, it becomes thinner, has higher mechanical strength, and becomes a flexible insulating layer having more preferable electrical characteristics (insulating characteristics, etc.). Resin and glass cloth composite epoxy resin are preferable materials.
The thickness of the base insulating layer is preferably 3 to 50 μm.
The material of the adhesive layer is not particularly limited, but is a thermoplastic resin such as polysulfone, polyethersulfone, polyhydantoin, polyetherimide, polyester, polyimidesiloxane, siloxane-modified polyamideimide, epoxy resin, acrylic resin, Silicone resins, polyimide resins and the like are preferred, and these may be blended and used.
The epoxy resin is not particularly limited, and examples thereof include an epoxy resin blended with a thermoplastic resin, rubber, or elastomer, a silica hybrid, and a nanoparticle dispersed epoxy resin.
In addition, the acrylic resin is not particularly limited, and examples thereof include epoxy acrylate, urethane acrylate, and silicone acrylate.
As for the thickness of an adhesive bond layer, 1-100 micrometers is preferable.

金属製支持体層上に配線回路基板を形成する方法には、セミアディティブ法や、サブトラクティブ法など、従来公知の回路基板やインターポーザの製造技術を適用してもよい。
金属製支持体層上に配線回路基板を形成することにより、製造工程中、寸法安定性が良好となり、また、薄い配線回路基板の取り扱い性が良好となる。 Conventionally known circuit board and interposer manufacturing techniques such as a semi-additive method and a subtractive method may be applied to the method for forming the printed circuit board on the metal support layer.
By forming the printed circuit board on the metal support layer, the dimensional stability is improved during the manufacturing process, and the handleability of the thin printed circuit board is improved.

セミアディティブ法によって配線回路基板内に導体層や導通路を形成する場合には、図４に示すように、導体層２３および導通路２５となるべき部分の壁面に金属材料を良好に堆積させるための種膜（金属薄膜）２３ａを予めスパッタリングによって形成しておくことが好ましい。そのような種膜の材料としては、例えば、銅、金、銀、白金、鉛、錫、ニッケル、コバルト、インジウム、ロジウム、クロム、タングステン、ルテニウムなどの単独金属、またはこれら２種類以上からなる合金などが用いられる。   In the case of forming a conductor layer or a conductive path in the printed circuit board by the semi-additive method, as shown in FIG. The seed film (metal thin film) 23a is preferably formed in advance by sputtering. Examples of such seed film materials include copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium and other single metals, or alloys composed of two or more of these. Etc. are used.

図３に示す導体層２３、２６、２７および導通路２４、２５、２８の材料としては、例えば、銅、金、銀、白金、鉛、錫、ニッケル、コバルト、インジウム、ロジウム、クロム、タングステン、ルテニウムなどから選ばれる単独金属や、または、これらを成分とする合金（例えば、はんだ、ニッケル−錫、金−コバルトなど）が挙げられる。これらのなかでも、電解メッキまたは無電解メッキ可能な金属が好ましく用いられる。導体層の回路パターンの形成容易性、および、電気的特性が優れている点からは、銅が好ましい材料として挙げられる。
導体層２３の厚さは、特に限定はされないが、１〜５０μｍの範囲で適宜選択すればよい。また、導通路２４、２５は円柱状が好ましい形状であって、その直径は５〜５００μｍ、好ましくは、５〜３００μｍである。 As the material of the conductor layers 23, 26, 27 and the conduction paths 24, 25, 28 shown in FIG. 3, for example, copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, Examples thereof include single metals selected from ruthenium and the like, and alloys containing these metals (for example, solder, nickel-tin, gold-cobalt, etc.). Among these, metals that can be electroplated or electrolessly plated are preferably used. From the viewpoint of ease of forming the circuit pattern of the conductor layer and excellent electrical characteristics, copper is a preferred material.
The thickness of the conductor layer 23 is not particularly limited, but may be appropriately selected within a range of 1 to 50 μm. In addition, the conduction paths 24 and 25 are preferably cylindrical, and the diameter thereof is 5 to 500 μm, preferably 5 to 300 μm.

金属製支持体層の材料は、特に限定はされないが、銅または、銅を主体とする銅合金、ニッケルまたはニッケルを主体とするニッケル合金、ニッケルと鉄を主な成分とする合金、ステンレスなどが好ましい材料として挙げられる。
半導体チップとの線膨張係数の差を小さくするために、ニッケルと鉄を主な成分とする合金（例えば、４２アロイ）を用いることが好ましい。 The material of the metal support layer is not particularly limited, but copper, a copper alloy mainly composed of copper, a nickel alloy mainly composed of nickel or nickel, an alloy mainly composed of nickel and iron, stainless steel, etc. It is mentioned as a preferable material.
In order to reduce the difference in linear expansion coefficient from the semiconductor chip, it is preferable to use an alloy (for example, 42 alloy) containing nickel and iron as main components.

金属製支持基板の厚さは、材料の剛性にもよるが、１０μｍ〜２００μｍ程度が好ましく、２０μｍ〜８０μｍ程度がより好ましい。
金属製支持基板の厚さが１０μｍを下回ると、該金属製支持基板に折れやシワが生じやすくなり、ロールプロセスでの取り扱い性が低下する。また、金属製支持基板の厚さが２００μｍを上回ると、その剛性によって巻き径が大きくなり、ロールプロセスでの取り扱いが困難となり、エッチングによる加工も困難となる。 The thickness of the metal support substrate is preferably about 10 μm to 200 μm, more preferably about 20 μm to 80 μm, although it depends on the rigidity of the material.
When the thickness of the metal support substrate is less than 10 μm, the metal support substrate is likely to be bent or wrinkled, and the handleability in the roll process is lowered. On the other hand, if the thickness of the metal support substrate exceeds 200 μm, the winding diameter increases due to its rigidity, making it difficult to handle in a roll process, and making processing by etching difficult.

金属製支持体層と配線回路基板とをよりスムーズに剥離するためには、両者の間に剥離層を介在させる構造が好ましい。剥離層は、配線回路基板からは容易に剥離し、金属製支持体層からは剥離し難いように形成し、該剥離層が金属製支持体層と一体的に配線回路基板から剥がれるようにすることが好ましい。
剥離層の材料としては、有機物（シリコーン樹脂、ポリイミドなど）、無機物（金属、金属酸化物、無機酸化物など）が挙げられる。前記無機物としては、Ａｇ、Ｔｉ、Ｗ、Ｎｉ、ＳｉＯ2などが例示される。
配線回路基板の製造工程や、チップを配線回路基板に実装する際の高熱条件を考慮すると、シリコーン樹脂は劣化する場合があるので、ポリイミドや前記無機物がより好ましい材料である。 In order to more smoothly separate the metal support layer and the printed circuit board, a structure in which a release layer is interposed between the two is preferable. The release layer is formed so as to be easily peeled off from the printed circuit board and hardly peeled off from the metal support layer, so that the release layer is peeled off from the printed circuit board integrally with the metal support layer. It is preferable.
Examples of the material for the release layer include organic substances (silicone resin, polyimide, etc.) and inorganic substances (metal, metal oxide, inorganic oxide, etc.). Examples of the inorganic material include Ag, Ti, W, Ni, and SiO 2 .
In consideration of the manufacturing process of the printed circuit board and high heat conditions when the chip is mounted on the printed circuit board, the silicone resin may be deteriorated, and therefore, polyimide and the inorganic substance are more preferable materials.

剥離層をポリイミド層とする場合、その厚さは０．１〜１０μｍが好ましく、配線回路基板全体の反りを防止するためには、０．１〜５μｍがより好ましい。
剥離層を前記無機物からなる層とする場合、その厚さは、１〜１００ｎｍが好ましく、配線回路基板全体の反りを防止するためには、１〜５０ｎｍがより好ましい。
剥離層を、ポリイミド層とする場合の該層の形成方法としては、溶液を塗工する方法、電着法やＣＶＤ法によって堆積させる方法、または、別途形成したポリイミドフィルムをラミネートする方法などが挙げられる。また、剥離層を、金属、金属酸化物、無機酸化物などの無機物からなる層とする場合の該層の形成方法としては、電解めっき法、真空蒸着法、スパッタリング法などが挙げられる。 When the release layer is a polyimide layer, the thickness is preferably 0.1 to 10 μm, and more preferably 0.1 to 5 μm in order to prevent warpage of the entire printed circuit board.
When the release layer is a layer made of the inorganic material, the thickness is preferably 1 to 100 nm, and more preferably 1 to 50 nm in order to prevent warpage of the entire printed circuit board.
Examples of the method for forming the release layer when the release layer is a polyimide layer include a method of applying a solution, a method of depositing by an electrodeposition method or a CVD method, or a method of laminating a separately formed polyimide film. It is done. Examples of the method for forming the release layer when the release layer is a layer made of an inorganic material such as a metal, a metal oxide, or an inorganic oxide include an electrolytic plating method, a vacuum deposition method, and a sputtering method.

以下、実際の製造例を挙げて、本発明の製造方法をより具体的かつ詳細に説明する。以下の説明に用いる図４〜７の配線回路基板は、いずれも、１つの接続用導体部と、それに裏面で対応する１つの外部接続用導体部だけを拡大して描いたものである。   Hereinafter, the production method of the present invention will be described more specifically and in detail by giving actual production examples. The printed circuit boards of FIGS. 4 to 7 used in the following description are each drawn by enlarging only one connection conductor portion and one external connection conductor portion corresponding on the back surface thereof.

実施例１
本実施例では、ステンレス（ＳＵＳ３０４）からなる金属製支持体層上に、ポリイミドからなる剥離層を形成し、その上に配線回路基板を形成した。本実施例で形成した配線回路基板は、その面上に、半導体チップを（４×１１）行列状の配置にて実装し得るよう、同じ形状の実装領域が繰り返しパターンにて面上に並んだものである。また、外部接続用導体部の端面に接点用の貴金属めっきを施す手順として、本実施例では、金属製支持体層に下面から開口を形成し、外部接続用導体部の端面を露出させてめっきを施している。
半導体チップは、電極パッドの数が２４０個、各パッドは直径８０μｍの円形であって、各パッド上には直径６０μｍの金スタッドバンプが形成されたものである。 Example 1
In this example, a release layer made of polyimide was formed on a metal support layer made of stainless steel (SUS304), and a printed circuit board was formed thereon. In the printed circuit board formed in this example, mounting regions of the same shape are arranged in a repeating pattern on the surface so that semiconductor chips can be mounted in a (4 × 11) matrix arrangement on the surface. Is. In addition, as a procedure for performing contact noble metal plating on the end face of the external connection conductor portion, in this embodiment, an opening is formed in the metal support layer from the lower surface, and the end face of the external connection conductor portion is exposed to perform plating. Has been given.
The semiconductor chip has 240 electrode pads, each pad is circular with a diameter of 80 μm, and gold stud bumps with a diameter of 60 μm are formed on each pad.

〔剥離層の形成〕
図４（ａ）に示すように、金属製支持体層１として、厚さ５０μｍのＳＵＳ３０４からなる箔を用い、その上に、ポリアミック酸溶液（ピロメリット酸二無水物と２, ２’−ジメチル−４, ４’−ジアミノビフェニルを反応して得たもの）を塗布し、加熱により乾燥、イミド化することによって、厚さ２μｍのポリイミド剥離層５を全面に形成した。 (Formation of release layer)
As shown in FIG. 4 (a), a foil made of SUS304 having a thickness of 50 [mu] m was used as the metal support layer 1, and a polyamic acid solution (pyromellitic dianhydride and 2,2'-dimethyl) was formed thereon. -4,4'-diaminobiphenyl) was applied, dried and imidized by heating to form a polyimide release layer 5 having a thickness of 2 μm on the entire surface.

〔ベース絶縁層の形成〕
図４（ｂ）に示すように、感光性ポリアミック酸（３，４’，３，４’−ビフェニルテトラカルボン酸二無水物と、４，４’−ジアミノジフェニルエーテル、パラフェニレンジアミンとを反応させて得たもので、感光剤を含有する）を用いて、ポリイミド層（ベース絶縁層）２０ａを形成した。また、外部接続用導体部を形成すべき位置には、開口ｈ１を形成した。該開口の底には剥離層が露出している。ベース絶縁層の厚さは５μｍ、開口形状は円形であり、直径１００μｍである。 [Formation of base insulating layer]
As shown in FIG. 4 (b), photosensitive polyamic acid (3,4 ', 3,4'-biphenyltetracarboxylic dianhydride, 4,4'-diaminodiphenyl ether, and paraphenylenediamine were reacted. A polyimide layer (base insulating layer) 20a was formed using the obtained product containing a photosensitizer. Further, an opening h1 was formed at a position where the external connection conductor portion was to be formed. A release layer is exposed at the bottom of the opening. The insulating base layer has a thickness of 5 μm, the opening has a circular shape, and has a diameter of 100 μm.

〔種膜、下側の導通路、導体層の形成〕
図４（ｃ）に示すように、クロム、銅の順にスパッタリングを施して、種膜（クロム層の厚さ２０ｎｍ、銅層の厚さ１００ｎｍ）２３ａを形成し、電解銅めっきにより、所定の配線パターンとされた導体層２３、導通路２５を形成した。その後、導体層２３の無い部分の種膜を除去した。種膜のうちの銅層は、導通路および導体層の銅と一体化するので、図４（ｃ）では、該種膜２３ａをクロムからなる一層のように描いている。図５〜図７も同様である。 [Formation of seed film, lower conductive path, conductor layer]
As shown in FIG. 4C, sputtering is performed in the order of chromium and copper to form a seed film (chrome layer thickness 20 nm, copper layer thickness 100 nm) 23a, and predetermined wiring is formed by electrolytic copper plating. A patterned conductor layer 23 and conductive path 25 were formed. Thereafter, the seed film in the portion without the conductor layer 23 was removed. Since the copper layer of the seed film is integrated with the copper of the conductive path and the conductor layer, in FIG. 4C, the seed film 23a is drawn as a single layer made of chromium. The same applies to FIGS.

〔金属製支持体層への開口形成〕
図４（ｄ）に示すように、金属製支持体層１の下面側から、導通路２５に対応する位置に、塩化第２鉄水溶液にて直径３００μｍの開口ｈ２を形成し、該開口ｈ２内に剥離層（ポリイミド層）５を露出させ、さらに、該剥離層５をアルカリ性処理液にてエッチング除去し、種膜（クロム層）２３ａを露出させ、該クロム層をフェリシアン化カリウムと水酸化ナトリウムの混合水溶液にて、エッチングし、銅層を露出させた。 [Opening to the metal support layer]
As shown in FIG. 4D, an opening h2 having a diameter of 300 μm is formed with a ferric chloride aqueous solution at a position corresponding to the conduction path 25 from the lower surface side of the metal support layer 1, and the opening h2 is formed in the opening h2. Then, the release layer (polyimide layer) 5 is exposed, and the release layer 5 is removed by etching with an alkaline treatment liquid to expose the seed film (chromium layer) 23a. The chromium layer is made of potassium ferricyanide and sodium hydroxide. Etching was performed with a mixed aqueous solution to expose the copper layer.

〔上側の導通路の形成〕
図４（ｅ）に示すように、導体層２３の上をめっきレジストｒ１にて覆い（導通路を形成すべき部分は除く）、かつ、金属製支持体層１の下面および開口ｈ２を全面的にレジストｒ２にて覆い、電解銅めっきにより、直径８０μｍ、高さ１５μｍの導通路２４を形成した。 [Formation of upper conduction path]
As shown in FIG. 4E, the conductor layer 23 is covered with a plating resist r1 (except for a portion where a conduction path is to be formed), and the lower surface of the metal support layer 1 and the opening h2 are entirely covered. The conductive path 24 having a diameter of 80 μm and a height of 15 μm was formed by electrolytic copper plating.

〔接着剤層の形成〕
図４（ｆ）に示すように、上記めっきレジストｒ１、ｒ２を除去し、露出した導体層２３および導通路２４を埋没させるように、エポキシ及びポリイミドを主成分とする接着剤層２０ｂを形成し、導通路２４の上端面が端子部として接着層上面に露出するように、該接着層をアルカリ性溶液にてエッチングした。 (Formation of adhesive layer)
As shown in FIG. 4 (f), an adhesive layer 20b mainly composed of epoxy and polyimide is formed so that the plating resists r1 and r2 are removed and the exposed conductor layer 23 and conductive path 24 are buried. The adhesive layer was etched with an alkaline solution so that the upper end surface of the conduction path 24 was exposed as a terminal portion on the upper surface of the adhesive layer.

〔端子部への金属膜の形成〕
図４（ｇ）に示すように、導通路２４の上面、および、金属製支持体層の開口内の底面（導通路２５の下端面）に、電解めっきにより、ニッケル膜（厚さ２μｍ）、金膜（厚さ０．５μｍ）を順次形成した。 [Formation of metal film on terminal part]
As shown in FIG. 4G, a nickel film (thickness 2 μm) is formed on the upper surface of the conduction path 24 and the bottom surface in the opening of the metal support layer (the lower end face of the conduction path 25) by electrolytic plating. Gold films (thickness 0.5 μm) were sequentially formed.

〔実装工程、剥離工程、ダイシング〕
上記で得た配線回路基板（金属製支持体層が剥離可能に付いたもの）の全ての実装領域にそれぞれチップを実装した。
イーヴィグループ社製のアライナー、ボンディング装置を用いて、アライメントを行い、真空度３Ｐａ、温度３００℃、圧力１．５ｇ／バンプの圧力にて、チップを実装した後、１８０℃にて２時間、接着剤層のエージングを行った。
さらに、配線回路基板上の各チップに樹脂封止を施した後、剥離層５とベース絶縁層２０ａとの界面で剥離して、該剥離層５と金属製支持体層とを除去し、個々の半導体装置へとダイシングした。 [Mounting process, peeling process, dicing]
Chips were respectively mounted on all the mounting regions of the printed circuit board obtained above (with the metal support layer being peelable).
Alignment is performed using an aligner and bonding equipment manufactured by Evi Group, and after mounting the chip at a vacuum of 3 Pa, a temperature of 300 ° C., and a pressure of 1.5 g / bump, bonding is performed at 180 ° C. for 2 hours. The agent layer was aged.
Further, after sealing each chip on the printed circuit board with a resin, it is peeled off at the interface between the peeling layer 5 and the base insulating layer 20a, and the peeling layer 5 and the metal support layer are removed. Dicing into a semiconductor device.

実施例２
本実施例では、外部接続用導体部の端面に接点用の貴金属めっきを施す手順として、金属製支持体層には開口を形成せず、初めから剥離層の所定位置に開口を設け、先に接点用の貴金属層を形成し、その上に導通路を形成している。 Example 2
In this example, as a procedure for applying the noble metal plating for the contact to the end face of the external connection conductor part, an opening is not formed in the metal support layer, but an opening is provided at a predetermined position of the peeling layer from the beginning. A noble metal layer for contact is formed, and a conduction path is formed thereon.

〔剥離層の形成〕
図５（ａ）に示すように、金属製支持体層１として、実施例１と同様のステンレス箔を用い、その上に、実施例１と同様の感光性ポリアミック酸溶液を用いて、ポリイミドから成る厚さ２μｍの剥離層５を形成した。剥離層のうち、外部接続用導体部を形成すべき所定位置には、開口ｈ３が設けられている。該開口の形状は円形であって、直径１００μｍである。 (Formation of release layer)
As shown in FIG. 5 (a), as the metal support layer 1, a stainless steel foil similar to that of Example 1 is used, and a photosensitive polyamic acid solution similar to that of Example 1 is used thereon, and polyimide is used. A release layer 5 having a thickness of 2 μm was formed. An opening h3 is provided at a predetermined position in the peeling layer where the external connection conductor portion is to be formed. The shape of the opening is circular and has a diameter of 100 μm.

〔ベース絶縁層の形成、接点用の金属膜の形成〕
図５（ｂ）に示すように、実施例１と同様の感光性ポリアミック酸を用いて、開口ｈ３と一致した開口ｈ４を有するポリイミド層を形成し、ベース絶縁層２０ａとした。該ベース絶縁層２０ａの厚さは５μｍ、開口形状は円形であり、直径１００μｍである。
そして、開口（ｈ４＋ｈ３）内に露出している金属製支持体層の表面に、電解めっきにより、金層２１２、ニッケル層２１１を順次形成した。 [Formation of insulating base layer, formation of metal film for contact]
As shown in FIG. 5B, a polyimide layer having an opening h4 coinciding with the opening h3 was formed using the same photosensitive polyamic acid as in Example 1 to obtain a base insulating layer 20a. The insulating base layer 20a has a thickness of 5 μm, the opening shape is circular, and has a diameter of 100 μm.
Then, a gold layer 212 and a nickel layer 211 were sequentially formed on the surface of the metal support layer exposed in the opening (h4 + h3) by electrolytic plating.

〔種膜、下側の導通路、導体層の形成〕
図５（ｃ）に示すように、クロム、銅の順にスパッタリングを施して、種膜（クロム層の厚さ２０ｎｍ、銅層の厚さ１００ｎｍ）２３ａを形成し、電解銅めっきにより、所定の配線パターンとされた導体層２３、導通路２５を形成した。その後、導体層２３の無い部分の種膜を除去した。 [Formation of seed film, lower conductive path, conductor layer]
As shown in FIG. 5C, sputtering is performed in the order of chromium and copper to form a seed film (chrome layer thickness 20 nm, copper layer thickness 100 nm) 23a, and predetermined wiring is formed by electrolytic copper plating. A patterned conductor layer 23 and conductive path 25 were formed. Thereafter, the seed film in the portion without the conductor layer 23 was removed.

〔上側の導通路の形成〕
図５（ｄ）に示すように、導体層２３の上をめっきレジストｒ１にて覆い（導通路を形成すべき部分は除く）、かつ、金属製支持体層１の下面を全面的にレジストｒ２にて覆い、電解銅めっきにより、直径８０μｍ、高さ１５μｍの導通路２４を形成した。 [Formation of upper conduction path]
As shown in FIG. 5D, the conductor layer 23 is covered with a plating resist r1 (except for a portion where a conduction path is to be formed), and the lower surface of the metal support layer 1 is entirely covered with a resist r2. And a conductive path 24 having a diameter of 80 μm and a height of 15 μm was formed by electrolytic copper plating.

〔接着剤層の形成〕
図５（ｅ）に示すように、上記実施例１と同様の材料、手順にて、めっきレジストｒ１、ｒ２を除去し、露出した導体層２３および導通路２４を埋没させるように、接着剤層２０ｂを形成し、導通路２４の上端面が端子部として接着層上面に露出するように、該接着層をエッチングした。 (Formation of adhesive layer)
As shown in FIG. 5 (e), the adhesive layer is formed so that the plating resists r1 and r2 are removed and the exposed conductor layer 23 and conductive path 24 are buried by the same material and procedure as in the first embodiment. 20b was formed, and the adhesive layer was etched so that the upper end surface of the conduction path 24 was exposed as a terminal portion on the upper surface of the adhesive layer.

〔接続用導体部の端面への金属膜の形成〕
図５（ｆ）に示すように、導通路２４の上端面に、電解めっきにより、ニッケル膜（厚さ２μｍ）、金膜（厚さ０．５μｍ）を順次形成した。
本実施例２では、図５（ａ）のように、最初に剥離層に開口を形成したので、実施例１に比べて、図４（ｄ）のように、端子のニッケルめっき、金めっきのために、金属製支持体層に開口部を形成する必要がない。 [Formation of metal film on end face of connecting conductor]
As shown in FIG. 5F, a nickel film (thickness 2 μm) and a gold film (thickness 0.5 μm) were sequentially formed on the upper end surface of the conduction path 24 by electrolytic plating.
In Example 2, since the opening was first formed in the release layer as shown in FIG. 5A, compared to Example 1, as shown in FIG. Therefore, it is not necessary to form an opening in the metal support layer.

〔実装工程、剥離工程、ダイシング〕
上記で得た配線回路基板（金属製支持体層が剥離可能に付いたもの）に対して、実施例１と同様の手順にてチップ実装、樹脂封止を行ない、剥離層と金属製支持体層とを除去し、各素子へダイシングを行ない、半導体装置を得た。 [Mounting process, peeling process, dicing]
The printed circuit board (with the metal support layer releasably attached) obtained above is subjected to chip mounting and resin sealing in the same procedure as in Example 1, and the release layer and the metal support body. The layer was removed and dicing was performed on each element to obtain a semiconductor device.

実施例３
本実施例では、剥離層の材料として金属を用いた。
〔剥離層の形成〕
図６（ａ）に示すように、金属製支持体層１として、実施例１と同様のステンレス箔を用い、その上に、Ａｇから成る剥離層５（厚さ２５ｎｍ）を、真空蒸着法にて形成した。 Example 3
In this example, metal was used as the material for the release layer.
(Formation of release layer)
As shown in FIG. 6 (a), the same stainless steel foil as in Example 1 was used as the metal support layer 1, and a release layer 5 (thickness 25 nm) made of Ag was formed thereon by vacuum evaporation. Formed.

〔ベース絶縁層の形成、接点用の金属膜の形成〕
図６（ｂ）に示すように、実施例１と同様の感光性ポリアミック酸を用いて、開口ｈ５を有するポリイミド層を形成し、ベース絶縁層２０ａとした。該ベース絶縁層２０ａの厚さは５μｍ、開口形状は円形であり、直径１００μｍである。
そして、開口内に露出しているＡｇの表面に、電解めっきにより、金層２１２、ニッケル層２１１を順次形成した。 [Formation of insulating base layer, formation of metal film for contact]
As shown in FIG. 6B, a polyimide layer having an opening h5 was formed using the same photosensitive polyamic acid as in Example 1 to form a base insulating layer 20a. The insulating base layer 20a has a thickness of 5 μm, the opening shape is circular, and has a diameter of 100 μm.
Then, a gold layer 212 and a nickel layer 211 were sequentially formed on the surface of Ag exposed in the opening by electrolytic plating.

〔種膜、下側の導通路、導体層の形成〕
図６（ｃ）に示すように、クロム、銅の順にスパッタリングを施して、種膜（クロム層の厚さ２０ｎｍ、銅層の厚さ１００ｎｍ）２３ａを形成し、電解銅めっきにより、所定の配線パターンとされた導体層２３、導通路２５を形成した。その後、導体層２３の無い部分の種膜を除去した。 [Formation of seed film, lower conductive path, conductor layer]
As shown in FIG. 6C, sputtering is performed in the order of chromium and copper to form a seed film (chrome layer thickness 20 nm, copper layer thickness 100 nm) 23a, and predetermined wiring is formed by electrolytic copper plating. A patterned conductor layer 23 and conductive path 25 were formed. Thereafter, the seed film in the portion without the conductor layer 23 was removed.

図６（ｄ）に示すように、導体層２３の上をめっきレジストｒ１にて覆い（導通路を形成すべき部分は除く）、かつ、金属製支持体層１の下面を全面的にレジストｒ２にて覆い、電解銅めっきにより、直径８０μｍ、高さ１５μｍの導通路２４を形成した。   As shown in FIG. 6D, the conductor layer 23 is covered with a plating resist r1 (except for a portion where a conduction path is to be formed), and the lower surface of the metal support layer 1 is entirely covered with a resist r2. The conductive path 24 having a diameter of 80 μm and a height of 15 μm was formed by electrolytic copper plating.

〔接着剤層の形成〕
図６（ｅ）に示すように、上記実施例１と同様の材料、手順にて、めっきレジストｒ１、ｒ２を除去し、露出した導体層２３および導通路２４を埋没させるように、接着剤層２０ｂを形成し、導通路２４の上端面が端子部として接着層上面に露出するように、該接着層をエッチングした。 (Formation of adhesive layer)
As shown in FIG. 6 (e), the adhesive layer is formed so that the plating resists r1 and r2 are removed and the exposed conductor layer 23 and conductive path 24 are buried by the same material and procedure as in the first embodiment. 20b was formed, and the adhesive layer was etched so that the upper end surface of the conduction path 24 was exposed as a terminal portion on the upper surface of the adhesive layer.

〔接続用導体部の端面への金属膜の形成〕
図６（ｆ）に示すように、導通路２４の上端面に、電解めっきにより、ニッケル膜（厚さ２μｍ）２１１、金膜（厚さ０．５μｍ）２１２を順次形成した。
本実施例３では、図６（ｂ）のように、剥離層（Ａｇ層）を通して通電し、金、ニッケルめっきができるので、実施例１に比べて、図４（ｄ）のように、端子のニッケルめっき、金めっきのために、金属製支持体層に開口部を形成する必要がない。 [Formation of metal film on end face of connecting conductor]
As shown in FIG. 6F, a nickel film (thickness 2 μm) 211 and a gold film (thickness 0.5 μm) 212 were sequentially formed on the upper end surface of the conduction path 24 by electrolytic plating.
In this third embodiment, as shown in FIG. 6B, it is possible to energize through the peeling layer (Ag layer) and perform gold and nickel plating. Therefore, as compared with the first embodiment, as shown in FIG. It is not necessary to form an opening in the metal support layer for the nickel plating and gold plating.

〔実装工程、剥離工程、ダイシング〕
上記で得た配線回路基板（金属製支持体層が剥離可能に付いたもの）に対して、実施例１と同様の手順にてチップ実装、樹脂封止を行ない、剥離層と金属製支持体層とを除去し、各素子へのダイシングを行ない、半導体装置を得た。 [Mounting process, peeling process, dicing]
The printed circuit board (with the metal support layer releasably attached) obtained above is subjected to chip mounting and resin sealing in the same procedure as in Example 1, and the release layer and the metal support body. The layer was removed and dicing was performed on each element to obtain a semiconductor device.

実施例４
本実施例では、剥離層の材料をＴｉとし、厚さを１８ｎｍとし、該剥離層の形成法をＲＦ（Radio Frequency：高周波）スパッタリング法としたこと以外は、上記実施例と全く同様にして、半導体装置を形成した。 Example 4
In this example, the material of the release layer was Ti, the thickness was 18 nm, and the formation method of the release layer was the same as the above example, except that the RF (Radio Frequency) sputtering method was used, A semiconductor device was formed.

実施例５
本実施例では、剥離層の材料として無機酸化物（ＳｉＯ2）を用いた。
〔剥離層の形成〕
図４（ａ）に示すように、金属製支持体層１として、実施例１と同様のステンレス箔を用い、その上に、ＳｉＯ2 から成る剥離層５（厚さ７ｎｍ）を、スパッタリング法で形成した。
以下、〔ベース絶縁層の形成、接点用の金属膜の形成〕、〔種膜、下側の導通路、導体層の形成〕、〔接着剤層の形成〕、〔接続用導体部の端面への金属膜の形成〕、〔実装工程、剥離工程、ダイシング〕の手順、材料等は、実施例１と全く同様にして、半導体装置を得た。
なお、本実施例では、図４（ｄ）に示した工程において、金属製支持体層１の下面側から開口をエッチングで形成する際に、剥離層であるＳｉＯ2膜が非常に薄いので、金属製支持体層のエッチングによって、該剥離層も同時に除去される。 Example 5
In this example, an inorganic oxide (SiO 2 ) was used as a material for the release layer.
(Formation of release layer)
As shown in FIG. 4A, the same stainless steel foil as in Example 1 was used as the metal support layer 1, and a release layer 5 (thickness 7 nm) made of SiO 2 was formed thereon by a sputtering method. Formed.
Hereinafter, [formation of base insulating layer, formation of metal film for contact], [formation of seed film, lower conductive path, conductor layer], [formation of adhesive layer], [to end surface of connecting conductor portion] Formation of Metal Film], [Mounting Process, Peeling Process, Dicing] Procedure, Materials, etc. were exactly the same as in Example 1 to obtain a semiconductor device.
In this example, in the process shown in FIG. 4D, when the opening is formed by etching from the lower surface side of the metal support layer 1, the SiO 2 film as the peeling layer is very thin. The release layer is also removed simultaneously by etching the metal support layer.

実施例６
本実施例では、図７に示すように、導体層を多層とした配線回路基板の製造例を示す。
図７の例は、ベース絶縁層と導体層とが繰り返して積層されていること以外は、上記実施例１で得られた構造と同様である。
本実施例では、図４（ａ）の〔金属製支持体層上への剥離層の形成〕から、図４（ｄ）の〔金属製支持体層への開口形成〕までは、実施例１と同様の加工を行う。この加工によって、図７に示すように、金属製支持体層１、剥離層５、第一のベース絶縁層２０１、第一の導通路２５１、第一の導体層２３１が形成される。種膜も、実施例１と同様である。
次に、本実施例では、図４（ｅ）の工程に進む替わりに、図４（ｂ）と同様の加工を再び行ない、第一の導体層２３１を第二のベース絶縁層２０２で埋め込み、その所定位置に開口を形成して、図４（ｃ）の如く、第二の導通路２５２、第二の導体層２３２を形成する。さらに前記と同様の加工を再び行ない、第三のベース絶縁層２０３、第三の導通路２５３、第三の導体層２３３を形成する。
次に、図４（ｅ）〜（ｆ）の工程に進み、上側の導通路２４の形成、接着剤層２０ｂの形成、端子部２１への金属膜の形成を行なう。
以上の加工によって、図７の配線回路基板を得た。 Example 6
In this embodiment, as shown in FIG. 7, an example of manufacturing a printed circuit board having a multi-layered conductor layer is shown.
The example of FIG. 7 is the same as the structure obtained in Example 1 except that the base insulating layer and the conductor layer are repeatedly laminated.
In this example, the steps from [Formation of release layer on metal support layer] in FIG. 4 (a) to [Formation of opening in metal support layer] in FIG. The same processing is performed. By this processing, as shown in FIG. 7, the metal support layer 1, the release layer 5, the first insulating base layer 201, the first conduction path 251, and the first conductor layer 231 are formed. The seed film is also the same as in Example 1.
Next, in this embodiment, instead of proceeding to the step of FIG. 4E, the same processing as in FIG. 4B is performed again, and the first conductor layer 231 is embedded with the second base insulating layer 202, An opening is formed at the predetermined position, and a second conduction path 252 and a second conductor layer 232 are formed as shown in FIG. Further, the same processing as described above is performed again to form the third insulating base layer 203, the third conductive path 253, and the third conductor layer 233.
Next, the process proceeds to the steps of FIGS. 4E to 4F, and the upper conductive path 24, the adhesive layer 20b, and the metal film on the terminal portion 21 are formed.
With the above processing, the printed circuit board of FIG. 7 was obtained.

本発明の製造方法によれば、金属製支持体層によって支持されたフレキシブルな配線回路基板にチップを実装した後、該金属製支持体層を簡単に剥離することができ、しかも、該金属製支持体層は、再利用可能となる。   According to the manufacturing method of the present invention, after mounting a chip on a flexible printed circuit board supported by a metal support layer, the metal support layer can be easily peeled, and the metal support layer The support layer becomes reusable.

本発明の製造方法を説明するために、各工程で形成されていく配線回路基板の各部の様子を模式的に示した図である。ハッチングは、領域を区別するために適宜加えている（他の図も、同様である）。It is the figure which showed typically the mode of each part of the printed circuit board formed in each process in order to demonstrate the manufacturing method of this invention. Hatching is appropriately added to distinguish the regions (the same applies to other drawings). 本発明によって形成される配線回路基板の内部構造、導体の接続構造のバリエーションを示す図である。It is a figure which shows the variation of the internal structure of the printed circuit board formed by this invention, and the connection structure of a conductor. 配線回路基板の内部構造の一例をより詳しく示す模式図である。It is a schematic diagram which shows an example of the internal structure of a printed circuit board in more detail. 本発明の実施例の加工手順を示す図である。It is a figure which shows the process sequence of the Example of this invention. 本発明の実施例の加工手順を示す図である。It is a figure which shows the process sequence of the Example of this invention. 本発明の実施例の加工手順を示す図である。It is a figure which shows the process sequence of the Example of this invention. 配線回路基板内の導体層を多層とする場合の構造例を示す図である。It is a figure which shows the structural example in case the conductor layer in a printed circuit board is made into a multilayer.

符号の説明Explanation of symbols

１ 金属製支持体層
２ 配線回路基板
２１ 接続用導体部
２２ 外部接続用導体部
３ 半導体チップ
４ 半導体装置 DESCRIPTION OF SYMBOLS 1 Metal support body layer 2 Wiring circuit board 21 Connection conductor part 22 External connection conductor part 3 Semiconductor chip 4 Semiconductor device

Claims (4)

半導体チップが配線回路基板上に実装された構造を有する半導体装置の製造方法であって、
半導体チップの電極に接続し得る接続用導体部を持った配線回路基板を、金属製支持体層上に、該支持体層から剥離可能となるように、かつ、接続用導体部が該配線回路基板の上面に露出するように形成する工程と、
前記配線回路基板の接続用導体部と半導体チップの電極とを接続して、該配線回路基板に半導体チップを実装する工程と、
前記実装の後、金属製支持体層を配線回路基板から剥離する工程とを、
有することを特微とする、前記半導体装置の製造方法。 A method of manufacturing a semiconductor device having a structure in which a semiconductor chip is mounted on a printed circuit board,
A wiring circuit board having a connecting conductor portion that can be connected to an electrode of a semiconductor chip can be peeled from the support layer on a metal support layer, and the connecting conductor portion is connected to the wiring circuit. Forming to be exposed on the upper surface of the substrate;
Connecting the conductor part for connection of the wired circuit board and the electrode of the semiconductor chip, and mounting the semiconductor chip on the wired circuit board;
After the mounting, the step of peeling the metal support layer from the printed circuit board,
A method for manufacturing the semiconductor device, characterized by comprising: 金属製支持体層と配線回路基板との間に剥離層が形成されており、それによって、金属製支持体層から配線回路基板が剥離可能となっている、請求項１に記載の製造方法。   The manufacturing method according to claim 1, wherein a peeling layer is formed between the metal support layer and the printed circuit board, whereby the printed circuit board can be peeled from the metal support layer. 剥離層がポリイミドからなる層である、請求項２に記載の製造方法。   The manufacturing method of Claim 2 whose peeling layer is a layer which consists of polyimides. 剥離層が、金属、金属酸化物、および、無機酸化物から選ばれる１つの材料からなる層である、請求項２に記載の製造方法。   The manufacturing method of Claim 2 whose peeling layer is a layer which consists of one material chosen from a metal, a metal oxide, and an inorganic oxide.
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