JP2010123684A - 不揮発性半導体記憶装置 - Google Patents
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- JP2010123684A JP2010123684A JP2008294786A JP2008294786A JP2010123684A JP 2010123684 A JP2010123684 A JP 2010123684A JP 2008294786 A JP2008294786 A JP 2008294786A JP 2008294786 A JP2008294786 A JP 2008294786A JP 2010123684 A JP2010123684 A JP 2010123684A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 141
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 34
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000003860 storage Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 70
- 239000002184 metal Substances 0.000 claims description 70
- 150000004767 nitrides Chemical class 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 53
- 229920005591 polysilicon Polymers 0.000 abstract description 53
- 230000006870 function Effects 0.000 abstract description 15
- 230000000903 blocking effect Effects 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 38
- 229910052814 silicon oxide Inorganic materials 0.000 description 38
- 229910052581 Si3N4 Inorganic materials 0.000 description 37
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 37
- 238000004519 manufacturing process Methods 0.000 description 35
- 238000000034 method Methods 0.000 description 20
- 238000005530 etching Methods 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052769 Ytterbium Inorganic materials 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052790 beryllium Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 150000002736 metal compounds Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052702 rhenium Inorganic materials 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- 229910052714 tellurium Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910052727 yttrium Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- -1 Metal Oxide Nitride Chemical class 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
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Abstract
【解決手段】表面に、互いに離間して設けられたソースまたはドレインとなる拡散領域21を有する半導体基板10と、拡散領域21の間の半導体基板10の表面に、順に、トンネル絶縁膜13、電荷蓄積絶縁膜14、及びブロッキング絶縁膜15を有するゲート絶縁膜18が配設され、ゲート絶縁膜18の上に、幅L1を有するシリサイド膜17aが配置されたゲート電極19を備えたメモリセルトランジスタ5と、拡散領域21の間の半導体基板10の表面に、ゲート絶縁膜28が配設され、ゲート絶縁膜28の上に、順に、第1の幅より大きい幅L2を有するポリシリコン膜16a及びシリサイド膜17aが配置されたゲート電極29を備えた選択トランジスタ6とを具備する。
【選択図】図1
Description
(付記1) 表面に、互いに離間して設けられたソースまたはドレインとなる拡散領域を有する半導体基板と、前記拡散領域の間の前記半導体基板の表面に、電荷蓄積絶縁膜を有する第1の絶縁膜が配設され、前記第1の絶縁膜の上に接して、第1の幅を有するシリサイドが配置された第1のゲート電極を備えたメモリセルトランジスタと、前記拡散領域の間の前記半導体基板の表面に、第2の絶縁膜が配設され、前記第2の絶縁膜の上に接して、順に、第1の幅より大きい第2の幅を有する不純物がドープされたシリコン及び前記シリサイドが配置された第2のゲート電極を備えた選択トランジスタとを具備している不揮発性半導体記憶装置。
5、71、73、76 メモリセルトランジスタ
6、72、74、75 選択トランジスタ
7 メモリセル領域
8 選択ゲート領域
10 半導体基板
11 素子領域
13 トンネル絶縁層
13a、13b、15a シリコン酸化膜
14 電荷蓄積絶縁膜
14a シリコン窒化膜
15 ブロッキング絶縁膜
16a、53a ポリシリコン膜
17a シリサイド膜
18、28 ゲート絶縁膜
19、29、61、62、63、64、65、66 ゲート電極
21 拡散領域
31 素子分離領域
33 層間絶縁膜
35a、52a 金属膜
41 トレンチ
51a 金属窒化膜
L1、L2 幅
Claims (5)
- 表面に、互いに離間して設けられたソースまたはドレインとなる拡散領域を有する半導体基板と、
前記拡散領域の間の前記半導体基板の表面に、電荷蓄積絶縁膜を有する第1の絶縁膜が配設され、前記第1の絶縁膜の上に接して、第1の幅を有するシリサイドが配置された第1のゲート電極を備えたメモリセルトランジスタと、
前記拡散領域の間の前記半導体基板の表面に、第2の絶縁膜が配設され、前記第2の絶縁膜の上に接して、順に、第1の幅より大きい第2の幅を有する不純物がドープされたシリコン及び前記シリサイドが配置された第2のゲート電極を備えた選択トランジスタと、
を具備していることを特徴とする不揮発性半導体記憶装置。 - 表面に、互いに離間して設けられたソースまたはドレインとなる拡散領域を有する半導体基板と、
前記拡散領域の間の前記半導体基板の表面に、電荷蓄積絶縁膜を有する第1の絶縁膜が配設され、前記第1の絶縁膜の上に接して、不純物がドープされたシリコン及び金属系導電性材料から選択される材料が配置された第1のゲート電極を備えたメモリセルトランジスタと、
前記拡散領域の間の前記半導体基板の表面に、第2の絶縁膜が配設され、前記第2の絶縁膜の上に接して、前記第1の絶縁膜に接する前記第1のゲート電極の材料とは異なる材料であって、前記不純物がドープされたシリコン及び前記金属系導電性材料から選択される材料が配置された第2のゲート電極を備えた選択トランジスタと、
を具備していることを特徴とする不揮発性半導体記憶装置。 - 前記第1の絶縁膜に接する前記第1のゲート電極は、金属窒化膜であり、前記第2の絶縁膜に接する前記第2のゲート電極は、不純物ドープがドープされたシリコンであることを特徴とする請求項2に記載の不揮発性半導体記憶装置。
- 前記第1の絶縁膜に接する前記第1のゲート電極は、不純物ドープがドープされたシリコンであり、前記第2の絶縁膜に接する前記第2のゲート電極は、金属窒化膜であることを特徴とする請求項2に記載の不揮発性半導体記憶装置。
- 前記第1の絶縁膜に接する前記第1のゲート電極は、金属窒化膜であり、前記第2の絶縁膜に接する前記第2のゲート電極は、金属膜であることを特徴とする請求項2に記載の不揮発性半導体記憶装置。
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JP2008294786A JP5558695B2 (ja) | 2008-11-18 | 2008-11-18 | 不揮発性半導体記憶装置 |
US12/618,119 US8134203B2 (en) | 2008-11-18 | 2009-11-13 | Nonvolatile semiconductor memory device |
US13/364,602 US8575684B2 (en) | 2008-11-18 | 2012-02-02 | Nonvolatile semiconductor memory device |
US13/364,588 US8614477B2 (en) | 2008-11-18 | 2012-02-02 | Nonvolatile semiconductor memory device |
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JP2008294786A JP5558695B2 (ja) | 2008-11-18 | 2008-11-18 | 不揮発性半導体記憶装置 |
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JP2010123684A true JP2010123684A (ja) | 2010-06-03 |
JP2010123684A5 JP2010123684A5 (ja) | 2012-01-12 |
JP5558695B2 JP5558695B2 (ja) | 2014-07-23 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012004403A (ja) * | 2010-06-18 | 2012-01-05 | Fujitsu Semiconductor Ltd | 半導体素子の製造方法、半導体メモリの製造方法、及び半導体素子 |
US8785334B2 (en) | 2011-05-27 | 2014-07-22 | Tokyo Electron Limited | Select transistor, method for making select transistor, memory device, and method for manufacturing memory device |
JP2018037503A (ja) * | 2016-08-31 | 2018-03-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101137929B1 (ko) * | 2010-05-31 | 2012-05-09 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
KR20130004784A (ko) * | 2011-07-04 | 2013-01-14 | 삼성전자주식회사 | 저항 변화 체를 갖는 비-휘발성 메모리 소자 및 그 제조방법 |
WO2015112327A1 (en) * | 2014-01-21 | 2015-07-30 | Applied Materials, Inc. | Dielectric-metal stack for 3d flash memory application |
JP6250506B2 (ja) | 2014-09-16 | 2017-12-20 | 東芝メモリ株式会社 | 集積回路装置及びその製造方法 |
US9793289B2 (en) | 2015-06-08 | 2017-10-17 | Toshiba Memory Corporation | Non-volatile memory device |
KR102653530B1 (ko) * | 2018-12-27 | 2024-04-02 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
KR20200126686A (ko) * | 2019-04-30 | 2020-11-09 | 에스케이하이닉스 주식회사 | 반도체 장치의 제조 방법 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002100686A (ja) * | 2000-09-21 | 2002-04-05 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2003051559A (ja) * | 2001-05-28 | 2003-02-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2005044844A (ja) * | 2003-07-23 | 2005-02-17 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2005243183A (ja) * | 2004-02-27 | 2005-09-08 | Toshiba Corp | データ記憶システム |
JP2007258612A (ja) * | 2006-03-24 | 2007-10-04 | Toshiba Corp | 不揮発性半導体メモリ装置 |
JP2008103666A (ja) * | 2006-04-28 | 2008-05-01 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2008270774A (ja) * | 2007-03-26 | 2008-11-06 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55156371A (en) * | 1979-05-24 | 1980-12-05 | Toshiba Corp | Non-volatile semiconductor memory device |
US5838041A (en) * | 1995-10-02 | 1998-11-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having memory cell transistor provided with offset region acting as a charge carrier injecting region |
JP2000286349A (ja) | 1999-03-31 | 2000-10-13 | Sony Corp | 半導体装置およびその製造方法 |
US6512263B1 (en) * | 2000-09-22 | 2003-01-28 | Sandisk Corporation | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming |
US6897522B2 (en) * | 2001-10-31 | 2005-05-24 | Sandisk Corporation | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements |
US6925007B2 (en) * | 2001-10-31 | 2005-08-02 | Sandisk Corporation | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements |
JP2004039866A (ja) | 2002-07-03 | 2004-02-05 | Toshiba Corp | 半導体装置及びその製造方法 |
US7829938B2 (en) * | 2005-07-14 | 2010-11-09 | Micron Technology, Inc. | High density NAND non-volatile memory device |
TWI260769B (en) * | 2005-08-23 | 2006-08-21 | Ememory Technology Inc | Non-volatile memory and operating method thereof |
JP2008159614A (ja) | 2006-12-20 | 2008-07-10 | Toshiba Corp | 不揮発性半導体メモリ |
US8089114B2 (en) * | 2007-11-08 | 2012-01-03 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including blocking and interface patterns between charge storage patterns and control electrodes and related methods |
-
2008
- 2008-11-18 JP JP2008294786A patent/JP5558695B2/ja active Active
-
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- 2009-11-13 US US12/618,119 patent/US8134203B2/en active Active
-
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- 2012-02-02 US US13/364,602 patent/US8575684B2/en active Active
- 2012-02-02 US US13/364,588 patent/US8614477B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002100686A (ja) * | 2000-09-21 | 2002-04-05 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2003051559A (ja) * | 2001-05-28 | 2003-02-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2005044844A (ja) * | 2003-07-23 | 2005-02-17 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2005243183A (ja) * | 2004-02-27 | 2005-09-08 | Toshiba Corp | データ記憶システム |
JP2007258612A (ja) * | 2006-03-24 | 2007-10-04 | Toshiba Corp | 不揮発性半導体メモリ装置 |
JP2008103666A (ja) * | 2006-04-28 | 2008-05-01 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2008270774A (ja) * | 2007-03-26 | 2008-11-06 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012004403A (ja) * | 2010-06-18 | 2012-01-05 | Fujitsu Semiconductor Ltd | 半導体素子の製造方法、半導体メモリの製造方法、及び半導体素子 |
US8785334B2 (en) | 2011-05-27 | 2014-07-22 | Tokyo Electron Limited | Select transistor, method for making select transistor, memory device, and method for manufacturing memory device |
KR101429706B1 (ko) * | 2011-05-27 | 2014-08-12 | 도쿄엘렉트론가부시키가이샤 | 메모리 장치의 제조 방법 |
JP2018037503A (ja) * | 2016-08-31 | 2018-03-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
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US8614477B2 (en) | 2013-12-24 |
US8134203B2 (en) | 2012-03-13 |
US20120139031A1 (en) | 2012-06-07 |
US20120146128A1 (en) | 2012-06-14 |
JP5558695B2 (ja) | 2014-07-23 |
US8575684B2 (en) | 2013-11-05 |
US20100123184A1 (en) | 2010-05-20 |
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