JP2010115026A - Control circuit of complex power supply device - Google Patents

Control circuit of complex power supply device Download PDF

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JP2010115026A
JP2010115026A JP2008286042A JP2008286042A JP2010115026A JP 2010115026 A JP2010115026 A JP 2010115026A JP 2008286042 A JP2008286042 A JP 2008286042A JP 2008286042 A JP2008286042 A JP 2008286042A JP 2010115026 A JP2010115026 A JP 2010115026A
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storage battery
command value
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capacitor
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JP5381026B2 (en
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Junichi Shimomura
潤一 下村
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13—Energy storage using capacitors

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Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in a complex power supply system wherein an electric double-layer capacitor is connected in parallel to a secondary battery, the life of the secondary battery is shortened depending on an internal impedance ratio due to a load current condition, a change in surrounding environment, etc. <P>SOLUTION: In a complex power supply device, a step-up/down chopper is provided between an electric double-layer capacitor and an inverter. A differential signal between a command value for the voltage of a storage battery and a detected voltage of the storage battery is input into a PI controller, which performs PI calculation, and the step-up/down chopper is controlled via a PWM control unit so that the voltage value of a secondary battery may conform to the command value for the voltage of the storage battery. During this chopper control, a fluctuation of the voltage of the secondary battery can be suppressed by varying the command value for the voltage of the storage battery in charging and discharging. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、二次電池と電気二重層キャパシタで構成された複合電源装置の制御方法に係り、特に二次電池の寿命低下を抑制する制御回路に関するものである。   The present invention relates to a control method for a composite power supply device including a secondary battery and an electric double layer capacitor, and more particularly to a control circuit that suppresses a reduction in the lifetime of the secondary battery.

バッテリーフォークリフトや無人車両、電気自動車などの移動車両には、その電源として鉛蓄電池やリチウム電池などの二次電池が搭載され、駆動用ＡＣモータは、この二次電池を電源としてインバータを介して制御される。駆動装置に搭載される二次電池は、蓄電エネルギー密度は高いが比較的内部抵抗が高いため、ＡＣモータに対して過渡駆動に応じた短時間大電流の充放電を行うと、電圧変動や発熱が生じ、二次電池の寿命が低下する。そのため、二次電池は容量の大きいものを用いる必要がある。   Mobile vehicles such as battery forklifts, unmanned vehicles, and electric vehicles are equipped with secondary batteries such as lead-acid batteries and lithium batteries as their power sources, and the drive AC motor is controlled via an inverter using these secondary batteries as power sources. Is done. The secondary battery installed in the drive device has a high storage energy density but relatively high internal resistance. Therefore, when charging and discharging a large current for a short time according to transient drive to an AC motor, voltage fluctuations and heat generation Occurs, and the life of the secondary battery is reduced. Therefore, it is necessary to use a secondary battery having a large capacity.

この対策として、
図２０で示すように蓄電池Ｂ（二次電池）に対して、内部抵抗の低い電気二重層キャパシタEDLCや電解コンデンサを並列接続した複合電源装置が採用されている。これは、蓄電池Ｂに対して電気二重層キャパシタEDLCは内部抵抗が低いこと、及び蓄電池Ｂは電気二重層キャパシタEDLCに対して蓄電エネルギーが高い特性を利用して、負荷の加速減速時のような過渡状態では必要な電力を電気二重層キャパシタEDLCから供給し、等速時の定常状態では蓄電池Ｂから供給する方式である。これにより、二次電池の電圧変動が抑制されるため、二次電池の長寿命化、容量削減、及び保水等のメンテナンスの軽減が可能となる。なお、図２０でＩＶはインバータ、ＭはＡＣモータである。 As a countermeasure,
As shown in FIG. 20, a composite power supply apparatus in which an electric double layer capacitor EDLC having a low internal resistance and an electrolytic capacitor are connected in parallel to a storage battery B (secondary battery) is employed. This is because the electric double layer capacitor EDLC has a low internal resistance with respect to the storage battery B, and the storage battery B uses the characteristic that the stored energy is higher than that of the electric double layer capacitor EDLC. In the transient state, necessary electric power is supplied from the electric double layer capacitor EDLC, and in the steady state at constant speed, it is supplied from the storage battery B. Thereby, since the voltage fluctuation of the secondary battery is suppressed, it is possible to extend the life of the secondary battery, reduce the capacity, and reduce maintenance such as water retention. In FIG. 20, IV is an inverter, and M is an AC motor.

また、特許文献１の段落０００８〜０００９、及び図３には、キャパシタをＤＣ／ＤＣコンバータを介して蓄電池と並列接続し、インバータへのエネルギー供給は蓄電池から行い、急峻なエネルギー供給や回生はＤＣ／ＤＣコンバータを通してキャパシタから行うことで、インバータの出力電圧を一定に保つことが記載されている。
特開２００３−１４３７１３の特に図３ Further, in paragraphs 0008 to 0009 of FIG. 1 and FIG. 3, a capacitor is connected in parallel with a storage battery via a DC / DC converter, and energy is supplied to the inverter from the storage battery. It is described that the output voltage of the inverter is kept constant by performing from a capacitor through a DC converter.
In particular, FIG. 3 of JP-A-2003-143713.

図２０で示す二次電池に、電気二重層キャパシタや電解コンデンサを直接並列接続する複合電源方式では、回路構成は簡単であるが、次のような問題点を有している。
（１）二次電池とキャパシタの内部インピーダンスにより、複合電源装置の性能が決まる。つまり、二次電池とキャパシタの内部インピーダンスで決まる比率で蓄電池電流とキャパシタ電流が流れる。これにより、蓄電池電流への過渡的な負過電流はキャパシタが分担する分だけ負担軽減されるが、負荷電流条件や内部インピーダンス比率によっては、二次電池の寿命低下が生じる問題がある。
また、内部インピーダンス比率を考慮した場合、複合電源装置を構成する蓄電素子の直並列数や電極面積に制約が生じる。
（２）二次電池と電気二重層キャパシタの経年変化等による劣化、周囲環境の変化によって内部インピーダンスが変化すると、複合電源装置の性能変化となる。
仮に、複合電源装置の設計時に、電流の分流比が最適となる内部インピーダンス比率で構成したとしても、周囲環境変化等で複合電源装置の性能が変化する。 The composite power supply system in which an electric double layer capacitor and an electrolytic capacitor are directly connected in parallel to the secondary battery shown in FIG. 20 has a simple circuit configuration, but has the following problems.
(1) The performance of the composite power supply apparatus is determined by the internal impedance of the secondary battery and the capacitor. That is, the storage battery current and the capacitor current flow at a ratio determined by the internal impedance of the secondary battery and the capacitor. Thereby, the burden of the transient negative overcurrent to the storage battery current is reduced by the share of the capacitor, but there is a problem that the life of the secondary battery is reduced depending on the load current condition and the internal impedance ratio.
Further, when the internal impedance ratio is taken into consideration, there are restrictions on the number of power storage elements constituting the composite power supply apparatus and the electrode area.
(2) When the internal impedance changes due to deterioration of the secondary battery and the electric double layer capacitor due to aging, etc., or changes in the surrounding environment, the performance of the composite power supply device changes.
Even when the composite power supply apparatus is designed with an internal impedance ratio that optimizes the current shunt ratio, the performance of the composite power supply apparatus changes due to changes in the surrounding environment.

なお、特許文献１の図３では、ＤＣ／ＤＣコントローラをどのように制御するかの記載はなく、二次電池の寿命低下を抑制することについての記載はない。   In addition, in FIG. 3 of patent document 1, there is no description of how to control a DC / DC controller, and there is no description about suppressing the lifetime reduction of a secondary battery.

本発明が目的とするとこは、内部インピーダンス比率に関係なく、複合電源装置の寿命低下を抑制する制御方法を提供することにある。   An object of the present invention is to provide a control method that suppresses a reduction in the lifetime of a composite power supply device regardless of the internal impedance ratio.

本発明は、インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
前記蓄電池電圧指令値と検出した蓄電池電圧の差信号をＰＩ制御器に入力してＰＩ演算を実行し、この演算値を電気二重層キャパシタの充放電設定値とし、この充放電設定値に基づいてＰＷＭ制御部を介して昇降圧チョッパを制御することを特徴としたものである。 The present invention provides a power supply for an AC motor controlled via an inverter, in a composite power supply device in which a step-up / step-down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel.
A difference signal between the storage battery voltage command value and the detected storage battery voltage is input to a PI controller to perform a PI calculation. This calculation value is used as a charge / discharge set value for the electric double layer capacitor, and based on the charge / discharge set value. The step-up / step-down chopper is controlled via the PWM control unit.

本発明の請求項２は、充電時蓄電池電圧指令値と放電時蓄電池電圧指令値を各別に設け、
充電時蓄電池電圧指令値と検出した蓄電池電圧の差信号は、蓄電池電圧＞充電時蓄電池電圧指令値のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、放電時蓄電池電圧指令値と検出した蓄電池電圧の差信号は、蓄電池電圧＜放電時蓄電池電圧指令値のときに発生するキャパシタ放電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、各ＰＩ演算値を電気二重層キャパシタの充電設定値と放電設定値とすることを特徴としたものである。 Claim 2 of the present invention separately provides a storage battery voltage command value during charging and a storage battery voltage command value during discharging,
The difference signal between the storage battery voltage command value during charging and the detected storage battery voltage is multiplied by the capacitor charging flag generated by the multiplication unit when the storage battery voltage is greater than the storage battery voltage command value during charging, and then PI calculation is performed by the PI controller. The difference signal between the discharged storage battery voltage command value and the detected storage battery voltage is multiplied by a capacitor discharge flag generated when the storage battery voltage <the discharged storage battery voltage command value and the multiplication unit, and then PI calculation is performed by the PI controller. Each PI calculation value is set as a charge set value and a discharge set value of the electric double layer capacitor.

本発明の請求項３は、インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
充電時チョッパ電流指令値、充電時蓄電池電力指令値、及び放電時蓄電池電力指令値を各別に設け、充電時チョッパ電流指令値とチョッパ電流の差信号は、０＜蓄電池電力＜充電時蓄電池電力指令値のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、
充電時蓄電池電力指令値と蓄電池電力の差信号は、蓄電池電力＜０のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、
放電時蓄電池電力指令値と蓄電池電力の差信号は、蓄電池電力＞放電時蓄電池電力指令値のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、
各ＰＩ演算値を電気二重層キャパシタの充電設定値と放電設定値を算出することを特徴としたものである。 Claim 3 of the present invention is a composite power supply apparatus in which a step-up / step-down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel as a power source of an AC motor controlled via an inverter.
A chopper current command value during charging, a battery power command value during charging, and a battery power command value during discharging are provided separately, and the difference signal between the chopper current command value during charging and the chopper current is 0 <storage battery power <charging battery power command. PI multiplication is performed by the PI controller after multiplying the capacitor charging flag generated at the time of the value by the multiplication unit,
The difference signal between the charging battery power command value and the storage battery power is multiplied by the capacitor charging flag generated when the storage battery power <0 and the multiplication unit, and then PI calculation is performed by the PI controller.
The difference signal between the storage battery power command value at the time of discharge and the storage battery power is multiplied by the capacitor charging flag generated by the multiplication unit when the storage battery power> the storage battery power command value at the time of discharge, and then the PI operation is performed by the PI controller.
Each PI calculation value is calculated as a charge set value and a discharge set value of the electric double layer capacitor.

本発明の請求項４は、インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
充電時蓄電池電流指令値と放電時蓄電池電流指令値を各別に設け、
充電時蓄電池電流指令値と蓄電池電流の差信号は、蓄電池電流＜充電時蓄電池電流指令値のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、
放電時蓄電池電流指令値と蓄電池電流の差信号は、蓄電池電流＞放電時蓄電池電流指令値のときに発生するキャパシタ放電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、各ＰＩ演算値を電気二重層キャパシタの充電設定値と放電設定値とすることを特徴としたものである。 According to a fourth aspect of the present invention, as a power source for an AC motor controlled via an inverter, a composite power supply device in which a step-up / step-down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel,
A battery current command value for charging and a battery current command value for discharging are provided separately,
The difference signal between the storage battery current command value during charging and the storage battery current is multiplied by a capacitor charging flag generated by the multiplier when the storage battery current <the storage battery current command value during charging, and then a PI operation is performed by the PI controller.
The difference signal between the battery current command value during discharge and the battery current is obtained by multiplying the capacitor discharge flag generated when the battery current> the battery current command value during discharge by the multiplier and then performing PI calculation in the PI controller. The calculated values are set as a charge set value and a discharge set value of the electric double layer capacitor.

本発明の請求項５は、前記キャパシタ充電フラグは、負荷電流＜充電時蓄電池電流指令値のときに発生し、前記キャパシタ放電フラグは、負荷電流＞充電時蓄電池電流指令値のときに発生することを特徴としたものである。   According to a fifth aspect of the present invention, the capacitor charge flag is generated when load current <charge battery current command value, and the capacitor discharge flag is generated when load current> charge battery current command value. It is characterized by.

本発明の請求項６は、インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
昇降圧チョッパの充電時チョッパ変調率が一定の変調率に設定された充電時チョッパ変調率設定部と、放電時チョッパ変調率が一定の変調率に設定された放電時チョッパ変調率設定部を設け、検出された負荷電流が充電時蓄電池電流指令値より小のときに充電時チョッパ変調率設定部、及びＰＷＭ制御部を介して昇降圧チョッパの充電制御を実行し、負荷電流が充電時蓄電池電流指令値より大のとき放電時チョッパ変調率設定部、及びＰＷＭ制御部を介して昇降圧チョッパの放電制御を行うこと特徴としたものである。 Claim 6 of the present invention is a composite power supply apparatus in which a step-up / step-down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel as a power source of an AC motor controlled via an inverter.
A chopper modulation rate setting unit for charging and a chopper modulation rate setting unit for discharging and setting a constant chopper modulation rate for discharging and a chopper modulation rate setting for discharging are provided. When the detected load current is smaller than the charging battery current command value, charging control of the step-up / step-down chopper is executed via the charging chopper modulation factor setting unit and the PWM control unit, and the load current is charging battery current When the value is larger than the command value, the discharge control of the step-up / step-down chopper is performed through the chopper modulation factor setting unit during discharge and the PWM control unit.

本発明の請求項７は、インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
前記電気二重層キャパシタの充電電流指令値とキャパシタ電流の差信号を入力してキャパシタ充電電流を演算するＰＩ制御器と、放電電流指令値とキャパシタ電流の差信号を入力してキャパシタ放電電流を演算するＰＩ制御器と、各ＰＩ制御器にて算出されたＰＩ制御信号に基づいて昇降圧チョッパの制御信号を生成するＰＷＭ制御部を設け、直流電流が蓄電池、電気二重層キャパシタ側に流れている
ときに前記電気二重層キャパシタの充電制御を行い、直流電流がＡＣモータ側に流れているときに放電制御を行うよう構成したことを特徴としたものである。 Claim 7 of the present invention is a composite power supply apparatus in which a step-up / step-down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel as a power source of an AC motor controlled via an inverter.
PI controller that calculates the capacitor charge current by inputting the charge current command value of the electric double layer capacitor and the capacitor current, and the capacitor discharge current by inputting the difference signal of the discharge current command value and the capacitor current And a PWM control unit that generates a control signal for the step-up / step-down chopper based on the PI control signal calculated by each PI controller, and direct current flows to the storage battery and the electric double layer capacitor side The charging control of the electric double layer capacitor is sometimes performed, and the discharging control is performed when a direct current is flowing to the AC motor side.

以上のとおり、本発明によれば、昇降圧チョッパによる二次電池電圧制御、電力制御、電流制御やキャパシタ充放電制御を行うことにより蓄電池の電圧変動、電流変動を抑制したものである。これにより、負荷電流条件や二次電池と電気二重層キャパシタによる内部インピーダンス比率に関係なく、二次電池の寿命を延ばすことが可能となる。また、電気二重層キャパシタ、又はＡＣモータ駆動装置に異常発生が生じた場合には、昇降圧チョッパをゲートブロックすることによって両者の分離が可能となり、他方への影響を防ぐことができて、安全、信頼性の向上が可能となる。   As described above, according to the present invention, the secondary battery voltage control, power control, current control and capacitor charge / discharge control by the buck-boost chopper are performed to suppress the voltage fluctuation and current fluctuation of the storage battery. As a result, the life of the secondary battery can be extended regardless of the load current condition and the internal impedance ratio of the secondary battery and the electric double layer capacitor. In addition, when an abnormality occurs in the electric double layer capacitor or AC motor drive device, the buck-boost chopper can be gate-blocked to be separated from each other, and the influence on the other can be prevented. Reliability can be improved.

図１は本発明の主回路構成を示したもので、電気二重層キャパシタEDLCは、昇降圧チョッパＣhを介して蓄電池Ｂに並列接続される。昇降圧チョッパＣhは、降圧（放電）用スイッチング素子Ｓ１と昇圧（充電）用スイッチング素子Ｓ２、及びリアクトルＬを有している。スイッチング素子Ｓ１、Ｓ２は、ここではＩＧＢＴが使用されている。Ｂは二次電池が使用される蓄電池、Ｃは電解コンデンサ、ＩＶはインバータ、ＭはＡＣモータである。
本発明では、昇降圧チョッパＣhを介して蓄電池電圧、蓄電池電流、又は蓄電池電力を制御することで、蓄電池の電圧変動を抑制するものである。以下、実施例に基づいて詳述する。 FIG. 1 shows a main circuit configuration of the present invention. An electric double layer capacitor EDLC is connected in parallel to a storage battery B via a step-up / step-down chopper Ch. The step-up / step-down chopper Ch has a step-down (discharge) switching element S1, a step-up (charge) switching element S2, and a reactor L. Here, IGBTs are used as the switching elements S1 and S2. B is a storage battery in which a secondary battery is used, C is an electrolytic capacitor, IV is an inverter, and M is an AC motor.
In the present invention, the voltage fluctuation of the storage battery is suppressed by controlling the storage battery voltage, the storage battery current, or the storage battery power via the step-up / step-down chopper Ch. Hereinafter, it explains in full detail based on an Example.

図２は、本発明の第１の実施例を示す昇降圧チョッパＣhの制御部構成図で、蓄電池の電圧制御を行うものである。
１は減算部で、設定された電池電圧指令値VbRefと検出された蓄電池電圧Vbが入力されて差演算が実行すされる。２はＰＩ制御部で、減算部１で求められた偏差信号は、このＰＩ制御部２に入力されて比例・積分演算が行われる。
３は除算部で、この除算部３ではＰＩ制御部２から入力された信号を、電気二重層キャパシタEDLCの検出電圧Vcで除することで昇降圧チョッパＣhの設定値ＣhRefとする。４は極性反転部、5及び６はリミッタ部で、昇降圧チョッパの設定値ＣhRefがＣhRef＜０のときには、除算部３での演算信号ＣhRefは極性反転部４において極性反転された後、リミッタ部５を介してＰＷＭ制御部１０に入力される。また、ＣhRef＞０のときにはリミッタ部６を介してＰＷＭ制御部１０に入力される。 FIG. 2 is a block diagram of the controller of the step-up / step-down chopper Ch showing the first embodiment of the present invention, and controls the voltage of the storage battery.
Reference numeral 1 denotes a subtracting unit that inputs the set battery voltage command value VbRef and the detected storage battery voltage Vb, and executes a difference calculation. Reference numeral 2 denotes a PI control unit, and the deviation signal obtained by the subtraction unit 1 is input to the PI control unit 2 for proportional / integral calculation.
Reference numeral 3 denotes a division unit. In the division unit 3, the signal input from the PI control unit 2 is divided by the detection voltage Vc of the electric double layer capacitor EDLC to obtain a set value ChRef of the step-up / down chopper Ch. 4 is a polarity reversing unit, and 5 and 6 are limiter units. When the setting value ChRef of the step-up / step-down chopper is ChRef <0, the operation signal ChRef in the dividing unit 3 is reversed in polarity by the polarity reversing unit 4 and then the limiter unit. 5 to the PWM control unit 10. Further, when ChRef> 0, it is input to the PWM control unit 10 via the limiter unit 6.

ＰＷＭ制御部１０では、各リミッタ部５，６を通して入力された昇降圧チョッパ設定値とキャリア信号に基づいてＰＷＭ信号を生成するが、ＣhRef＞０のときには昇降圧チョッパの降圧用スイッチング素子Ｓ１をオン・オフ制御することで、電気二重層キャパシタEDLCに蓄積されたエネルギーを放電する。また、ＣhRef＜０のときには昇圧用スイッチング素子Ｓ２を制御することで電気二重層キャパシタEDLCへの充電制御を実行する。   The PWM control unit 10 generates a PWM signal based on the step-up / step-down chopper setting value and the carrier signal input through the limiter units 5 and 6, but when ChRef> 0, the step-down switching element S1 of the step-up / down chopper is turned on -Discharge the energy stored in the electric double layer capacitor EDLC by turning it off. Further, when ChRef <0, the charge switching to the electric double layer capacitor EDLC is executed by controlling the step-up switching element S2.

図３はシミュレーション結果を示したものである。同図の上部に示す電圧圧波形図において、線ａは電気二重層キャパシタEDLCを用いないときの蓄電池電圧、
線ｂは電気二重層キャパシタEDLCを設置して本実施例に基づいて蓄電池電圧制御を実施した時の電圧波形図で、負荷電流Iを±３００Ａ変動させた例である。この例によると、線ａで示す電気二重層キャパシタEDLCなしの場合の蓄電池電圧変動は４１．４〜５４．６Ｖ変動し、その差は１３．２Ｖとなっている。
一方、線ｂで示す本実施例によれば、４３．４〜５０．７Ｖでその変動幅は ７．３Ｖとなっている。また、電気二重層キャパシタEDLCなしの場合、蓄電池電流Ibは負荷電流ILと略同等の電流値となるが、蓄電池電圧制御を実施したことで、電気二重層キャパシタEDLCにキャパシタ電流Icが分流され、蓄電池電流の変動幅も抑制される。
蓄電池の電圧・電流の変動抑制幅は、実際の装置においてどの変動幅まで抑制すべきか等の仕様から求められる電気二重層キャパシタEDLCの容量により決まってくることは勿論である。 FIG. 3 shows the simulation results. In the voltage-pressure waveform diagram shown at the top of the figure, line a represents the storage battery voltage when the electric double layer capacitor EDLC is not used,
Line b is a voltage waveform diagram when the electric double layer capacitor EDLC is installed and the storage battery voltage control is performed based on the present embodiment, and is an example in which the load current I is varied by ± 300 A. According to this example, the storage battery voltage fluctuation without the electric double layer capacitor EDLC shown by the line a fluctuates by 41.4 to 54.6V, and the difference is 13.2V.
On the other hand, according to the present embodiment shown by the line b, the fluctuation range is 7.3V at 43.4-50.7V. In addition, in the case without the electric double layer capacitor EDLC, the storage battery current Ib has a current value substantially equal to the load current IL, but by executing the storage battery voltage control, the capacitor current Ic is shunted to the electric double layer capacitor EDLC, The fluctuation range of the storage battery current is also suppressed.
It goes without saying that the voltage / current fluctuation suppression width of the storage battery is determined by the capacity of the electric double layer capacitor EDLC obtained from the specifications such as to what fluctuation range the actual device should be suppressed.

この実施例によれば、ＰＩ制御により蓄電池電圧値Vbを、電池電圧指令値VbRefと一致するように電圧制御したものである。これにより、負荷電流条件や使用環境等による内部インピーダンス比率の変化に関係なく、ＰＩ制御部２は蓄電池電圧を常に一定抑制するよう動作することで、蓄電池の長寿命化が可能となるものである。   According to this embodiment, the storage battery voltage value Vb is voltage-controlled by PI control so as to coincide with the battery voltage command value VbRef. As a result, regardless of the change in the internal impedance ratio due to the load current condition, the usage environment, etc., the PI control unit 2 operates so as to always keep the storage battery voltage constant, thereby extending the life of the storage battery. .

図４は、本発明の第２の実施例を示す昇降圧チョッパＣhの制御部構成図で、蓄電池の電圧制御を行うものである。この実施例で第１の実施例と相違する点は、充電時と放電時との蓄電池電圧指令を変えたことである。通常、充電時の蓄電池電圧指令値VbChgRefは定格蓄電池電圧より高めに設定し、放電時の蓄電池電圧指令値VbDisChgRefは定格蓄電池電圧より低めに設定する。そして、蓄電池電圧の検出値Vbが充電時の蓄電池電圧指令値VbChgRef以上となったときに、蓄電池電圧Vbが充電時の蓄電池電圧指令値VbChgRefに一致するよう電気二重層キャパシタEDLCを充電する。その反対に蓄電池電圧Vbが放電時の蓄電池電圧指令値VbDisChgRef以下となったときに、蓄電池電圧Vbが充電時の蓄電池電圧指令値VbChgRefに一致するよう電気二重層キャパシタEDLCを放電制御する。   FIG. 4 is a block diagram of the controller of the step-up / step-down chopper Ch showing the second embodiment of the present invention, and controls the voltage of the storage battery. This embodiment is different from the first embodiment in that the storage battery voltage command is changed between charging and discharging. Usually, the storage battery voltage command value VbChgRef during charging is set higher than the rated storage battery voltage, and the storage battery voltage command value VbDisChgRef during discharging is set lower than the rated storage battery voltage. When the detected value Vb of the storage battery voltage becomes equal to or higher than the storage battery voltage command value VbChgRef during charging, the electric double layer capacitor EDLC is charged so that the storage battery voltage Vb matches the storage battery voltage command value VbChgRef during charging. Conversely, when the storage battery voltage Vb becomes equal to or lower than the storage battery voltage command value VbDisChgRef at the time of discharging, the electric double layer capacitor EDLC is controlled to discharge so that the storage battery voltage Vb matches the storage battery voltage command value VbChgRef at the time of charging.

すなわち、図４において、充電時の蓄電池電圧指令値VbChgRefは、減算部１１に入力されて蓄電池電圧Vbとの差信号が求められ、放電時の蓄電池電圧指令値VbDisChgRefは、減算部２１に入力されて蓄電池電圧Vbとの差信号が求められる。１６、２６は乗算部で、減算部１１、２１で求められた各差信号とキャパシタ充電フラグ、及び放電フラグとの乗算がそれぞれ実行される。   That is, in FIG. 4, the storage battery voltage command value VbChgRef during charging is input to the subtraction unit 11 to obtain a difference signal from the storage battery voltage Vb, and the storage battery voltage command value VbDisChgRef during discharging is input to the subtraction unit 21. Thus, a difference signal from the storage battery voltage Vb is obtained. Reference numerals 16 and 26 denote multiplication units, which respectively multiply the difference signals obtained by the subtraction units 11 and 21, the capacitor charge flag, and the discharge flag.

キャパシタフラグは、図５で示すフラグ発生手段により生成される。８は充電フラグ発生部、９は放電フラグ発生部で、検出された蓄電池電圧Vbと充電時の蓄電池電圧指令値VbChgRefの大小関係が、Vb＞VbChgRefのときには充電フラグ発生部８でキャパシタ充電フラグ１を立てる。また、蓄電池電圧Vbと放電時の蓄電池電圧指令値VbDisChgRefの大小関係が、Vb＜VbDisChgRefのときには放電フラグ発生部９でキャパシタ充電フラグ１を立てる。   The capacitor flag is generated by flag generation means shown in FIG. 8 is a charge flag generation unit, and 9 is a discharge flag generation unit. When the magnitude relationship between the detected storage battery voltage Vb and the storage battery voltage command value VbChgRef during charging is Vb> VbChgRef, the charge flag generation unit 8 uses the capacitor charge flag 1. Stand up. Further, when the magnitude relation between the storage battery voltage Vb and the storage battery voltage command value VbDisChgRef at the time of discharge is Vb <VbDisChgRef, the discharge flag generator 9 sets the capacitor charge flag 1.

キャパシタフラグ１が立てられた側のＰＩ制御部１２、又は２２では、減算部１１、又は２１で求められた偏差信号は、ＰＩ制御部１２、又は２２に入力されて比例・積分演算が行われ、その演算値は除算部１３、又は２３において検出されたキャパシタ電圧Cvにより除されて昇降圧チョッパの設定値となる。この設定値は、除算部１３の出力のみ極性反転部１４において極性反転された後、リミッタ部１５を介してＰＷＭ制御部１０に入力され、また、除算部２３の出力は、リミッタ部２５を介してＰＷＭ制御部１０に入力される。   In the PI control unit 12 or 22 on the side where the capacitor flag 1 is set, the deviation signal obtained by the subtraction unit 11 or 21 is input to the PI control unit 12 or 22, and proportional / integral calculation is performed. The calculated value is divided by the capacitor voltage Cv detected by the dividing unit 13 or 23 to become a set value of the step-up / down chopper. Only the output of the dividing unit 13 is inverted in polarity by the polarity inverting unit 14 and then input to the PWM control unit 10 through the limiter unit 15, and the output of the dividing unit 23 is input through the limiter unit 25. Are input to the PWM controller 10.

ＰＷＭ制御部１０では、第１の実施例と同様に、各リミッタ部１５，２６を通して入力された昇降圧チョッパ設定値とキャリア信号に基づいてＰＷＭ信号を生成し、キャパシタフラグが充電フラグ発生部９に立てられたときには、昇降圧チョッパの降圧用スイッチング素子Ｓ１をオン・オフ制御することで、電気二重層キャパシタEDLCに蓄積されたエネルギーを放電する。
また、キャパシタフラグが充電フラグ発生部８に立てられたときには、昇圧用スイッチング素子Ｓ２を制御することで電気二重層キャパシタEDLCへの充電制御を実行する。 As in the first embodiment, the PWM control unit 10 generates a PWM signal based on the step-up / step-down chopper setting value and the carrier signal input through the limiter units 15 and 26, and the capacitor flag becomes the charge flag generation unit 9 Is set to ON / OFF, the energy stored in the electric double layer capacitor EDLC is discharged by controlling on / off of the step-down switching element S1 of the step-up / step-down chopper.
Further, when the capacitor flag is set in the charge flag generation unit 8, the electric double layer capacitor EDLC is charged by controlling the step-up switching element S2.

図６は第２実施例におけるシミュレーション結果を示したものである。
線ａで示す電気二重層キャパシタEDLCなしの場合の蓄電池電圧変動は４１．４〜５４．６Ｖ変動し、その差は１３．２Ｖとなっている。一方、線ｂで示す本実施例によれば、４５．７〜５０．２Ｖでその変動幅は４．５Ｖとなって、線ａよりも蓄電池電圧の変動が抑制されていることが判る。
また、キャパシタ電流Icが大幅に電流分担することで、蓄電池電流Ibの電流変動幅も大幅に抑制されていることが判る。 FIG. 6 shows a simulation result in the second embodiment.
The battery voltage fluctuation in the case without the electric double layer capacitor EDLC indicated by the line a fluctuates by 41.4 to 54.6V, and the difference is 13.2V. On the other hand, according to the present embodiment indicated by the line b, the fluctuation range is 4.5 V at 45.7 to 50.2 V, and it can be seen that the fluctuation of the storage battery voltage is suppressed more than the line a.
In addition, it can be seen that the current fluctuation width of the storage battery current Ib is greatly suppressed because the capacitor current Ic is largely shared.

この実施例によれば、充電と放電を各別の設定値とし、この充放電の制御判断は蓄電池電圧で行なうことで、常に、蓄電池電圧が一定となる。   According to this embodiment, charging and discharging are set to different set values, and the charging / discharging control determination is performed by the storage battery voltage, so that the storage battery voltage is always constant.

図７は第３の実施例を示す昇降圧チョッパＣhの構成図で、蓄電池の電力制御を行うものである。この実施例で第２実施例と相違する点は、蓄電池電力を制御することである。蓄電池電力Wbは、蓄電池電圧Vbと蓄電池電流Ibの乗算によって求められる。この電力値が負の値、つまりＡＣモータが回生時の場合には、昇降圧チョッパＣhを流れるチョッパ電流Ｉcが、充電時チョッパ電流指令値IcChgRefに一致するよう電気二重層キャパシタEDLCを充電する。また、充電時の蓄電池電力指令値WbChgRef以下のときには、蓄電池電力Wbの値が充電時の蓄電池電力指令値WbChgRefに一致するよう電気二重層キャパシタEDLCを充電し、放電時の蓄電池電力指令値WbDisChgRef以上のときには、蓄電池電圧Vbの値が放電時蓄電池電力指令値WbDisChgRefに一致するよう電気二重層キャパシタEDLCの放電制御を実行する。   FIG. 7 is a block diagram of a step-up / step-down chopper Ch showing a third embodiment, and performs power control of the storage battery. This embodiment is different from the second embodiment in that the storage battery power is controlled. The storage battery power Wb is obtained by multiplying the storage battery voltage Vb and the storage battery current Ib. When the power value is negative, that is, when the AC motor is in regeneration, the electric double layer capacitor EDLC is charged so that the chopper current Ic flowing through the step-up / step-down chopper Ch matches the charging chopper current command value IcChgRef. In addition, when the battery power command value WbChgRef at the time of charging is less than or equal to, the electric double layer capacitor EDLC is charged so that the value of the battery power Wb matches the battery power command value WbChgRef at the time of charging, and the battery power command value WbDisChgRef or more at the time of discharging In this case, the discharge control of the electric double layer capacitor EDLC is executed so that the value of the storage battery voltage Vb matches the discharged storage battery power command value WbDisChgRef.

すなわち、図７において、充電時チョッパ電流指令値IcChgRefは、減算部３１に入力されてチョッパ電流Ｉcとの差信号が求められる。充電時蓄電池電力指令値WbChgRefは、減算部４１に入力されて蓄電池電力Wbとの差信号が求められ、放電時蓄電池電力指令値WbDisChgRefは、減算部５１に入力されて蓄電池電力Wbとの差信号が求められる。求められた各差信号は、乗算部３６，４６、及び５６に入力されて各別のキャパシタ充電フラグF1,F2及び放電フラグF3との乗算がそれぞれ実行される。   That is, in FIG. 7, the charging chopper current command value IcChgRef is input to the subtractor 31 to obtain a difference signal from the chopper current Ic. The charging battery power command value WbChgRef is input to the subtraction unit 41 to obtain a difference signal from the storage battery power Wb, and the discharging storage battery power command value WbDisChgRef is input to the subtraction unit 51 and the difference signal from the storage battery power Wb. Is required. The obtained difference signals are input to the multipliers 36, 46, and 56, and multiplications with the different capacitor charge flags F1, F2 and the discharge flag F3 are respectively performed.

フラグF1〜F3は、図８で示すフラグ発生手段により生成される。すなわち、乗算部３７とフラグ発生部３９、４９、及び５９により構成される。乗算部３７は、蓄電池電圧Vbと蓄電池電流Ibを乗算して蓄電池電力Wbを求めて各フラグ発生部に出力する。フラグ発生部３９は、入力された蓄電池電力Wbと充電時の蓄電池電力指令値WbChgRefとの大小関係が、０＜Wb＜WbChgRefのときにキャパシタ充電フラグF1を１に立てる。フラグ発生部４９は、入力された蓄電池電力Wbが、Wb＜０のときにキャパシタ充電フラグF2を１に立てる。また、フラグ発生部５９は、蓄電池電力Wbと放電時の蓄電池電力指令値WbDisChgRefとの間に、Wb＞WbDisChgRefとなったときにキャパシタ放電フラグF3を１に立てる。   The flags F1 to F3 are generated by flag generation means shown in FIG. That is, it comprises a multiplication unit 37 and flag generation units 39, 49, and 59. Multiplier 37 multiplies storage battery voltage Vb and storage battery current Ib to determine storage battery power Wb, and outputs it to each flag generator. The flag generation unit 39 sets the capacitor charge flag F1 to 1 when the magnitude relationship between the input storage battery power Wb and the storage battery power command value WbChgRef at the time of charging is 0 <Wb <WbChgRef. The flag generator 49 sets the capacitor charge flag F2 to 1 when the input storage battery power Wb is Wb <0. Further, the flag generating unit 59 sets the capacitor discharge flag F3 to 1 when Wb> WbDisChgRef between the storage battery power Wb and the storage battery power command value WbDisChgRef during discharge.

ＰＩ制御部３２は、フラグ発生部３９により充電フラグF1が立てられると、減算部３１で算出された差信号に基づいて比例・積分演算を実行し、その演算値は除算部３３においてキャパシタ電圧Cvにより除されて電気二重層キャパシタEDLCを充電するための昇降圧チョッパの電流制御指令となる。この電流制御指令は、極性反転部３４、リミッタ部３５、及び加算部４８を介してＰＷＭ制御部１０に入力されてＰＷＭ処理が実行されて昇圧用スイッチング素子Ｓ２のゲート信号になる。   When the charging flag F1 is set by the flag generation unit 39, the PI control unit 32 executes a proportional / integral calculation based on the difference signal calculated by the subtraction unit 31, and the calculated value is obtained by the division unit 33 at the capacitor voltage Cv. Is a current control command of the step-up / step-down chopper for charging the electric double layer capacitor EDLC. This current control command is input to the PWM control unit 10 via the polarity inversion unit 34, the limiter unit 35, and the addition unit 48, and PWM processing is executed to become a gate signal for the boosting switching element S2.

ＰＩ制御部４２は、フラグ発生部４９により充電フラグF2が立てられると、減算部４１で算出された差信号に基づいて比例・積分演算を実行し、その演算値は除算部４３においてキャパシタ電圧Cvにより除され、昇降圧チョッパの充電制御指令となる。したがって、この充電制御指令は、リミッタ部４５、及び加算部４８を介してＰＷＭ制御部１０に入力され、ＰＷＭ処理が実行されて昇圧用スイッチング素子Ｓ２のゲート信号になり、この信号による制御によって蓄電池電力制御が行われる。   When the flag generation unit 49 sets the charge flag F2, the PI control unit 42 executes a proportional / integral calculation based on the difference signal calculated by the subtraction unit 41, and the calculated value is obtained by the division unit 43 at the capacitor voltage Cv. The charge control command for the step-up / step-down chopper is obtained. Therefore, the charge control command is input to the PWM control unit 10 via the limiter unit 45 and the addition unit 48, and PWM processing is executed to become a gate signal of the boost switching element S2, and the storage battery is controlled by this signal. Power control is performed.

ＰＩ制御部５２は、フラグ発生部５９により充電フラグF3が立てられると、減算部５１で算出された差信号に基づいて比例・積分演算を実行し、その演算値は除算部４３においてキャパシタ電圧Cvにより除され、昇降圧チョッパによる放電制御指令となる。したがって、この放電制御指令は、極性反転部５４、リミッタ部５５を介してＰＷＭ制御部１０に入力され、ＰＷＭ処理が実行されて降圧用スイッチング素子Ｓ１のゲート信号になり、この信号による制御によって蓄電池の電力制御が実行される。   When the charging flag F3 is set by the flag generating unit 59, the PI control unit 52 executes a proportional / integral calculation based on the difference signal calculated by the subtracting unit 51, and the calculated value is calculated by the dividing unit 43 at the capacitor voltage Cv. And becomes a discharge control command by the step-up / down chopper. Therefore, this discharge control command is input to the PWM control unit 10 via the polarity inverting unit 54 and the limiter unit 55, and the PWM process is executed to become the gate signal of the step-down switching element S1, and the storage battery is controlled by this signal. The power control is executed.

図９は第３実施例におけるシミュレーション結果を示したものである。
線ａで示す電気二重層キャパシタEDLCなしの場合の蓄電池電圧変動は４１．４〜５４．６Ｖ変動し、変動幅１３．２Ｖとなっているところ、線ｂで示す本実施例によれば、４３．９〜５１．２Ｖでその変動幅は７．３Ｖとなって、線ａよりも蓄電池電圧の変動が抑制されていることが判る。
また、キャパシタ電流Icが大幅に電流分担することで、蓄電池電流Ibの電流変動幅も抑制されていることが判る。 FIG. 9 shows a simulation result in the third embodiment.
The battery voltage fluctuation without the electric double layer capacitor EDLC indicated by the line a varies from 41.4 to 54.6 V, and the fluctuation range is 13.2 V. According to the present embodiment indicated by the line b, 43 The fluctuation range is 7.3 V at .9 to 51.2 V, and it can be seen that the fluctuation of the storage battery voltage is suppressed more than the line a.
Further, it can be seen that the current fluctuation width of the storage battery current Ib is also suppressed by the capacitor current Ic sharing a large amount of current.

この実施例によれば、蓄電池に対する充放電電力を一定に制御すると共に、昇降圧チョッパの充電電流を一定に制御することで、蓄電池の電力変動の抑制が可能となる。   According to this embodiment, the charging / discharging power of the storage battery is controlled to be constant, and the charging current of the step-up / step-down chopper is controlled to be constant, thereby suppressing the power fluctuation of the storage battery.

図１０は第４の実施例を示す昇降圧チョッパＣhの制御部構成図で、蓄電池の電流制御を行うものである。この実施例で第２実施例と相違する点は、蓄電池電流の値を蓄電池電流指令値と一致するよう制御することである。通常、充電時の蓄電池電流指令値IbChgRefは、放電時の蓄電池電流指令値IbDisChgRefより低く設定される。そして、蓄電池電流Ibが放電時の蓄電池電流指令値IbDisChgRef以上になったとき、蓄電池電流Ibが放電時の蓄電池電流指令値IbDisChgRefに一致するよう電気二重層キャパシタEDLCの蓄積エネルギーを放出する。また、蓄電池電流Ibが充電時の蓄電池電流指令値IbChgRef以下になったとき、蓄電池電流Ibが充電時の蓄電池電流指令値IbChgRefに一致するよう電気二重層キャパシタEDLCを充電する。   FIG. 10 is a block diagram of the control unit of the step-up / step-down chopper Ch showing the fourth embodiment, which controls the current of the storage battery. This embodiment is different from the second embodiment in that the value of the storage battery current is controlled to coincide with the storage battery current command value. Usually, the storage battery current command value IbChgRef during charging is set lower than the storage battery current command value IbDisChgRef during discharging. When the storage battery current Ib becomes equal to or greater than the storage battery current command value IbDisChgRef at the time of discharge, the stored energy of the electric double layer capacitor EDLC is released so that the storage battery current Ib matches the storage battery current command value IbDisChgRef at the time of discharge. Further, when the storage battery current Ib becomes equal to or less than the storage battery current command value IbChgRef during charging, the electric double layer capacitor EDLC is charged so that the storage battery current Ib matches the storage battery current command value IbChgRef during charging.

図１０において、充電時の蓄電池電流指令値IbChgRefは、減算部６１に入力されて蓄電池電流Ibとの差信号が求められ、放電時の蓄電池電流指令値IbDisChgRefは、減算部7１に入力されて蓄電池電流Ibとの差信号が求められる。6６、７６は乗算部で、減算部６１、７１で求められた各差信号とキャパシタ充電フラグ及び放電フラグとの乗算がそれぞれ実行される。   In FIG. 10, the storage battery current command value IbChgRef at the time of charging is input to the subtraction unit 61 to obtain a difference signal from the storage battery current Ib, and the storage battery current command value IbDisChgRef at the time of discharging is input to the subtraction unit 71. A difference signal from the current Ib is obtained. Reference numerals 66 and 76 denote multiplication units, which respectively multiply the difference signals obtained by the subtraction units 61 and 71 by the capacitor charge flag and the discharge flag.

キャパシタフラグは、図１１で示すフラグ発生手段により生成される。６８は充電フラグ発生部、７８は放電フラグ発生部で、検出された蓄電池電流Ibと充電時の蓄電池電流指令値IbChgRefの大小関係が、Ib＜IbChgRefのときに充電フラグ発生部６８でキャパシタ充電フラグ１を立てる。また、蓄電池電流Ibと放電時の蓄電池電流指令値IbDisChgRefの大小関係が、Ib＞IbDisChgRefのときには放電フラグ発生部７８でキャパシタ放電フラグ１を立てる。   The capacitor flag is generated by the flag generating means shown in FIG. 68 is a charge flag generation unit, and 78 is a discharge flag generation unit. When the magnitude relationship between the detected storage battery current Ib and the storage battery current command value IbChgRef at the time of charge is Ib <IbChgRef, the charge flag generation unit 68 uses the capacitor charge flag. Set 1 Further, when the magnitude relationship between the storage battery current Ib and the storage battery current command value IbDisChgRef at the time of discharge is Ib> IbDisChgRef, the discharge flag generator 78 sets the capacitor discharge flag 1.

キャパシタフラグ１の立てられた側のＰＩ制御部６２、又は７２では、減算部
６１、又は７１で求められた偏差信号は、ＰＩ制御部６２、又は７２に入力されて比例・積分演算が行われ、その演算値は除算部６３、又は７３において検出されたキャパシタ電圧Cvにより除されて昇降圧チョッパの設定値となる。この設定値は、除算部７３の出力のみ極性反転部７４において極性反転された後、リミッタ部７５を介してＰＷＭ制御部１０に入力され、また、除算部６３の出力は、リミッタ部６５を介してＰＷＭ制御部１０に入力される。 In the PI control unit 62 or 72 on the side where the capacitor flag 1 is set, the deviation signal obtained by the subtraction unit 61 or 71 is input to the PI control unit 62 or 72 and proportional / integral calculation is performed. The calculated value is divided by the capacitor voltage Cv detected by the division unit 63 or 73 to become the set value of the step-up / down chopper. Only the output of the division unit 73 is inverted in polarity by the polarity inversion unit 74 and then input to the PWM control unit 10 via the limiter unit 75, and the output of the division unit 63 is input through the limiter unit 65. Are input to the PWM controller 10.

ＰＷＭ制御部１０では、第２の実施例と同様に、各リミッタ部６５，７５を通して入力された昇降圧チョッパ設定値とキャリア信号に基づいてＰＷＭ信号を生成し、キャパシタフラグが放電フラグ発生部７８に立てられたときには、昇降圧チョッパの降圧用スイッチング素子Ｓ１をオン・オフ制御することで、電気二重層キャパシタEDLCに蓄積されたエネルギーを放電する。
また、キャパシタフラグが充電フラグ発生部６８に立てられたときには、昇圧用スイッチング素子Ｓ２を制御することで電気二重層キャパシタEDLCへの充電制御を実行する。 As in the second embodiment, the PWM controller 10 generates a PWM signal based on the step-up / step-down chopper set value and the carrier signal input through the limiters 65 and 75, and the capacitor flag becomes the discharge flag generator 78. Is set to ON / OFF, the energy stored in the electric double layer capacitor EDLC is discharged by controlling on / off of the step-down switching element S1 of the step-up / step-down chopper.
When the capacitor flag is set in the charge flag generator 68, the electric double layer capacitor EDLC is charged by controlling the step-up switching element S2.

図１２は実施例４にけるシミュレーション結果を示したものである。
線ａで示す電気二重層キャパシタEDLCなしの場合の蓄電池電圧変動は４１．４〜５４．６Ｖ変動し、その差は１３．２Ｖとなっている。一方、線ｂで示す本実施例によれば、４４．２〜４８．０Ｖでその変動幅は３．８Ｖとなって、線ａよりも蓄電池電圧の変動が抑制されていることが判る。
また、キャパシタ電流Icが電流分担することで、キャパシタ電流Icは変動するが、蓄電池電流Ibの電流変動幅は大幅に抑制されていることが判る。 FIG. 12 shows a simulation result in the fourth embodiment.
The battery voltage fluctuation in the case without the electric double layer capacitor EDLC indicated by the line a fluctuates by 41.4 to 54.6V, and the difference is 13.2V. On the other hand, according to the present embodiment shown by the line b, the fluctuation range is 3.8 V at 44.2 to 48.0 V, and it can be seen that the fluctuation of the storage battery voltage is suppressed more than the line a.
Further, it can be seen that the capacitor current Ic varies due to the current sharing of the capacitor current Ic, but the current fluctuation width of the storage battery current Ib is greatly suppressed.

この実施例によれば、充電時、及び放電時の蓄電池電流を一定にするよう制御し、その充放電制御の判断を蓄電池電流で行うようにしたものである。これにより、蓄電池電圧の変動幅の抑制が可能となる。   According to this embodiment, the storage battery current during charging and discharging is controlled to be constant, and the determination of the charge / discharge control is performed based on the storage battery current. As a result, the fluctuation range of the storage battery voltage can be suppressed.

この実施例で実施例４と相違する点は、昇降圧チョッパＣhの制御部構成図を図１０と同じ構成とし、キャパシタフラグ発生手段のみが図１３で示すように、フラグ発生の判断基準を、主回路を流れる負荷電流ILと充放電時蓄電池電流指令値で行うようにしたものである。すなわち、充電フラグ発生部６８ａでは、
IL＜IbChgRefのときにキャパシタ充電フラグを発生し、放電フラグ発生部７８ａでは、IL＞IbDisChgRefのときにキャパシタ放電フラグを発生する。他は図１１と同様である。 This embodiment is different from the fourth embodiment in that the controller block diagram of the step-up / step-down chopper Ch is the same as that in FIG. 10 and only the capacitor flag generating means shows the determination criterion for flag generation as shown in FIG. This is performed with the load current IL flowing through the main circuit and the storage battery current command value during charge / discharge. That is, in the charge flag generator 68a,
A capacitor charge flag is generated when IL <IbChgRef, and the discharge flag generator 78a generates a capacitor discharge flag when IL> IbDisChgRef. Others are the same as FIG.

図１４は実施例５にけるシミュレーション結果を示したもので、蓄電池の電圧・電流の変動幅は実施例４と略同様である。   FIG. 14 shows a simulation result in Example 5, and the fluctuation range of the voltage / current of the storage battery is substantially the same as that in Example 4.

この実施例によれば、充電時、及び放電時の蓄電池電流を一定にするよう制御し、その充放電制御の判断を負荷電流で行うようにしたものである。これにより、蓄電池に対する電圧、電流の変動幅抑制が可能となる。   According to this embodiment, the storage battery current during charging and discharging is controlled to be constant, and the determination of the charge / discharge control is performed with the load current. Thereby, the fluctuation range of the voltage and current with respect to the storage battery can be suppressed.

図１５は第６の実施例を示したもので、実施例５との相違点は、昇降圧チョッパＣhの制御部ゲート信号のオン・オフ制御を一定の変調率で充放電制御するものである。そのために、この実施例は充電時チョッパ変調率設定部８０と放電時チョッパ変調率設定部９０を備えている。図１３で示す充電フラグ発生部６８ａにおいて、負荷電流ILと充電時蓄電池電流指令値IbChgRefとの間で、IL＜IbChgRefとなったきにキャパシタ充電フラグを発生し、その信号を充電時チョッパ変調率設定部８０へ出力する。充電時チョッパ変調率設定部８０では、充電フラグ発生を受けて予め設定された一定の変調率となる信号を発生し、ＰＷＭ制御部１０にてゲート信号を生成して昇圧用スイッチング素子Ｓ１のゲート信号とする。   FIG. 15 shows the sixth embodiment. The difference from the fifth embodiment is that charge / discharge control is performed at a constant modulation rate on / off control of the control unit gate signal of the buck-boost chopper Ch. . For this purpose, this embodiment includes a charging chopper modulation factor setting unit 80 and a discharging chopper modulation factor setting unit 90. In the charge flag generating unit 68a shown in FIG. 13, a capacitor charge flag is generated between IL and IbChgRef between the load current IL and the chargeable battery current command value IbChgRef, and the signal is set as the charge chopper modulation factor. To the unit 80. The charging chopper modulation factor setting unit 80 generates a signal having a predetermined constant modulation factor in response to the generation of the charge flag, and the PWM control unit 10 generates a gate signal to generate the gate of the boost switching element S1. Signal.

一方、放電フラグ発生部７８ａでは、IL＞IbDisChgRefを検出してキャパシタ放電フラグを発生し、その信号を放電時チョッパ変調率設定部９０へ出力する。放電時チョッパ変調率設定部８０では、放電フラグ発生を受けて予め設定された一定の変調率となる放電用の信号を発生し、ＰＷＭ制御部１０にてゲート信号を生成して降圧用スイッチング素子Ｓ２のゲート信号とする。   On the other hand, discharge flag generation unit 78a detects IL> IbDisChgRef, generates a capacitor discharge flag, and outputs the signal to discharge chopper modulation factor setting unit 90. The discharge chopper modulation factor setting unit 80 generates a discharge signal having a predetermined constant modulation factor in response to the generation of the discharge flag, and the PWM control unit 10 generates a gate signal to generate a step-down switching element. The gate signal of S2.

図１６は実施例６にけるシミュレーション結果を示したものである。
線ａで示す電気二重層キャパシタEDLCなしの場合の蓄電池電圧変動は４１．４〜５４．６Ｖ変動し、その差は１３．２Ｖとなっている。一方、線ｂで示す本実施例によれば、４２．５〜５０．５Ｖでその変動幅は８Ｖとなって、線ａよりも蓄電池電圧の変動が抑制されていることが判る。
また、キャパシタ電流Icが電流分担することで、蓄電池電流Ibの電流変動幅も抑制されていることが判る。 FIG. 16 shows a simulation result in the sixth embodiment.
The battery voltage fluctuation in the case without the electric double layer capacitor EDLC indicated by the line a fluctuates by 41.4 to 54.6V, and the difference is 13.2V. On the other hand, according to the present embodiment indicated by the line b, the fluctuation range is 8 V at 42.5 to 50.5 V, and it can be seen that the fluctuation of the storage battery voltage is suppressed more than the line a.
Further, it can be seen that the current fluctuation width of the storage battery current Ib is suppressed by the capacitor current Ic sharing the current.

この実施例によれば、昇降圧チョッパＣhのオン・オフ制御を一定の変調率で充放電制御するものである。これにより、蓄電池電圧の電圧・電流の変動幅抑制が可能となる。   According to this embodiment, on / off control of the step-up / step-down chopper Ch is performed with charge / discharge control at a constant modulation rate. Thereby, it is possible to suppress the fluctuation range of the voltage / current of the storage battery voltage.

図１７は第６の実施例を示す制御フローで、この実施例は、ステップＳt１で負荷電流ILの大きさを見て、その値がIL＜０のときにはステップＳt２で電気二重層キャパシタEDLCに対する充電制御を行い、ステップＳt１でIL＞０のときにステップＳt３で放電制御を行うものである。そのための制御回路は図１８のように構成される。   FIG. 17 is a control flow showing the sixth embodiment. In this embodiment, the magnitude of the load current IL is observed at step St1, and when the value IL <0, the charging to the electric double layer capacitor EDLC is performed at step St2. Control is performed, and when IL> 0 in step St1, discharge control is performed in step St3. The control circuit for this is configured as shown in FIG.

図１８で、負荷電流IL＜０で負荷電流が負のとき、すなわち、回生状態となったときに充電電流指令値（＝負荷電流IL）は減算部１１ａに入力され、昇降圧チョッパを介して流れるキャパシタ電流Icとの差信号が算出される。偏差信号はＰＩ制御部１２ａに入力されて比例・積分演算が行われた後、リミッタ１５ａを介しＰＷＭ制御部１０に入力されて電気二重層キャパシタEDLCに対する充電制御信号が生成される。つまり、回生電流をこの信号により昇圧用スイッチング素子Ｓ１による電流制御で電気二重層キャパシタEDLCを充電する。
一方、負荷電流IL＞０で負荷電流
正のとき、すなわち、力行時には放電電流指令値が減算部２１ａに入力されてキャパシタ電流Icとの差信号が算出される。偏差信号はＰＩ制御部２２ａに入力されて比例・積分演算が行われた後、リミッタ２６ａを介しＰＷＭ制御部１０に入力されて電気二重層キャパシタEDLCに対する放電制御信号を生成し、この信号で降圧用スイッチング素子Ｓ２を制御することでキャパシタから一定電流を放電する。 In FIG. 18, when the load current IL <0 and the load current is negative, that is, when the regenerative state is entered, the charging current command value (= load current IL) is input to the subtractor 11a and is passed through the step-up / down chopper. A difference signal from the flowing capacitor current Ic is calculated. The deviation signal is input to the PI control unit 12a and subjected to proportional / integral calculation, and then input to the PWM control unit 10 via the limiter 15a to generate a charge control signal for the electric double layer capacitor EDLC. That is, the electric double layer capacitor EDLC is charged by the regenerative current by this signal by the current control by the boost switching element S1.
On the other hand, when the load current IL> 0 and the load current is positive, that is, during power running, the discharge current command value is input to the subtractor 21a, and a difference signal from the capacitor current Ic is calculated. After the deviation signal is input to the PI control unit 22a and proportional / integral calculation is performed, the deviation signal is input to the PWM control unit 10 via the limiter 26a to generate a discharge control signal for the electric double layer capacitor EDLC. A constant current is discharged from the capacitor by controlling the switching element S2.

図１９は、実施例７によるシミュレーション結果である。
この実施例では、回生エネルギーを全て電気二重層キャパシタEDLCに蓄え、力行時には蓄えたエネルギーを放出するものであるが、このことは、回生電流発生時である時刻ｔ１〜ｔ２では蓄電池電流Ibは流れず、回生電流は全てキャパシタ電流Icとなり、その結果、電気二重層キャパシタEDLCの充電電圧が徐々に上昇している。
したがって、この実施例によれば、キャパシタ電流を負荷電流（＝充電電流指令値）に一致させるよう制御しているので、キャパシタ電流による充放電制御が優先された制御となっている。電気二重層キャパシタが満充電となった場合や、放電限界電圧となったときには、昇降圧チョッパを停止するか、若しくはチョッパ指令値を０にし、その後に蓄電池の充放電制御が行われる。このため、各実施例と同様に蓄電池の電圧・電流変動が抑制されるが、特に蓄電池の充放電制御が少なくなり、蓄電池の放電エネルギーの軽減化（蓄電池負担の軽減）が可能となることによって、より蓄電池の長寿命化が可能となるものである。
なお、電圧値、電流値、及び負荷変動パターンは、図１９で示すパターンでなくともよいことは勿論である。 FIG. 19 shows a simulation result according to the seventh embodiment.
In this embodiment, all the regenerative energy is stored in the electric double layer capacitor EDLC, and the stored energy is released during power running. This means that the storage battery current Ib flows at time t1 to t2 when the regenerative current is generated. All of the regenerative current becomes the capacitor current Ic, and as a result, the charging voltage of the electric double layer capacitor EDLC gradually increases.
Therefore, according to this embodiment, since the capacitor current is controlled to coincide with the load current (= charge current command value), the charge / discharge control by the capacitor current is given priority. When the electric double layer capacitor is fully charged or reaches the discharge limit voltage, the step-up / step-down chopper is stopped or the chopper command value is set to 0, and then charge / discharge control of the storage battery is performed. For this reason, the voltage and current fluctuations of the storage battery are suppressed in the same manner as in each of the embodiments. In particular, the charge / discharge control of the storage battery is reduced, and the discharge energy of the storage battery can be reduced (reduction of the burden on the storage battery). Thus, the life of the storage battery can be extended.
Needless to say, the voltage value, current value, and load variation pattern need not be the patterns shown in FIG.

二次電池と電気二重層キャパシタを使用した複合電源装置の構成図。The block diagram of the composite power supply device using a secondary battery and an electrical double layer capacitor. 本発明の実施例１による制御装置の構成図。The block diagram of the control apparatus by Example 1 of this invention. 本発明の実施例１によるシミュレーション結果図。The simulation result figure by Example 1 of this invention. 本発明の実施例２による制御装置の構成図。The block diagram of the control apparatus by Example 2 of this invention. 実施例２に使用されるフラグ発生手段の構成図。The block diagram of the flag generation means used for Example 2. FIG. 本発明の実施例２によるシミュレーション結果図。The simulation result figure by Example 2 of this invention. 本発明の実施例３による制御装置の構成図。The block diagram of the control apparatus by Example 3 of this invention. 実施例３に使用されるフラグ発生手段の構成図。FIG. 6 is a configuration diagram of flag generation means used in the third embodiment. 本発明の実施例３によるシミュレーション結果図。The simulation result figure by Example 3 of this invention. 本発明の実施例４による制御装置の構成図。The block diagram of the control apparatus by Example 4 of this invention. 実施例４に使用されるフラグ発生手段の構成図。FIG. 9 is a configuration diagram of flag generation means used in the fourth embodiment. 本発明の実施例４によるシミュレーション結果図。The simulation result figure by Example 4 of this invention. 実施例５に使用されるフラグ発生手段の構成図。FIG. 10 is a configuration diagram of flag generation means used in the fifth embodiment. 本発明の実施例５によるシミュレーション結果図。The simulation result figure by Example 5 of this invention. 本発明の実施例６による制御装置の構成図。The block diagram of the control apparatus by Example 6 of this invention. 本発明の実施例６によるシミュレーション結果図。The simulation result figure by Example 6 of this invention. 本発明の実施例７による制御のフローチャート。The flowchart of control by Example 7 of this invention. 本発明の実施例７による制御装置の構成図。The block diagram of the control apparatus by Example 7 of this invention. 本発明の実施例７によるシミュレーション結果図。The simulation result figure by Example 7 of this invention. 二次電池と電気二重層キャパシタを使用した電動機駆動回路図。The motor drive circuit diagram using a secondary battery and an electric double layer capacitor.

符号の説明Explanation of symbols

Ｂ… 蓄電池（二次電池）
ＥＤＬＣ… 電気二重層キャパシタ
ＩＶ… インバータ
Ｍ… ＡＣモータ
Ｃ… コンデンサ
Ｃｈ… 昇降圧チョッパ
Ｓ１… 昇圧用スイッチング素子
Ｓ２… 降圧用スイッチング素子
Ｌ… リアクトル B ... Storage battery (secondary battery)
EDLC ... Electric double layer capacitor IV ... Inverter M ... AC motor C ... Capacitor Ch ... Buck-boost chopper S1 ... Step-up switching element S2 ... Step-down switching element L ... Reactor

Claims (7)

インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
前記蓄電池電圧指令値と検出した蓄電池電圧の差信号をＰＩ制御器に入力してＰＩ演算を実行し、この演算値を電気二重層キャパシタの充放電設定値とし、この充放電設定値に基づいてＰＷＭ制御部を介して昇降圧チョッパを制御することを特徴とした複合電源装置の制御回路。 As a power source for an AC motor controlled via an inverter, in a composite power supply apparatus in which a step-up / down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel,
A difference signal between the storage battery voltage command value and the detected storage battery voltage is input to a PI controller to perform a PI calculation. This calculation value is used as a charge / discharge set value for the electric double layer capacitor, and based on the charge / discharge set value. A control circuit for a composite power supply apparatus, wherein the step-up / step-down chopper is controlled via a PWM control unit. 充電時蓄電池電圧指令値と放電時蓄電池電圧指令値を各別に設け、
充電時蓄電池電圧指令値と検出した蓄電池電圧の差信号は、蓄電池電圧＞充電時蓄電池電圧指令値のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、放電時蓄電池電圧指令値と検出した蓄電池電圧の差信号は、蓄電池電圧＜放電時蓄電池電圧指令値のときに発生するキャパシタ放電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、各ＰＩ演算値を電気二重層キャパシタの充電設定値と放電設定値とすることを特徴とした請求項1記載の複合電源装置の制御回路。 A battery voltage command value for charging and a battery voltage command value for discharging are provided separately,
The difference signal between the storage battery voltage command value during charging and the detected storage battery voltage is multiplied by the capacitor charging flag generated by the multiplication unit when the storage battery voltage is greater than the storage battery voltage command value during charging, and then PI calculation is performed by the PI controller. The difference signal between the discharged storage battery voltage command value and the detected storage battery voltage is multiplied by a capacitor discharge flag generated when the storage battery voltage <the discharged storage battery voltage command value and the multiplication unit, and then PI calculation is performed by the PI controller. 2. The control circuit for a composite power supply apparatus according to claim 1, wherein each PI calculation value is set as a charge set value and a discharge set value of the electric double layer capacitor. インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
充電時チョッパ電流指令値、充電時蓄電池電力指令値、及び放電時蓄電池電力指令値を各別に設け、充電時チョッパ電流指令値とチョッパ電流の差信号は、０＜蓄電池電力＜充電時蓄電池電力指令値のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、
充電時蓄電池電力指令値と蓄電池電力の差信号は、蓄電池電力＜０のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、
放電時蓄電池電力指令値と蓄電池電力の差信号は、蓄電池電力＞放電時蓄電池電力指令値のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、
各ＰＩ演算値を電気二重層キャパシタの充電設定値と放電設定値を算出することを特徴とした複合電源装置の制御回路。 As a power source for an AC motor controlled via an inverter, in a composite power supply apparatus in which a step-up / down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel,
A chopper current command value during charging, a battery power command value during charging, and a battery power command value during discharging are provided separately, and the difference signal between the chopper current command value during charging and the chopper current is 0 <storage battery power <charging battery power command. PI multiplication is performed by the PI controller after multiplying the capacitor charging flag generated at the time of the value by the multiplication unit,
The difference signal between the charging battery power command value and the storage battery power is multiplied by the capacitor charging flag generated when the storage battery power <0 and the multiplication unit, and then PI calculation is performed by the PI controller.
The difference signal between the storage battery power command value at the time of discharge and the storage battery power is multiplied by the capacitor charging flag generated by the multiplication unit when the storage battery power> the storage battery power command value at the time of discharge, and then the PI operation is performed by the PI controller.
A control circuit for a composite power supply apparatus, wherein each PI calculation value is calculated as a charge set value and a discharge set value of an electric double layer capacitor. インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
充電時蓄電池電流指令値と放電時蓄電池電流指令値を各別に設け、
充電時蓄電池電流指令値と蓄電池電流の差信号は、蓄電池電流＜充電時蓄電池電流指令値のときに発生するキャパシタ充電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、
放電時蓄電池電流指令値と蓄電池電流の差信号は、蓄電池電流＞放電時蓄電池電流指令値のときに発生するキャパシタ放電フラグと乗算部で乗算した後にＰＩ制御器でＰＩ演算を実行し、各ＰＩ演算値を電気二重層キャパシタの充電設定値と放電設定値とすることを特徴とした複合電源装置の制御回路。 As a power source for an AC motor controlled via an inverter, in a composite power supply apparatus in which a step-up / down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel,
A battery current command value for charging and a battery current command value for discharging are provided separately,
The difference signal between the storage battery current command value during charging and the storage battery current is multiplied by a capacitor charging flag generated by the multiplier when the storage battery current <the storage battery current command value during charging, and then a PI operation is performed by the PI controller.
The difference signal between the battery current command value during discharge and the battery current is obtained by multiplying the capacitor discharge flag generated when the battery current> the battery current command value during discharge by the multiplier and then performing PI calculation in the PI controller. A control circuit for a composite power supply apparatus, characterized in that a calculated value is a charge set value and a discharge set value of an electric double layer capacitor. 前記キャパシタ充電フラグは、負荷電流＜充電時蓄電池電流指令値のときに発生し、前記キャパシタ放電フラグは、負荷電流＞充電時蓄電池電流指令値のときに発生することを特徴とした請求項４記載の複合電源装置の制御回路。 5. The capacitor charge flag is generated when load current <charge-time battery current command value, and the capacitor discharge flag is generated when load current> charge-time battery current command value. Control circuit for the combined power supply. インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
昇降圧チョッパの充電時チョッパ変調率が一定の変調率に設定された充電時チョッパ変調率設定部と、放電時チョッパ変調率が一定の変調率に設定された放電時チョッパ変調率設定部を設け、検出された負荷電流が充電時蓄電池電流指令値より小のときに充電時チョッパ変調率設定部、及びＰＷＭ制御部を介して昇降圧チョッパの充電制御を実行し、負荷電流が充電時蓄電池電流指令値より大のとき放電時チョッパ変調率設定部、及びＰＷＭ制御部を介して昇降圧チョッパの放電制御を行うこと特徴とした複合電源装置の制御回路。 As a power source for an AC motor controlled via an inverter, in a composite power supply apparatus in which a step-up / down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel
A chopper modulation rate setting unit for charging and a chopper modulation rate setting unit for discharging and setting a constant chopper modulation rate for discharging and a chopper modulation rate setting for discharging are provided. When the detected load current is smaller than the charging battery current command value, charging control of the step-up / step-down chopper is executed via the charging chopper modulation factor setting unit and the PWM control unit, and the load current is charging battery current A control circuit for a composite power supply apparatus, wherein discharge control of a step-up / step-down chopper is performed via a chopper modulation factor setting unit during discharge and a PWM control unit when larger than a command value. インバータを介して制御されるＡＣモータの電源として、蓄電池と電気二重層キャパシタを充放電制御する昇降圧チョッパを並列接続した複合電源装置において、
前記電気二重層キャパシタの充電電流指令値とキャパシタ電流の差信号を入力してキャパシタ充電電流を演算するＰＩ制御器と、放電電流指令値とキャパシタ電流の差信号を入力してキャパシタ放電電流を演算するＰＩ制御器と、各ＰＩ制御器にて算出されたＰＩ制御信号に基づいて昇降圧チョッパの制御信号を生成するＰＷＭ制御部を設け、直流電流が蓄電池、電気二重層キャパシタ側に流れている
ときに前記電気二重層キャパシタの充電制御を行い、直流電流がＡＣモータ側に流れているときに放電制御を行うよう構成したことを特徴とした複合電源装置の制御回路。 As a power source for an AC motor controlled via an inverter, in a composite power supply apparatus in which a step-up / down chopper for charge / discharge control of a storage battery and an electric double layer capacitor is connected in parallel,
PI controller that calculates the capacitor charge current by inputting the charge current command value of the electric double layer capacitor and the capacitor current, and the capacitor discharge current by inputting the difference signal of the discharge current command value and the capacitor current And a PWM control unit that generates a control signal for the step-up / step-down chopper based on the PI control signal calculated by each PI controller, and direct current flows to the storage battery and the electric double layer capacitor side A control circuit for a composite power supply apparatus, characterized in that charging control of the electric double layer capacitor is sometimes performed and discharging control is performed when a direct current is flowing to the AC motor side.
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