JP2010114350A - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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Abstract
【解決手段】ウエハW2の主面上の表面保護膜48とウエハW3の裏面との間で、第1バンプ電極50が形成されていない領域に、スペーサ49と第2バンプ電極50aとを積層した支持部を形成することによって、ウエハW3のたわみを防いで、ウエハW2の主面上の表面保護膜48とウエハW3の裏面との間隔をウエハ面内で均一に保つ。これにより、ウエハW2の主面上の表面保護膜48とウエハW3の裏面との間の接着剤51の未充填箇所の生成を防ぐ。
【選択図】図25
Description
本実施の形態1の半導体装置は、互いに異なる集積回路が形成された3枚の半導体チップ(以下、単にチップという)C1,C2,C3を積層して貼り合わせた3次元構造を有している。図1は、この半導体装置を配線基板1に実装してモールド樹脂2で封止したパッケージの一例を示す断面図である。
本発明の実施の形態2による半導体装置を示す半導体ウエハの要部断面図を図28に示す。
本発明の実施の形態3による半導体装置を示す半導体ウエハの要部断面図を図29に示す。ここでは、積層して貼り合わせたウエハW1とウエハW2とを用いて説明する。
2 モールド樹脂
3 接着剤
4 貫通電極
4A 導電溝
4C 導電部
5 ボンディングパッド
6 電極
7 ワイヤ
8 配線
9 半田バンプ
20 酸化シリコン膜
21 窒化シリコン膜
22 素子分離溝
23 溝
24,24a 酸化シリコン膜
25 窒化シリコン膜
26 貫通分離部
26A 絶縁溝
26C 絶縁部
26a 貫通孔
27 酸化シリコン膜
28 多結晶シリコン膜
29 キャップ絶縁膜
30 n型ウエル
31 p型ウエル
32 ゲート絶縁膜
33 ゲート電極
34 n型半導体領域(ソース、ドレイン)
35 p型半導体領域(ソース、ドレイン)
36,37 酸化シリコン膜
38,39 第1層アルミニウム配線
40 窒化チタン膜
42 窒化チタン膜
43 タングステン膜
44 第1層間絶縁膜
45 第2層アルミニウム配線
46 第2層間絶縁膜
47 第3層アルミニウム配線
48 表面保護膜
49 スペーサ
50 第1バンプ電極
50a 第2バンプ電極
51 接着剤
C1,C2,C3 半導体チップ
Qn nチャネル型MISトランジスタ
Qp pチャネル型MISトランジスタ
W1,W2,W3 半導体ウエハ
Claims (10)
- 第1面上に集積回路が形成され、前記第1面と反対側の第2面から突出する貫通電極が形成された第1ウエハと、第1面上に集積回路が形成され、最上層配線に電気的に接続して第1バンプ電極が形成された第2ウエハとを積層して貼り合わせる工程を有する半導体装置の製造方法であって、
(a)前記第2ウエハの前記第1面上に前記最上層配線を覆う表面保護膜を形成する工程と、
(b)前記表面保護膜を加工して前記最上層配線の一部を露出させる工程と、
(c)前記(b)工程の後、前記第2ウエハの前記第1面上に絶縁膜を形成する工程と、
(d)前記第2ウエハの前記第1面上に形成された前記第1バンプ電極に、前記第1ウエハの前記第2面から突出する前記貫通電極を物理的に接触させる工程と、
(e)前記第1ウエハの前記第2面と前記第2ウエハの前記第1面上の前記表面保護膜との間に樹脂を充填する工程とからなるプロセスにおいて、
(f)前記(c)工程の前記絶縁膜を加工して前記最上層配線が露出していない領域の前記表面保護膜上に前記絶縁膜からなるスペーサを形成する工程と、
(g)前記(f)工程の後、同一工程で前記第2ウエハの前記第1面上の露出した前記最上層配線上に前記第1バンプ電極を形成し、前記スペーサ上に第2バンプ電極を形成する工程とを含むことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記絶縁膜はポリイミド樹脂膜であることを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、1つの前記スペーサ上に1つまたは2つ以上の前記第2バンプ電極を形成することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、2つ以上の前記スペーサ上に1つの前記第2バンプ電極を形成することを特徴とする半導体装置の製造方法。
- 請求項1記載の半導体装置の製造方法において、前記スペーサと前記第2バンプ電極とを積層した厚さは、前記第1ウエハの前記第2面と前記第2ウエハの前記第1面上の前記表面保護膜との間隔とほぼ同じであることを特徴とする半導体装置の製造方法。
- 第1面上に集積回路が形成され、前記第1面と反対側の第2面から突出する貫通電極が形成された第1ウエハと、第1面上に集積回路が形成され、最上層配線に電気的に接続して第1バンプ電極が形成された第2ウエハとを積層して貼り合わせる工程を有する半導体装置の製造方法であって、
(a)前記第2ウエハの前記第1面上に前記最上層配線を覆う表面保護膜を形成する工程と、
(b)前記表面保護膜を加工して前記第1バンプ電極が形成される領域の前記最上層配線の一部を露出させる工程と、
(c)前記第2ウエハの前記第1面上に形成された前記第1バンプ電極に、前記第1ウエハの前記第2面から突出する前記貫通電極を物理的に接触させる工程と、
(d)前記第1ウエハの前記第2面と前記第2ウエハの前記第1面上の前記表面保護膜との間に樹脂を充填する工程とからなるプロセスにおいて、
(e)前記(a)工程の前記表面保護膜を加工して前記第1バンプ電極が形成される領域の前記表面保護膜の厚さを前記第1バンプ電極が形成されない領域の前記表面保護膜の厚さよりも薄くする工程と、
(f)同一工程で前記第2ウエハの前記第1面上の露出した前記最上層配線上に前記第1バンプ電極を形成し、前記最上層配線が露出していない領域の前記表面保護膜上に第2バンプ電極を形成する工程とを含むことを特徴とする半導体装置の製造方法。 - 請求項1または6記載の半導体装置の製造方法において、前記第1ウエハの前記第2面と前記第2ウエハの前記第1面上の前記表面保護膜との間隔は5〜30μmであることを特徴とする半導体装置の製造方法。
- 請求項1または6記載の半導体装置の製造方法において、前記表面保護膜は、酸化シリコン膜、窒化シリコン膜、または酸化シリコン膜上に窒化シリコン膜を形成した積層膜からなることを特徴とする半導体装置の製造方法。
- 第1面上に形成された複数の第1集積回路と、前記第1面と反対側の第2面から突出する貫通電極とを含む第1チップと、
第1面上に形成された複数の第2集積回路と、前記複数の第2集積回路のいずれかに電気的に接続されて前記第1面上に形成された複数層の配線と、最上層配線の一部を露出して前記第1面上に形成された表面保護膜と、前記表面保護膜上に形成されたスペーサと、前記表面保護膜から露出する前記最上層配線と電気的に接続して形成された第1バンプ電極と、前記スペーサ上に形成された第2バンプ電極とを含む第2チップとを有し、
前記第1チップの前記第2面から突出する前記貫通電極が前記第2チップの前記第1面上の前記第1バンプ電極と物理的に接触しており、前記第1チップの前記第2面と前記第2チップの前記第1面上の前記表面保護膜との間に樹脂が充填されていることを特徴とする半導体装置。 - 第1面上に形成された複数の第1集積回路と、前記第1面と反対側の第2面から突出する貫通電極とを含む第1チップと、
第1面上に形成された複数の第2集積回路と、前記複数の第2集積回路のいずれかに電気的に接続されて前記第1面上に形成された複数層の配線と、最上層配線の一部を露出して前記第1面上に形成された表面保護膜と、前記表面保護膜から露出する前記最上層配線と電気的に接続して形成された第1バンプ電極と、前記表面保護膜上に形成された第2バンプ電極とを含む第2チップとを有し、
前記第1バンプ電極が形成された領域の前記表面保護膜の厚さは、前記第2バンプ電極が形成された領域の前記表面保護膜の厚さよりも薄く、
前記第1チップの前記第2面から突出する前記貫通電極が前記第2チップの前記第1バンプ電極と物理的に接触しており、前記第1チップの前記第2面と前記第2チップの前記第1面上の前記表面保護膜との間に樹脂が充填されていることを特徴とする半導体装置。
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