JP2010114287A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010114287A
JP2010114287A JP2008286161A JP2008286161A JP2010114287A JP 2010114287 A JP2010114287 A JP 2010114287A JP 2008286161 A JP2008286161 A JP 2008286161A JP 2008286161 A JP2008286161 A JP 2008286161A JP 2010114287 A JP2010114287 A JP 2010114287A
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semiconductor device
resin
semiconductor chip
frame
halogen
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JP5364338B2 (en
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Masahiro Kawaguchi
真寛 川口
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Rohm Co Ltd
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Rohm Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device hardly causing a failure and capable of carrying out stable operation over a long time. <P>SOLUTION: The semiconductor device 1 includes: a semiconductor chip 2; a frame 3 or a substrate for mounting the semiconductor chip 2 thereon; a resin without containing a halogenated flame retardant for sealing the semiconductor chip 2; and a gettering part 4 capturing impurity ions around the semiconductor chip 2. The semiconductor device can be applied to a module product where a printed board mounted with a lot of the semiconductor devices 1 or the semiconductor chips 2 is sealed by a halogen-free resin. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、樹脂封止された半導体装置に関する。 The present invention relates to a resin-sealed semiconductor device.

従来、トランジスタ、ダイオード、ＬＳＩ等の半導体チップを封止する樹脂には、難燃性剤としてＳｂＢｒが使用されていたが、Ｓｂ，Ｂｒ等のハロゲン系物質は環境に悪影響を与えるものとして、代替材料の使用が求められていた。 Conventionally, SbBr has been used as a flame retardant for resins encapsulating semiconductor chips such as transistors, diodes, LSIs, etc., but halogen-based substances such as Sb and Br can be used as alternatives as they adversely affect the environment. The use of materials was sought.

そこで、リン系難燃剤、金属水和物系難燃剤（特許文献１）などのＳｂ，Ｂｒ等を含むハロゲン系難燃剤を含有しないハロゲンフリー樹脂が提案されている。
特開２００８−７５７０号公報 Thus, halogen-free resins that do not contain halogen-based flame retardants including Sb, Br, etc., such as phosphorus-based flame retardants and metal hydrate-based flame retardants (Patent Document 1) have been proposed.
JP 2008-7570 A

しかしながら、上記のようなハロゲンフリー樹脂を用いることの影響として、従来使用していた樹脂よりもガラス転移点温度（以下Ｔｇと呼ぶ）が低いことが指摘されている。高温で電子デバイスを使用した場合、Ｔｇを超えると、樹脂の弾性率は急激に低下し、樹脂は柔らかくなり、材料間の密着性は低下する。界面間に存在する不純物イオンは、動作時のデバイスに印加された電界により引き寄せられ、柔らかくなった樹脂界面を移動しやすくなり、イオンマイグレーションを引き起こし、デンドライトもしくはリークパスを形成してしまう。その結果、半導体装置の長期的な安定動作に不具合をもたらす。 However, it has been pointed out that the glass transition temperature (hereinafter referred to as Tg) is lower than that of conventionally used resins as an influence of using the halogen-free resin as described above. When an electronic device is used at a high temperature, if the Tg is exceeded, the elastic modulus of the resin is drastically lowered, the resin becomes soft, and the adhesion between the materials is lowered. Impurity ions existing between the interfaces are attracted by the electric field applied to the device during operation, and easily move on the softened resin interface, causing ion migration and forming a dendrite or leak path. As a result, there is a problem in the long-term stable operation of the semiconductor device.

本発明の課題は、上記に鑑み、不良が生じにくく、長期的に安定した動作が可能な半導体装置を提供することにある。 In view of the above, an object of the present invention is to provide a semiconductor device that is less prone to defects and that can operate stably over the long term.

上記課題を達成するため、本発明の一態様によれば、半導体チップと、前記半導体チップを搭載するフレームもしくは基板と、前記半導体チップを封止するハロゲンフリー樹脂と、前記半導体チップの周辺に不純物イオンを捕獲するゲッタリング部とを有することを特徴とする半導体装置が提供される。 In order to achieve the above object, according to one embodiment of the present invention, a semiconductor chip, a frame or substrate on which the semiconductor chip is mounted, a halogen-free resin that seals the semiconductor chip, and impurities around the semiconductor chip A semiconductor device having a gettering portion for capturing ions is provided.

ハロゲンフリー樹脂を使用したとしても不純物イオンはゼロにはならず、プロセス中もしくは材料により不純物イオンが導入されることがある。また、高電圧デバイスになるほど素子の電界は大きくなり、不純物イオンの濃度は小さくても、不純物イオンは電界により引き寄せられマイグレーションを引き起こし、リークパスの形成を促進する方向に向かう。 Even when a halogen-free resin is used, impurity ions do not become zero, and impurity ions may be introduced during the process or depending on the material. Further, the higher the voltage device, the larger the electric field of the element, and even if the concentration of impurity ions is small, the impurity ions are attracted by the electric field and cause migration, which tends to promote the formation of a leak path.

これに対し、本発明は上記のように構成したので、不純物イオンの移動が制限され、リークパスや腐食の要因となるイオンマイグレーションの形成を抑制できるため、長期にわたる安定動作が可能な半導体装置を提供できる。 On the other hand, since the present invention is configured as described above, the movement of impurity ions is limited, and the formation of ion migration that causes leak paths and corrosion can be suppressed, so that a semiconductor device capable of stable operation over a long period of time is provided. it can.

次に、図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一または類似の部分には同一または類似の符号を付している。ただし、図面は模式的なものであり、現実のものとは異なる。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。 Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

また、以下に示す実施の形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の技術的思想は、各構成部品の配置などを下記のものに特定するものでない。この発明の技術的思想は、特許請求の範囲において、種々の変更を加えることができる。 Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is the arrangement of each component as described below. It is not something specific. The technical idea of the present invention can be variously modified within the scope of the claims.

本発明の実施の形態に係る半導体装置において、ハロゲンフリー樹脂とは原材料にハロゲン化合物及びアンチモン化合物を使用せず、かつ（１）塩素Ｃｌの含有率が０．０９ｗｔ％以下、（２）臭素Ｂｒの含有率が０．０９ｗｔ％以下、（３）アンチモンＳｂの含有率が０．０９ｗｔ％以下の基準を満たす樹脂と定義する。上記のように、ハロゲンフリー樹脂は必ずしもハロゲンの含有量がゼロになるということではない。Ｂｒイオンの含有量は極端に小さいが、それ以外のハロゲン系イオン、例えばＣｌイオンを含むハロゲンフリー樹脂もある。Ｃｌイオンは樹脂を形成する骨格高分子に含まれており、リークパスに悪影響を及ぼしていると考えられる。また、ハロゲンフリー樹脂として、実質的にハロゲン系難燃剤を含まない樹脂、あるいは金属水和物系難燃剤、リン系難燃剤の少なくとも一方を含む樹脂、あるいは難燃剤を含まない難燃剤レス樹脂が用いられる。難燃剤を含まない難燃剤レス樹脂は高分子の表面に皮膜を形成して酸素を遮断している。 In the semiconductor device according to the embodiment of the present invention, the halogen-free resin does not use a halogen compound and an antimony compound as raw materials, and (1) a chlorine Cl content is 0.09 wt% or less, and (2) bromine Br. Is defined as a resin that satisfies the standard of 0.09 wt% or less and (3) the content of antimony Sb is 0.09 wt% or less. As described above, halogen-free resins do not necessarily have a halogen content of zero. Although the content of Br ions is extremely small, there are halogen-free resins containing other halogen-based ions such as Cl ions. It is considered that Cl ions are contained in the skeleton polymer forming the resin and have an adverse effect on the leak path. Further, as the halogen-free resin, a resin that does not substantially contain a halogen-based flame retardant, a resin that includes at least one of a metal hydrate-based flame retardant and a phosphorus-based flame retardant, or a flame retardant-less resin that does not include a flame retardant. Used. A flame retardant-less resin containing no flame retardant forms a film on the surface of the polymer to block oxygen.

（第１実施形態） 図１は、本発明に係る半導体装置の第１実施形態を平面図で示している。図２には、図１のII-II線に沿う断面図を示している。図１および図２に示す半導体装置Ａ１は、半導体チップ１、フレーム２、ゲッタリング部３、ハンダ層４および、樹脂パッケージ５を備えた半導体装置である。なお、フレーム２の表面の様子を示すために、図１では、樹脂パッケージ５を省略している。図１は、フレーム２の厚み方向視における平面を示しており、以下の説明における平面視はフレーム２の厚み方向視と同一である。図３は本発明に係る半導体チップの一例であるＭＯＳＦＥＴの構造の断面図を示している。 First Embodiment FIG. 1 is a plan view showing a first embodiment of a semiconductor device according to the present invention. FIG. 2 shows a cross-sectional view taken along the line II-II in FIG. A semiconductor device A1 shown in FIGS. 1 and 2 is a semiconductor device including a semiconductor chip 1, a frame 2, a gettering portion 3, a solder layer 4, and a resin package 5. In addition, in order to show the state of the surface of the frame 2, the resin package 5 is omitted in FIG. FIG. 1 shows a plan view of the frame 2 in the thickness direction, and the plan view in the following description is the same as the view of the frame 2 in the thickness direction. FIG. 3 shows a sectional view of the structure of a MOSFET which is an example of a semiconductor chip according to the present invention.

半導体チップ１は、たとえば、トレンチゲート型のパワーＭＯＳＦＥＴである。上記ＭＯＳＦＥＴは、図３に示すように、Ｎ+型シリコン基板１１の上面上に、所定の厚みを有するシリコンからなるエピタキシャル層が形成されている。このエピタキシャル層には、Ｎ+型シリコン基板側から、Ｎ-型不純物領域１２、Ｐ-型不純物領域１３、および、Ｎ+型ソース領域１４が順次形成されている。そして、Ｎ+型ソース領域１４およびＰ-型不純物領域１３を貫通するように、複数のトレンチ１５がエピタキシャル層に形成されている。このトレンチ１５は、エピタキシャル層の所定領域がその上面（主表面）側からエッチングされることによって形成されている。すなわち、複数のトレンチ１５の各々の開口端は、エピタキシャル層の上面側に位置している。また、複数のトレンチ１５は、その各々がエピタキシャル層の上面に対して並行な所定方法に沿って延びるように細長状（ストライプ状）に形成されている。 また、複数のトレンチ１５は、エピタキシャル層の上面に対して並行で、かつ、トレンチ１５が延びる方向と直交する方向に所定の間隔を隔てて配列されている。さらに、複数のトレンチ１５の各々の溝深さは、エピタキシャル層の厚みよりも小さくなるように設定されている。具体的には、複数のトレンチ１５の各々の溝深さは、約１μｍ〜約３μｍに設定されている。また、複数のトレンチ１５の各々の幅は、約０．３μｍ〜約０．５μｍに設定されている。 The semiconductor chip 1 is, for example, a trench gate type power MOSFET. In the MOSFET, an epitaxial layer made of silicon having a predetermined thickness is formed on the upper surface of an N + type silicon substrate 11 as shown in FIG. In this epitaxial layer, an N − -type impurity region 12, a P − -type impurity region 13, and an N + -type source region 14 are sequentially formed from the N + -type silicon substrate side. A plurality of trenches 15 are formed in the epitaxial layer so as to penetrate the N + type source region 14 and the P − type impurity region 13. The trench 15 is formed by etching a predetermined region of the epitaxial layer from the upper surface (main surface) side. That is, the open end of each of the plurality of trenches 15 is located on the upper surface side of the epitaxial layer. The plurality of trenches 15 are formed in an elongated shape (stripe shape) so that each of the trenches 15 extends along a predetermined method parallel to the upper surface of the epitaxial layer. The plurality of trenches 15 are arranged in parallel to the upper surface of the epitaxial layer and at a predetermined interval in a direction orthogonal to the direction in which the trenches 15 extend. Further, the depth of each of the plurality of trenches 15 is set to be smaller than the thickness of the epitaxial layer. Specifically, the depth of each of the plurality of trenches 15 is set to about 1 μm to about 3 μm. The width of each of the plurality of trenches 15 is set to about 0.3 μm to about 0.5 μm.

また、上記したＮ+型ソース領域１４は、複数のトレンチ１５の各々がＮ+型ソース領域１４を貫通するように形成されることによって、複数のトレンチ１５の各々の縁部に形成されている。そして、互いに隣り合う２つのトレンチ１５の縁部に形成されたＮ+型ソース領域１４の間には、Ｎ+型ソース領域１４を貫通してＰ-型不純物領域と接するＰ+型ベース領域１６が形成されている。 The N + -type source region 14 is formed at the edge of each of the plurality of trenches 15 by forming each of the plurality of trenches 15 so as to penetrate the N + -type source region 14. . Between the N + -type source regions 14 formed at the edges of the two adjacent trenches 15, a P + -type base region 16 that penetrates the N + -type source region 14 and is in contact with the P − -type impurity region. Is formed.

また、複数のトレンチ１５の各々の内面には、エピタキシャル層を構成するシリコンを熱酸化処理することによって得られるＳｉＯ2からなるシリコン酸化膜１７が形成されている。このシリコン酸化膜１７は、Ｎ+型ソース領域１４の上面上に延設されている。また、複数のトレンチ１５の各々の内部には、シリコン酸化膜１７を介して、ポリシリコン層１８とタングステン１９からなるゲート電極２０が形成されている。 ゲート電極２０の上面上、および、エピタキシャル層の上面上には、ＳｉＯ2からなる層間絶縁膜２１が形成されている。この層間絶縁膜の所定領域には、Ｎ+型ソース領域の一部およびＰ+型ベース領域を露出させるコンタクトホールが形成されている。 また、エピタキシャル層の上面上には、層間絶縁膜２１を覆うとともに、コンタクトホールを埋めるように、Ａｌ、または、ＡｌとＳｉとの合金からなるソース電極２２が形成されている。このソース電極２２は、Ｎ+型ソース領域１４およびＰ+型ベース領域１６に対してオーミック接触されている一方、ゲート電極２０とは、層間絶縁膜２１によって電気的に絶縁されている。 A silicon oxide film 17 made of SiO 2 obtained by thermally oxidizing silicon constituting the epitaxial layer is formed on the inner surface of each of the plurality of trenches 15. The silicon oxide film 17 extends on the upper surface of the N + type source region 14. A gate electrode 20 made of a polysilicon layer 18 and tungsten 19 is formed in each of the plurality of trenches 15 with a silicon oxide film 17 interposed therebetween. An interlayer insulating film 21 made of SiO 2 is formed on the upper surface of the gate electrode 20 and the upper surface of the epitaxial layer. In a predetermined region of the interlayer insulating film, a contact hole exposing a part of the N + type source region and the P + type base region is formed. A source electrode 22 made of Al or an alloy of Al and Si is formed on the upper surface of the epitaxial layer so as to cover the interlayer insulating film 21 and fill the contact hole. The source electrode 22 is in ohmic contact with the N + type source region 14 and the P + type base region 16, while being electrically insulated from the gate electrode 20 by an interlayer insulating film 21.

一方、Ｎ+型シリコン基板の裏面上（エピタキシャル層とは反対側の面上）には、Ａｕ、Ｔｉ、Ｎｉ、Ａｇなどを含む多層構造体からなるドレイン電極２３が形成されている。このドレイン電極２３は、Ｎ+型シリコン基板１１に対してオーミック接触している。 On the other hand, a drain electrode 23 made of a multilayer structure containing Au, Ti, Ni, Ag, or the like is formed on the back surface of the N + -type silicon substrate (on the surface opposite to the epitaxial layer). The drain electrode 23 is in ohmic contact with the N + type silicon substrate 11.

フレーム２は、たとえばＣｕ製であり、厚さ１〜２ｍｍ程度の板状に形成されている。このフレーム２は、平面視において、四隅の角が丸く形成された、一辺の長さがたとえば２０ｍｍの正方形となっている。このフレームには溝２１が形成されている。 The frame 2 is made of Cu, for example, and is formed in a plate shape having a thickness of about 1 to 2 mm. The frame 2 has a square shape with one side having a length of, for example, 20 mm, with four corners rounded in plan view. A groove 21 is formed in this frame.

溝２１は、図１および図２に示すように、平面視においてＭＯＳＦＥＴを囲むように周辺に形成されている。この溝２１は、たとえば５μｍ〜４０μｍ程度、フレーム２の表面から凹んでいる。上記溝２１は、フレーム２もしくはフレーム２上に形成されたメッキと樹脂パッケージ５の樹脂との界面沿いに形成されたものであれば形状は問わない。上記溝２１は必ずしもＭＯＳＦＥＴを囲むように周辺に形成されている必要はなく、ＭＯＳＦＥＴの各辺と平行に４箇所に形成されていても良い。また、上記溝２１の内部には絶縁物２２を介してゲッタリング部３が埋め込まれている。電極が片側のみに形成され、電子の流れ横方向の半導体チップである場合は、ゲッタリング部３が溝２１に直接埋め込まれていてもよい。 As shown in FIGS. 1 and 2, the groove 21 is formed in the periphery so as to surround the MOSFET in plan view. The groove 21 is recessed from the surface of the frame 2 by about 5 μm to 40 μm, for example. The shape of the groove 21 is not limited as long as it is formed along the interface between the frame 2 or the plating formed on the frame 2 and the resin of the resin package 5. The groove 21 does not necessarily have to be formed in the periphery so as to surround the MOSFET, and may be formed in four places in parallel with each side of the MOSFET. Further, the gettering portion 3 is embedded in the groove 21 through an insulator 22. When the electrode is formed only on one side and is a semiconductor chip in the lateral direction of electron flow, the gettering portion 3 may be directly embedded in the groove 21.

ゲッタリング部３はたとえばコンデンサなどの分極材料が用いられる。分極材料はプラス、マイナス両方の電荷があるため、陽イオン、陰イオン双方の不純物イオンの捕獲において効果を発揮する。また、ゲッタリング部３はたとえば不純物イオンを捕獲する添加剤を塗布してもよいし、強誘電材料を埋め込んでもよい。 For the gettering unit 3, for example, a polarization material such as a capacitor is used. Since the polarization material has both positive and negative charges, it is effective in trapping both positive ions and negative ions. The gettering unit 3 may be coated with an additive for trapping impurity ions or may be embedded with a ferroelectric material.

ハンダ層４は、たとえば、直径５〜１０μｍ程度の金属粒が添加されたハンダ材によって形成されている。上記金属粒としては、たとえばＡｇ，ＣｕまたはＴｅが用いられる。このハンダ層３は、平面視においてゲッタリング部３の内縁近傍まで広がっている。 The solder layer 4 is formed of, for example, a solder material to which metal particles having a diameter of about 5 to 10 μm are added. For example, Ag, Cu, or Te is used as the metal particles. The solder layer 3 extends to the vicinity of the inner edge of the gettering portion 3 in plan view.

樹脂パッケージ５は、実質的にハロゲン系難燃剤を含有しないハロゲンフリー樹脂である。たとえば、金属水和物系難燃剤、リン系難燃剤の少なくとも一方を含む樹脂、あるいは難燃剤を含まない難燃剤レス樹脂が用いられる。また、樹脂パッケージ５はＭＯＳＦＥＴ１、フレーム２、ゲッタリング部３、およびハンダ層４を覆うように形成されており、ＭＯＳＦＥＴ１、フレーム２、ゲッタリング部３、およびハンダ層４を保護している。 The resin package 5 is a halogen-free resin that does not substantially contain a halogen-based flame retardant. For example, a resin containing at least one of a metal hydrate flame retardant and a phosphorus flame retardant, or a flame retardant-less resin containing no flame retardant is used. The resin package 5 is formed so as to cover the MOSFET 1, the frame 2, the gettering portion 3, and the solder layer 4, and protects the MOSFET 1, the frame 2, the gettering portion 3, and the solder layer 4.

次に、上記構成の半導体装置Ａ１の作用について説明する。 Next, the operation of the semiconductor device A1 having the above configuration will be described.

本実施形態によれば、不純物イオンを捕獲するゲッタリング部３を設けているため、ＭＯＳＦＥＴの動作時に不純物イオンがＭＯＳＦＥＴの電界により引き寄されるのを低減することができ、リークパスや腐食の要因となるイオンマイグレーションの形成を抑制することができる。 According to the present embodiment, since the gettering unit 3 that captures impurity ions is provided, the impurity ions can be reduced from being attracted by the electric field of the MOSFET during the operation of the MOSFET. The formation of ion migration can be suppressed.

また、本実施形態ではゲッタリング部３にコンデンサなどの分極材料が用いて説明したが、これに限定されるものではなく、分極材料の代わりにポリシリコン３１を用いても良い。図４は、ポリシリコンを使用した場合の本発明に係る半導体装置を平面図で示している。ポリシリコン３１はたとえばＭＯＳＦＥＴの各辺と平行に４箇所に形成されており、Ｐ型ポリシリコンとＮ型ポリシリコンとを５０μｍごとに交互に設けられている。実際のＰＣＢＴ試験をはじめとする耐湿性試験において、オバーク分析によりポリシリコン部３１が発光することが確認されている。これは不純物イオンがポリシリコン３１に捕獲されていることを意味する。従って、半導体チップ１の動作に直接関係しない部分に、上記のようなポリシリコン３１を設けることで、不純物イオンを捕獲する機能をもたせることができる。 In the present embodiment, the gettering unit 3 has been described using a polarization material such as a capacitor. However, the present invention is not limited to this, and polysilicon 31 may be used instead of the polarization material. FIG. 4 is a plan view showing a semiconductor device according to the present invention when polysilicon is used. Polysilicon 31 is formed at, for example, four locations in parallel with each side of the MOSFET, and P-type polysilicon and N-type polysilicon are alternately provided every 50 μm. In a moisture resistance test including an actual PCBT test, it has been confirmed that the polysilicon portion 31 emits light by an overburst analysis. This means that impurity ions are trapped in the polysilicon 31. Therefore, by providing the polysilicon 31 as described above in a portion not directly related to the operation of the semiconductor chip 1, it is possible to have a function of capturing impurity ions.

図５〜図１５は、本発明の他の実施形態を示している。なお、これらの図において上記実施形態と同一または類似の要素には、上記実施形態と同一の符号を付し、説明を省略している。 （第２実施形態） 図５は、本発明に係る半導体装置の第２実施形態を平面図で示している。図６には、図５のVI-VI線に沿う断面図を示している。図５および図６に示す半導体装置Ａ２は、半導体チップ１０１、部分的にメッキ６が施されたフレーム２０１、ゲッタリング部３２、ハンダ層４および、樹脂パッケージ５２を備えた半導体装置である。なお、フレーム２０１の表面の様子を示すために、図５では、樹脂パッケージ５２を省略している。図５に示す半導体装置Ａ２では、フレーム２０１の表面で、かつ半導体チップ１０１の周辺にゲッタリング部３２が形成されている。 5 to 15 show other embodiments of the present invention. In these drawings, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment, and description thereof is omitted. Second Embodiment FIG. 5 is a plan view showing a second embodiment of a semiconductor device according to the present invention. FIG. 6 shows a cross-sectional view taken along the line VI-VI in FIG. A semiconductor device A2 shown in FIGS. 5 and 6 is a semiconductor device including a semiconductor chip 101, a frame 201 partially plated 6, a gettering portion 32, a solder layer 4, and a resin package 52. In addition, in order to show the state of the surface of the frame 201, the resin package 52 is omitted in FIG. In the semiconductor device A <b> 2 shown in FIG. 5, the gettering portion 32 is formed on the surface of the frame 201 and around the semiconductor chip 101.

半導体チップ１０１はたとえば中電流および大電流用のパワートランジスタが用いられる。 As the semiconductor chip 101, for example, power transistors for medium current and large current are used.

フレーム２０１はＣｕ製であるが、たとえばＡｇやＮｉといったハンダとの濡れ性のよい金属材料によりメッキされたフレーム２０１であってもよい。また、半導体チップ１０１のフレーム２０１と対向する側の面に、ＡｇやＮｉといったハンダとの濡れ性のよい金属材料によるメッキを施してもよい。 The frame 201 is made of Cu, but may be a frame 201 plated with a metal material having good wettability with solder such as Ag or Ni. Further, the surface of the semiconductor chip 101 facing the frame 201 may be plated with a metal material having good wettability with solder such as Ag or Ni.

ゲッタリング部３２は半導体チップ１０１の周辺のメッキを施していない部分で形成されている。たとえば、硫酸、硝酸などの酸により選択的にエッチングすることでメッキを除去し、ゲッタリング部３２を形成することが好ましい。ゲッタリング部３２は平面視において半導体チップ１０１を囲むように周辺に形成されていてもよいし、半導体チップ１０１と平行に直線状に形成されていてもよい。ゲッタリング部３２は樹脂パッケージ５２の外表面から半導体チップ１０１までの間で、かつ樹脂とフレーム２０１との界面に形成されていればよい。通常フレームと樹脂との界面は水
素結合で密着しているため、メッキを施していない部分を粗面化したり、中性子照射、レーザ照射、プラズマ処理を施したりすることで、部分的に未結合手部（ダングリングボンド）を形成するのが好ましい。 The gettering portion 32 is formed at a portion around the semiconductor chip 101 that is not plated. For example, the gettering portion 32 is preferably formed by removing the plating by selective etching with an acid such as sulfuric acid or nitric acid. The gettering portion 32 may be formed in the periphery so as to surround the semiconductor chip 101 in plan view, or may be formed in a straight line parallel to the semiconductor chip 101. The gettering portion 32 may be formed between the outer surface of the resin package 52 and the semiconductor chip 101 and at the interface between the resin and the frame 201. Normally, the interface between the frame and the resin is in close contact by hydrogen bonding, so the unplated part can be partially removed by roughening the unplated part, or by applying neutron irradiation, laser irradiation, or plasma treatment. It is preferable to form a part (dangling bond).

このような半導体装置Ａ２では、メッキが施されていないゲッタリング部３２はメッキを施した部分に比べて、ダングリングボンドが多くなる。このため、不純物イオンを半導体チップに到達するまでにダングリングボンドに結合させ捕獲することができる。 In such a semiconductor device A2, the gettering portion 32 that is not plated has more dangling bonds than the plated portion. For this reason, impurity ions can be bound to and captured by dangling bonds before reaching the semiconductor chip.

本実施形態ではフレーム２０１の表面に部分的にメッキを施こしたが、フレームの表面全体にメッキを施してもよい。この場合、ゲッタリング部として機能させたい部分を粗面化したり、中性子照射、プラズマ処理を施したりすることで、メッキ上の必要な箇所、たとえば半導体チップの周辺に未結合手部（ダングリングボンド）を形成することができる。 In the present embodiment, the surface of the frame 201 is partially plated, but the entire surface of the frame may be plated. In this case, unbonded hands (dangling bonds) are formed at the necessary places on the plating, for example, around the semiconductor chip, by roughening the part to be functioned as the gettering part, neutron irradiation or plasma treatment. ) Can be formed.

また、本実施形態ではメッキ（第１のメッキ）が施されていない部分に不純物イオンと結合性の良いメッキ（第２のメッキ）を施しても良い。この場合、第２のメッキ部分がゲッタリング部として機能する。 第１のメッキはＣｕ、ＡｇもしくはＮｉを使用し、 第２のメッキは第１のメッキよりダングリングボンドの多い金属、たとえばＨよりイオン化傾向の大きい金属Ｍｇ，Ｚｎを使用するのが好ましい。このような半導体装置では、少なくとも２種類のメッキを施しているため、不純物イオンと結合性が良い方のメッキによって不純物イオンを捕獲することができる。樹脂パッケージとしてＢｒイオンの含有量は極端に小さいが、それ以外のハロゲン系イオン、例えばＣｌイオンを含むハロゲンフリー樹脂を使用した場合、第２のメッキはＣｌイオンを捕獲しやすい金属、たとえばリンをドープした金属を用いることが好ましい。 Further, in the present embodiment, plating (second plating) having good binding properties with impurity ions may be applied to a portion where plating (first plating) is not applied. In this case, the second plating portion functions as a gettering portion. The first plating preferably uses Cu, Ag or Ni, and the second plating preferably uses a metal having more dangling bonds than the first plating, such as metals Mg and Zn having a higher ionization tendency than H. In such a semiconductor device, since at least two types of plating are performed, the impurity ions can be captured by plating having better bonding with impurity ions. Although the content of Br ions in the resin package is extremely small, when a halogen-free resin containing other halogen-based ions such as Cl ions is used, the second plating uses a metal that easily traps Cl ions, such as phosphorus. It is preferable to use a doped metal.

（第３実施形態） 図７は、本発明に係る半導体装置の第３実施形態を平面図で示している。図８には、図７のVIII-VIII線に沿う断面図を示している。図７および図８に示す半導体装置Ａ３は、半導体チップ１０２、複数の突起７が形成されたフレーム２０２、ゲッタリング部３３および樹脂パッケージ５３を備える。 Third Embodiment FIG. 7 shows a plan view of a third embodiment of a semiconductor device according to the present invention. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7 and 8 includes a semiconductor chip 102, a frame 202 on which a plurality of protrusions 7 are formed, a gettering portion 33, and a resin package 53.

半導体チップ１０２は、たとえば、一辺の長さが４ｍｍ程度の電力の制御を行うパワーＩＣである。半導体チップ１０２は、平面視において、四隅の頂角が丸く形成された正方形状に形成されている。半導体チップ１０２の外周縁は、たとえばレーザを用いて上下から切断することにより、曲面で構成されている。この半導体チップ１は、フレームの表面にハンダ層を介して搭載されている。 The semiconductor chip 102 is, for example, a power IC that controls power with a side length of about 4 mm. The semiconductor chip 102 is formed in a square shape in which the apex angles of the four corners are round in a plan view. The outer peripheral edge of the semiconductor chip 102 is configured by a curved surface, for example, by cutting from above and below using a laser. The semiconductor chip 1 is mounted on the surface of the frame via a solder layer.

フレーム２０２は、たとえばＣｕ製であり、厚さ１〜２ｍｍ程度の板状に形成されている。このフレーム２０２は、平面視において、四隅の角が丸く形成された正方形となっている。このフレーム２０２には、８個の同形の突起７が形成されている。 The frame 202 is made of Cu, for example, and is formed in a plate shape having a thickness of about 1 to 2 mm. The frame 202 has a square shape with rounded corners in plan view. On the frame 202, eight isomorphous protrusions 7 are formed.

各突起７は、図に仮想線で示した、半導体チップ１０２よりも大きい正方形Ｂ１の各辺に沿って延びるように形成されている。この正方形Ｂ１の各辺は半導体チップ１０２の各辺と平行となっている。各突起７は、正方形Ｂ１の各頂点周辺までは延びていない。さらに、図８に示すように、各突起７の断面は半円状に形成されている。各突起７は、たとえば５μｍ〜４０μｍ程度、フレーム２０２の表面から突き出している。 Each protrusion 7 is formed so as to extend along each side of the square B <b> 1 larger than the semiconductor chip 102, which is indicated by a virtual line in the drawing. Each side of the square B1 is parallel to each side of the semiconductor chip 102. Each protrusion 7 does not extend to the periphery of each vertex of the square B1. Furthermore, as shown in FIG. 8, the cross section of each protrusion 7 is formed in a semicircular shape. Each protrusion 7 protrudes from the surface of the frame 202, for example, about 5 μm to 40 μm.

ゲッタリング部３３は平行に並んだ二つの突起７の間に形成されている。ゲッタリング部３３は、たとえばコンデンサなどの分極材料，不純物イオンを捕獲する添加剤、強誘電材料、ポリシリコンなどが用いられる。分極材料はプラス、マイナス両方の電荷があるため、陽イオン、陰イオン双方の不純物イオンの捕獲において効果を発揮する。 The gettering portion 33 is formed between two protrusions 7 arranged in parallel. For the gettering portion 33, for example, a polarization material such as a capacitor, an additive for trapping impurity ions, a ferroelectric material, polysilicon, or the like is used. Since the polarization material has both positive and negative charges, it is effective in trapping both positive ions and negative ions.

このような半導体装置Ａ３では、突起７により樹脂とフレーム２０２との界面に入り込んだ不純物イオンや水分のリークパスを長くすることができるため、半導体チップの動作時に不純物イオンが半導体チップの電界により引き寄されるのを低減することができ、リークパスや腐食の要因となるイオンマイグレーションの形成を抑制することができる。また、突起７を設けることで樹脂パッケージ５３とフレーム２０２との接触面積が大きくなるので、密着強度をあげることができる。 In such a semiconductor device A3, since the impurity ion or moisture leak path that has entered the interface between the resin and the frame 202 can be lengthened by the protrusion 7, the impurity ions are attracted by the electric field of the semiconductor chip during the operation of the semiconductor chip. The formation of ion migration that causes leak paths and corrosion can be suppressed. Moreover, since the contact area between the resin package 53 and the frame 202 is increased by providing the protrusions 7, the adhesion strength can be increased.

（第４実施形態） 図９は、本発明に係る半導体装置の第４実施形態を平面図で示している。図９に示す半導体装置Ａ４は、半導体チップ１０３、フレーム２０３、ゲッタリング部３４、第１インナーリード８、第２インナーリード９および樹脂パッケージ５４を備える。 Fourth Embodiment FIG. 9 is a plan view showing a fourth embodiment of a semiconductor device according to the present invention. A semiconductor device A4 shown in FIG. 9 includes a semiconductor chip 103, a frame 203, a gettering portion 34, a first inner lead 8, a second inner lead 9, and a resin package 54.

半導体チップ１０３は、たとえば、一方の面にゲート電極１Ａ、ソース電極１Ｂ、他方の面にドレイン電極１Ｃが形成されたＭＯＳＦＥＴである。ドレイン電極１Ｃはフレーム２０３と接続している。ゲート電極１Ａは第１インナーリード８と接続している。ソース電極１Ｂは第２インナーリード９と接続している。 The semiconductor chip 103 is, for example, a MOSFET in which a gate electrode 1A and a source electrode 1B are formed on one surface, and a drain electrode 1C is formed on the other surface. The drain electrode 1 </ b> C is connected to the frame 203. The gate electrode 1 </ b> A is connected to the first inner lead 8. The source electrode 1B is connected to the second inner lead 9.

ゲッタリング部３４は、たとえば金属膜からなり、絶縁層を介してフレーム２０３上に形成されている。また、ゲッタリング部３４は半導体チップ１０３から離間し、かつ半導体チップ１０３と平行に二ヶ所に形成されており、それぞれ第１インナーリード８、第２インナーリード９に接続している。 The gettering portion 34 is made of, for example, a metal film, and is formed on the frame 203 via an insulating layer. Further, the gettering portion 34 is formed at two locations that are separated from the semiconductor chip 103 and parallel to the semiconductor chip 103, and are connected to the first inner lead 8 and the second inner lead 9, respectively.

このような半導体装置Ａ４では、ゲッタリング部３４に電圧を印加し、電子部品１０３かかる電界よりも大きい電界をゲッタリング部３４にかけることで、半導体チップ１０３への電界の集中を緩和することができ、不純物イオンの半導体チップ１０３への悪影響を防止することができる。 In such a semiconductor device A4, it is possible to reduce the concentration of the electric field on the semiconductor chip 103 by applying a voltage to the gettering unit 34 and applying an electric field larger than the electric field applied to the electronic component 103 to the gettering unit 34. In addition, the adverse effect of impurity ions on the semiconductor chip 103 can be prevented.

また、本発明においては、ゲッタリング部３４に電界をかけるかわりに、電流を流すことで磁界を発生させ、不純物イオンが半導体チップ１０３に集まるのを防止してもよい。この場合、たとえば半導体チップ１０３から離間し、かつ半導体チップ１０３を囲むようにコの字状に金属配線を形成する。第１インナーリード８と上記金属配線の一端を電気的に接続し、第２インナーリード９と上記金属配線の他端とを電気的に接続する。フレミングの法則により、上記金属配線に電流を流すことで磁界を発生させ、不純物イオンの動く方向をコントロールし、不純物イオンが半導体チップ１０３に集まるのを防止する。磁界を発生させ、不純物イオンの動く方向をコントロールすることは、たとえば３０Ｖ以上の耐圧を有するパワーデバイスにおいて極めて有効である。また、モジュール製品においては外部から電源を取り、金属配線に電流を流してもよい。 In the present invention, instead of applying an electric field to the gettering portion 34, a magnetic field may be generated by flowing a current to prevent impurity ions from collecting on the semiconductor chip 103. In this case, for example, a metal wiring is formed in a U shape so as to be separated from the semiconductor chip 103 and surround the semiconductor chip 103. The first inner lead 8 and one end of the metal wiring are electrically connected, and the second inner lead 9 and the other end of the metal wiring are electrically connected. According to Fleming's law, a magnetic field is generated by passing a current through the metal wiring, the direction of movement of impurity ions is controlled, and impurity ions are prevented from collecting on the semiconductor chip 103. Controlling the direction of movement of impurity ions by generating a magnetic field is extremely effective in a power device having a breakdown voltage of 30 V or more, for example. Moreover, in module products, a power supply may be taken from the outside and an electric current may be sent through metal wiring.

（第５実施形態） 図１０は、本発明に係る半導体装置の第５実施形態を断面図で示している。図１０に示す電子デバイスＡ５は、半導体チップ１０４、フレーム２０４、第１樹脂層５５Ａ、第２樹脂層５５Ｂ、第３樹脂層５５Ｃおよびゲッタリング部３５を備える。 Fifth Embodiment FIG. 10 is a sectional view showing a fifth embodiment of a semiconductor device according to the present invention. The electronic device A5 illustrated in FIG. 10 includes the semiconductor chip 104, the frame 204, the first resin layer 55A, the second resin layer 55B, the third resin layer 55C, and the gettering unit 35.

第１樹脂層５５Ａは半導体チップ１０４のクラックを、ハンダなどのダイボンディング材のクラックを防止するために電子部品の熱膨張係数に近い値で、かつ弾性率が低い樹脂を使用する。半導体チップの主成分がＳｉの場合は第１樹脂層５５Ａの熱膨張係数は２１ｐｐｍ／℃に近いほど良い。また、ワイヤの変形やはがれを防止するためにワイヤの熱膨張係数に近い値を持つ樹脂を使用してもよい。その場合Ａｌ（２３ｐｐｍ／℃）、Ｃｕ（１７ｐｐｍ／℃）、Ａｕ（１４．２ｐｐｍ／℃）の熱膨張係数に近い値を持つ樹脂を使用するのが好ましい。また、弾性率を下げるために第１樹脂層５５Ａにシリコーンを添加することが好ましい。 The first resin layer 55A uses a resin having a value close to the thermal expansion coefficient of the electronic component and a low elastic modulus in order to prevent cracks in the semiconductor chip 104 and die bonding material such as solder. When the main component of the semiconductor chip is Si, it is better that the thermal expansion coefficient of the first resin layer 55A is closer to 21 ppm / ° C. Further, a resin having a value close to the thermal expansion coefficient of the wire may be used to prevent the wire from being deformed or peeled off. In that case, it is preferable to use a resin having a value close to the thermal expansion coefficient of Al (23 ppm / ° C.), Cu (17 ppm / ° C.), or Au (14.2 ppm / ° C.). Further, it is preferable to add silicone to the first resin layer 55A in order to lower the elastic modulus.

第２樹脂層５５Ｂは不純物イオンを捕獲するゲッタリング部３５を備える。ゲッタリング部３５は誘電剤、強誘電剤のような分極剤、イオントラップ添加剤などのイオントラップ材料で樹脂内に形成されており、フレームに近づくほどイオントラップ材料の量は多くなっているのが好ましい。一般的にハロゲンフリー樹脂はガラス転移点温度Ｔｇが低い。さらに高温で半導体装置を使用した場合、Ｔｇを超えると、樹脂の弾性率は急激に低下し、樹脂は柔らかくなり、材料間の密着性は低下する。界面間に存在する不純物イオンは柔らかくなった樹脂界面を移動しやすくなる。しかしながら、フレーム２０４と樹脂との界面に近づくほど、ゲッタリング部３５を構成するイオントラップ材料の量は多くすることで、界面間に存在する不純物イオンの移動を抑制することができる。 The second resin layer 55B includes a gettering portion 35 that captures impurity ions. The gettering portion 35 is formed in the resin with a dielectric agent, a polarizing agent such as a ferroelectric agent, or an ion trap material such as an ion trap additive, and the amount of the ion trap material increases as it approaches the frame. Is preferred. Generally, a halogen-free resin has a low glass transition temperature Tg. Further, when the semiconductor device is used at a high temperature, if the Tg is exceeded, the elastic modulus of the resin is drastically lowered, the resin is softened, and the adhesion between the materials is lowered. Impurity ions existing between the interfaces easily move on the softened resin interface. However, the closer to the interface between the frame 204 and the resin, the larger the amount of the ion trap material constituting the gettering portion 35, thereby suppressing the movement of impurity ions existing between the interfaces.

第３樹脂層５５Ｃは第１樹脂層５５Ａ、第２樹脂層５５Ｂに比べて高密度、高密着の樹脂を使用する。また、樹脂をモールドするための金型に密着して残らない離散性の良い離形剤を含む樹脂が好ましい。 The third resin layer 55C uses a resin having higher density and higher adhesion than the first resin layer 55A and the second resin layer 55B. Further, a resin containing a release agent with good discreteness that does not remain in close contact with a mold for molding the resin is preferable.

図１１は３層の封止用の樹脂タブレット５５の斜視図である。 FIG. 11 is a perspective view of a three-layer sealing resin tablet 55.

本実施形態に係る封止用の樹脂タブレット５５は、円柱状、角柱状または錠剤状であり、下から第１樹脂層５５Ａ、第２樹脂層５５Ｂ、第３樹脂層５５Ｃの順に形成されている。上記のような複層構造のタブレットを使用することにより、別々の樹脂タブレットを使用するのに比べ、充填効率をあげ時間を短縮することができる。また１００Ｖ以上の高耐圧品では、表面放電を防止するために絶縁のコーティング剤で半導体チップを覆うことが好ましい。その場合、封止用の樹脂タブレットは、下からコーティング剤、第１樹脂層５５Ａ、第２樹脂層５５Ｂ、第３樹脂層５５Ｃの順に形成される。上記のようなタブレットを使用することにより、単一の工程でコーティングと樹脂封止が完了するため、コスト低減が期待できる。 The sealing resin tablet 55 according to the present embodiment has a cylindrical shape, a prismatic shape, or a tablet shape, and is formed from the bottom in the order of the first resin layer 55A, the second resin layer 55B, and the third resin layer 55C. . By using a tablet having a multilayer structure as described above, the filling efficiency can be increased and the time can be shortened compared to the use of separate resin tablets. Further, in a high voltage product having a voltage of 100 V or higher, it is preferable to cover the semiconductor chip with an insulating coating agent in order to prevent surface discharge. In that case, the sealing resin tablet is formed in the order of the coating agent, the first resin layer 55A, the second resin layer 55B, and the third resin layer 55C from the bottom. By using the tablet as described above, coating and resin sealing are completed in a single step, and therefore cost reduction can be expected.

図１２は半導体装置Ａ５製造するための樹脂成形装置である。本装置は、樹脂タブレットが供給されるポット部４１、樹脂タブレット５５の樹脂が成型されるキャビティ部４２、ポット部４１とキャビティ部４２とを連通するランナ部４３、およびプランジャ４４を備える。本装置の特徴は樹脂が半導体チップ１０４の真上から注入されるようにランナ部４３の位置を半導体チップ１０４の真上に調節したことである。上記の方法では上から下に樹脂を充填するため、従来の横方向からの充填に比べて、未充填部分が発生するのを防ぐことができる。また、ランナの長さを等しくし、樹脂タブレット５５が供給されるポット部４１から半導体チップ１０４までの距離を等しくするのが好ましい。 FIG. 12 shows a resin molding apparatus for manufacturing the semiconductor device A5. The apparatus includes a pot portion 41 to which a resin tablet is supplied, a cavity portion 42 in which the resin of the resin tablet 55 is molded, a runner portion 43 that communicates the pot portion 41 and the cavity portion 42, and a plunger 44. The feature of this apparatus is that the position of the runner portion 43 is adjusted to be directly above the semiconductor chip 104 so that the resin is injected from directly above the semiconductor chip 104. In the above method, since the resin is filled from the top to the bottom, it is possible to prevent an unfilled portion from occurring as compared with the conventional filling from the lateral direction. Further, it is preferable that the runners have the same length, and the distance from the pot portion 41 to which the resin tablet 55 is supplied to the semiconductor chip 104 is made equal.

本実施例においてはゲッタリング部３５を第２樹脂層５５Ｂに形成したが、第１樹脂層５５Ａ、第３樹脂層５５Ｃに形成してもよいし、第１樹脂層５５Ａないし第３樹脂層５５Ｃとフレーム２０４との界面に形成しても良い。また本実施例においては樹脂層を３層で形成したが、これに限定されるものでなく、３層以上でも３層以下でもよい。 In this embodiment, the gettering portion 35 is formed in the second resin layer 55B, but it may be formed in the first resin layer 55A and the third resin layer 55C, or the first resin layer 55A to the third resin layer 55C. And the frame 204 may be formed at the interface. In this embodiment, the resin layer is formed of three layers, but is not limited to this, and may be three or more layers or three layers or less.

（第６実施形態） 図１３は、本発明に係る半導体装置の第６実施形態を平面図で示している。図１３に示す半導体装置Ａ６は、半導体チップ１０５、フレーム２０５、ゲッタリング部３６、第１インナーリード８２、第２インナーリード９２および樹脂パッケージ５６を備える。 Sixth Embodiment FIG. 13 is a plan view showing a sixth embodiment of a semiconductor device according to the present invention. A semiconductor device A6 shown in FIG. 13 includes a semiconductor chip 105, a frame 205, a gettering portion 36, a first inner lead 82, a second inner lead 92, and a resin package 56.

半導体チップ１は、たとえば、一方の面にゲート電極１Ｄ、ソース電極１Ｅ、他方の面にドレイン電極１Ｆが形成された縦型ＭＯＳＦＥＴである。ドレイン１Ｆ電極は導電性のハンダを介してフレーム２０５と接続している。ゲート電極１Ｄはワイヤを介して第１インナーリード８２と接続している。ソース電極１Ｅもワイヤを介して第２インナーリード９２と接続している。 The semiconductor chip 1 is, for example, a vertical MOSFET in which a gate electrode 1D and a source electrode 1E are formed on one surface, and a drain electrode 1F is formed on the other surface. The drain 1F electrode is connected to the frame 205 through conductive solder. The gate electrode 1D is connected to the first inner lead 82 via a wire. The source electrode 1E is also connected to the second inner lead 92 via a wire.

ソース電極１Ｅと第２インナーリード９２との間に形成された複数本のワイヤがゲッタリング部３６として機能する。ワイヤは、たとえばＡｌが用いられる。また、ワイヤは必ずしも複数ある必要はなく、ゲート電極１Ｄと第１インナーリード８２と接続しているワイヤよりも幅の広いワイヤを用いても良い。 A plurality of wires formed between the source electrode 1E and the second inner lead 92 function as the gettering portion 36. For example, Al is used for the wire. There is not necessarily a plurality of wires, and a wire wider than the wire connected to the gate electrode 1D and the first inner lead 82 may be used.

このような半導体装置Ａ６では、ワイヤの本数を増やすこと、あるいはワイヤの幅を変えることで電界集中が起こるのを緩和することができる。また、ワイヤの抵抗が大幅に低減されるため、半導体チップ１０５全体としての抵抗を減らすことができる。 In such a semiconductor device A6, it is possible to reduce the occurrence of electric field concentration by increasing the number of wires or changing the width of the wires. Further, since the resistance of the wire is greatly reduced, the resistance of the entire semiconductor chip 105 can be reduced.

ゲッタリング部３６として機能するワイヤはソース電極１Ｅに接続するように設けたが、それに限定されるものではない。また、ＭＯＳＦ
ＥＴに限定されるものではなく、ＩＧＢＴ、パワーＩＣ等にも適用することができる。 Although the wire functioning as the gettering portion 36 is provided so as to be connected to the source electrode 1E, it is not limited thereto. MOSF
The present invention is not limited to ET, and can also be applied to IGBTs, power ICs, and the like.

（第７実施形態） 図１４は、本発明に係る半導体装置の第７実施形態を平面図で示している。図１５には、図１４のXV-XV線に沿う断面図を示している。図１４および図１５に示す電子デバイスＡ７は、半導体チップ１０６、フレーム２０６、ゲッタリング部３７、第１インナーリード８３、第２インナーリード９３、第１金属ストラップ８４、第２金属ストラップ９４、樹脂パッケージ５７を備える。 Seventh Embodiment FIG. 14 is a plan view showing a seventh embodiment of a semiconductor device according to the present invention. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14 and 15 includes a semiconductor chip 106, a frame 206, a gettering portion 37, a first inner lead 83, a second inner lead 93, a first metal strap 84, a second metal strap 94, and a resin package. 57.

半導体チップ１０６は、たとえば、一方の面にゲート電極１Ｇ、ソース電極１Ｈ、他方の面にドレイン電極１Ｉが形成されたＭＯＳＦＥＴである。ドレイン電極１Ｉはフレーム２０６と接続している。ゲート電極１Ｇは第１金属ストラップ８４を介して第１インナーリード８３と接続している。ソース電極１Ｈは第２金属ストラップ９４介して第２インナーリード９３と接続している。 The semiconductor chip 106 is, for example, a MOSFET having a gate electrode 1G and a source electrode 1H formed on one surface and a drain electrode 1I formed on the other surface. The drain electrode 1I is connected to the frame 206. The gate electrode 1G is connected to the first inner lead 83 via the first metal strap 84. The source electrode 1H is connected to the second inner lead 93 through the second metal strap 94.

第１金属ストラップ８４、第２金属ストラップ９４はたとえば、Ｃｕ、Ａｌなどの金属プレートが用いられる。通常のワイヤに比べて熱伝導経路の断面積が大きく、熱抵抗が小さいものが好ましい。第１金属ストラップ８４、第２金属ストラップ９４は半導体チップ１の上面電極（ゲート電極１Ｇ、ソース電極１Ｈ）と接続する接続部と、電子部品の厚み方向Ｚに屈曲または湾曲して形成された傾斜部と、フレーム２に沿って伸びるように形成された足部とを備える。前記足部とフレーム２０６とは絶縁されている。前記接続部と、前記足部とは直交する方向に伸びているのが好ましい。 For the first metal strap 84 and the second metal strap 94, for example, a metal plate such as Cu or Al is used. It is preferable that the heat conduction path has a larger cross-sectional area and a smaller thermal resistance than a normal wire. The first metal strap 84 and the second metal strap 94 are connected to the upper surface electrodes (gate electrode 1G and source electrode 1H) of the semiconductor chip 1 and inclined formed by bending or bending in the thickness direction Z of the electronic component. And a foot portion formed so as to extend along the frame 2. The feet and the frame 206 are insulated. It is preferable that the connection portion and the foot portion extend in a direction orthogonal to each other.

第１金属ストラップ８４、第２金属ストラップ９４には凹凸等が形成された表面粗さの異なる部分が存在し、ゲッタリング部３７として機能する。前記ゲッタリング部３７は少なくともフレーム２０６に沿って伸びるように形成された足部もしくは傾斜部に設けるのが好ましい。 The first metal strap 84 and the second metal strap 94 have a portion with unevenness on which irregularities and the like are formed, and function as the gettering portion 37. The gettering portion 37 is preferably provided on a foot portion or an inclined portion formed so as to extend along at least the frame 206.

このような半導体装置Ａ７では、金属ストラップに凹凸等が形成された表面粗さの異なる部分が存在するため、不純物イオンを捕獲しリークパスを長くすることができる。 In such a semiconductor device A7, since there are portions having different surface roughnesses where unevenness or the like is formed on the metal strap, it is possible to capture impurity ions and lengthen the leak path.

（その他の実施形態） 上記のように、本発明は第１〜第７実施形態によって記載したが、この開示の一部をなす論述および図面はこの発明を限定するものではない。この開示から当業者には様々な代替実施の形態、実施例および運用技術が明らかとなろう。 (Other embodiment) As mentioned above, although this invention was described by 1st-7th embodiment, the description and drawing which make a part of this indication do not limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

たとえば、本発明では半導体チップの例としてパワーＭＯＳＦＥＴを説明したが、それに限定されるものではなく、バイポーラトランジスタや半導体集積回路（パワーＩＣ）等の半導体、コンデンサ等の電子部品、モジュール、プリント基板の設計などに適用することができる。 For example, in the present invention, a power MOSFET has been described as an example of a semiconductor chip. However, the present invention is not limited thereto. Semiconductors such as bipolar transistors and semiconductor integrated circuits (power ICs), electronic components such as capacitors, modules, and printed circuit boards It can be applied to design etc.

また、半導体装置もしくは半導体チップを多数実装したプリント基板をハロゲンフリー樹脂で封止したモジュール製品にも適用することができる。半導体チップの外側に、高電界もしくは低電位のゲッタリング部を設けることで、不純物イオンが電子部品に引き寄せられるのを防ぐことができる。 The present invention can also be applied to a module product in which a printed circuit board on which a large number of semiconductor devices or semiconductor chips are mounted is sealed with a halogen-free resin. By providing a gettering portion having a high electric field or a low potential outside the semiconductor chip, impurity ions can be prevented from being attracted to the electronic component.

このように、本発明はここでは記載していない様々な実施の形態などを含むことは勿論である。したがって、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。 As described above, the present invention naturally includes various embodiments that are not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

本発明の第１実施形態に係る半導体装置の一例を示す平面図である。1 is a plan view showing an example of a semiconductor device according to a first embodiment of the present invention. 図１のII-II線に沿う断面図である。It is sectional drawing which follows the II-II line of FIG. 本発明の第１実施形態に係る半導体チップの一例であるＭＯＳＦＥＴの構造の断面図である。It is sectional drawing of the structure of MOSFET which is an example of the semiconductor chip concerning 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第２実施形態に係る半導体装置の一例を示す平面図である。It is a top view which shows an example of the semiconductor device which concerns on 2nd Embodiment of this invention. 図５のIV-IV線に沿う断面図である。It is sectional drawing which follows the IV-IV line of FIG. 本発明の第３実施形態に係る半導体装置の一例を示す平面図である。It is a top view which shows an example of the semiconductor device which concerns on 3rd Embodiment of this invention. 図７のVIII-VIII線に沿う断面図である。It is sectional drawing which follows the VIII-VIII line of FIG. 本発明の第４実施形態に係る半導体装置の一例を示す平面図である。It is a top view which shows an example of the semiconductor device which concerns on 4th Embodiment of this invention. 本発明の第５実施形態に係る半導体装置の一例を示す断面図である。It is sectional drawing which shows an example of the semiconductor device which concerns on 5th Embodiment of this invention. 本発明の第５実施形態に係る半導体装置用の樹脂タブレットの一例を示す斜視図である。It is a perspective view which shows an example of the resin tablet for semiconductor devices which concerns on 5th Embodiment of this invention. 本発明の第５実施形態に係る半導体装置を製造するための樹脂成型装置の一例を示す断面図である。It is sectional drawing which shows an example of the resin molding apparatus for manufacturing the semiconductor device which concerns on 5th Embodiment of this invention. 本発明の第６実施形態に係る半導体装置の一例を示す平面図である。It is a top view which shows an example of the semiconductor device which concerns on 6th Embodiment of this invention. 本発明の第７実施形態に係る半導体装置の一例を示す平面図である。It is a top view which shows an example of the semiconductor device which concerns on 7th Embodiment of this invention. 図１４のXV-XV線に沿う断面図である。It is sectional drawing which follows the XV-XV line | wire of FIG.

符号の説明Explanation of symbols

Ａ１，Ａ２〜Ａ７ 半導体装置１，１０１〜１０６ 半導体チップ２，２０１〜２０６ フレーム３，３１〜３７ ゲッタリング部４ ハンダ層５，５２〜５７ 樹脂パッケージ６ メッキ７ 突起８，８２，８３ 第１インナーリード９，９２，９３ 第２インナーリード A1, A2-A7 Semiconductor device 1, 101-106 Semiconductor chip 2, 201-206 Frame 3, 31-37 Gettering part 4 Solder layer 5, 52-57 Resin package 6 Plating 7 Protrusion 8, 82, 83 First inner Lead 9, 92, 93 Second inner lead

Claims (17)

半導体チップと、
前記半導体チップを搭載するフレームもしくは基板と、
前記半導体チップを封止するハロゲンフリー樹脂と、
前記半導体チップの周辺に不純物イオンを捕獲するゲッタリング部と
を有することを特徴とする半導体装置。 A semiconductor chip;
A frame or substrate on which the semiconductor chip is mounted;
A halogen-free resin for sealing the semiconductor chip;
A semiconductor device comprising: a gettering portion that captures impurity ions around the semiconductor chip. 前記ハロゲンフリー樹脂は実質的にハロゲン系難燃剤を含まないことを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the halogen-free resin does not substantially contain a halogen-based flame retardant. 前記ハロゲンフリー樹脂は金属水和物系難燃剤、リン系難燃剤の少なくとも一方を含むことを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the halogen-free resin includes at least one of a metal hydrate flame retardant and a phosphorus flame retardant. 前記ハロゲンフリー樹脂は実質的に難燃剤を含まないことを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the halogen-free resin does not substantially contain a flame retardant. 前記ハロゲンフリー樹脂は実質的に原材料にハロゲン化合物及びアンチモン化合物を含まないことを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the halogen-free resin does not substantially contain a halogen compound and an antimony compound as raw materials. 前記ハロゲンフリー樹脂は（１）塩素の含有率が０．０９ｗｔ％以下、（２）臭素の含有率が０．０９ｗｔ％以下、（３）アンチモンの含有率が０．０９ｗｔ％以下の基準を満たしていることを特徴とする請求項５に記載の半導体装置。 The halogen-free resin satisfies the criteria of (1) chlorine content of 0.09 wt% or less, (2) bromine content of 0.09 wt% or less, and (3) antimony content of 0.09 wt% or less. 6. The semiconductor device according to claim 5, wherein: 前記ハロゲンフリー樹脂は塩素の含有量が臭素の含有量より大きいことを特徴とする請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the halogen-free resin has a chlorine content greater than a bromine content. 前記フレームもしくは基板と前記樹脂との界面に前記ゲッタリング部が形成されていることを特徴とする請求項１〜７いずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the gettering portion is formed at an interface between the frame or the substrate and the resin. 前記フレームもしくは基板には前記半導体チップを搭載する領域の周辺に凹部が設けられており、前記ゲッタリング部は前記凹部内に形成されていることを特徴とする請求項１〜８いずれか１項に記載の半導体装置。 9. The frame or the substrate is provided with a recess around a region where the semiconductor chip is mounted, and the gettering portion is formed in the recess. A semiconductor device according to 1. 前記フレームもしくは基板には前記半導体チップを搭載する領域の周辺に複数の凸部が設けられており、前記ゲッタリング部は前記凸部に近接して設けられていることを特徴とする請求項１〜８いずれか１項に記載の半導体装置。 2. The frame or the substrate is provided with a plurality of convex portions around a region where the semiconductor chip is mounted, and the gettering portion is provided close to the convex portion. The semiconductor device according to any one of? 8. 前記ゲッタリング部は前記フレームもしくは基板の前記半導体チップを搭載する領域の周辺に設けられており、かつ前記ゲッタリング部が形成された領域は前記ゲッタリング部が形成されていない領域に比べてダングリングボンドが多いことを特徴とする請求項１〜８いずれか１項に記載の半導体装置。 The gettering portion is provided around a region of the frame or substrate where the semiconductor chip is mounted, and a region where the gettering portion is formed is dangling compared to a region where the gettering portion is not formed. The semiconductor device according to claim 1, wherein there are many ring bonds. 前記ゲッタリング部は前記フレームもしくは基板の前記半導体チップを搭載する領域の周辺に設けられた金属膜で形成されていることを特徴とする請求項１〜８いずれか１項に記載の半導体装置。 9. The semiconductor device according to claim 1, wherein the gettering portion is formed of a metal film provided around a region of the frame or the substrate on which the semiconductor chip is mounted. 前記ゲッタリング部は前記フレームもしくは基板の前記半導体チップを搭載する領域の周辺に設けられた金属膜で形成され、かつ前記配線は電流を流し磁界を発生させていることを特徴とする請求項１〜８いずれか１項に記載の半導体装置。 2. The gettering portion is formed of a metal film provided around a region of the frame or substrate where the semiconductor chip is mounted, and the wiring passes a current to generate a magnetic field. The semiconductor device according to any one of? 8. 前記ゲッタリング部は前記樹脂内部にイオントラップ材料を添加することで形成されており、
前記イオントラップ材料は前記フレームもしくは基板と前記樹脂の界面に近づくほど多く添加されていることを特徴とする請求項１〜８いずれか１項に記載の半導体装置。 The gettering portion is formed by adding an ion trap material inside the resin,
9. The semiconductor device according to claim 1, wherein the ion trap material is added in a larger amount as it approaches the interface between the frame or the substrate and the resin. 前記ゲッタリング部は前記樹脂内部にイオントラップ材料を添加することで形成されており、
前記樹脂は前記半導体チップを包囲する第１の樹脂と、前記第１の樹脂の外側に設けられた第２の樹脂とを有し、少なくとも前記第２の樹脂内に前記イオントラップ材料が添加されていることを特徴とする請求項１〜８いずれか１項に記載の半導体装置。 The gettering portion is formed by adding an ion trap material inside the resin,
The resin has a first resin surrounding the semiconductor chip and a second resin provided outside the first resin, and at least the ion trap material is added into the second resin. The semiconductor device according to claim 1, wherein the semiconductor device is provided. 複数本のインナーリードと、
前記インナーリードと前記半導体チップとを電気的に接続する接続部と、をさらに有し、
前記ゲッタリング部は前記接続部に形成されていることを特徴とする請求項１〜８いずれか１項に記載の半導体装置。 Multiple inner leads,
A connection portion for electrically connecting the inner lead and the semiconductor chip;
The semiconductor device according to claim 1, wherein the gettering portion is formed in the connection portion. 前記ゲッタリング部は分極材料を含んでいることを特徴とする請求項１〜８いずれか１項に記載の半導体装置。
The semiconductor device according to claim 1, wherein the gettering unit includes a polarization material.
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JP2003101075A (en) * 2001-08-23 2003-04-04 Lumileds Lighting Us Llc Reduction of contamination in light-emitting device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62198130A (en) * 1986-02-26 1987-09-01 Sumitomo Bakelite Co Ltd Manufacture of semiconductor device
JPS63110737A (en) * 1986-10-29 1988-05-16 Sony Corp Manufacture of semiconductor device
JPS63193537A (en) * 1987-02-06 1988-08-10 Hitachi Ltd Manufacture of semiconductor device
JPH04221842A (en) * 1990-12-25 1992-08-12 Fujitsu Ltd Semiconductor device and manufacture thereof
JPH07116870A (en) * 1993-10-26 1995-05-09 Matsushita Electric Works Ltd Processing method for surface of base material
JPH09326396A (en) * 1996-06-04 1997-12-16 Hitachi Ltd Semiconductor integrated circuit device and its manufacture
JP2003101075A (en) * 2001-08-23 2003-04-04 Lumileds Lighting Us Llc Reduction of contamination in light-emitting device
JP2006041100A (en) * 2004-07-26 2006-02-09 Hitachi Ltd Wiring board for power ic
JP2007009166A (en) * 2005-06-03 2007-01-18 Hitachi Chem Co Ltd Epoxy resin composition for sealing, and electronic component apparatus
JP2007099996A (en) * 2005-10-06 2007-04-19 Kyocera Chemical Corp Sealing resin composition and sealing device for semiconductor

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