JP2010086983A - リードフレーム型基板の製造方法と半導体装置 - Google Patents
リードフレーム型基板の製造方法と半導体装置 Download PDFInfo
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- JP2010086983A JP2010086983A JP2008250860A JP2008250860A JP2010086983A JP 2010086983 A JP2010086983 A JP 2010086983A JP 2008250860 A JP2008250860 A JP 2008250860A JP 2008250860 A JP2008250860 A JP 2008250860A JP 2010086983 A JP2010086983 A JP 2010086983A
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- lead frame
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Abstract
【解決手段】イ)金属板の第1と第2の面に感光性レジストをコート又はドライフィルムを貼付し、ロ)パターン露光と現像により接続用ポストと配線パターンを形成する各レジストパターンを設け、ハ)第1面を中途エッチングし接続用ポストを形成し、ニ)その面が埋没するまでプリモールド用樹脂を充填し、ホ)接続用ポスト底面が露出する迄プリモールド用樹脂を均一に除去し、ヘ)第2面のエッチングにより配線パターンを形成する。
【選択図】図1
Description
このインターポーザの一方の面に、半導体素子を実装し、他方の面もしくは基板の周辺でプリント基板との接続がとられる。インターポーザは内部もしくは表面に金属リードフレームを有しており、リードフレームにより電気的接続経路を引き回して、プリント基板との接続を行う外部接続端子のピッチを拡張している。
図2(a)に示すように、アルミニウムあるいは銅からなるリードフレームの中央部に半導体素子22を搭載する平坦部分21を設け、外周部にピッチの広いリード23を配設したもので、リード23と半導体素子の電気的接続用端子との接続には、金線などのメタルワイヤー24によるボンディング法を使用したものである。図2(b)に示すように、最終的には全体を樹脂でモールド25して一体化する。
しかし、図2のインターポーザでは、電気的接続が半導体素子の外周部とリードフレームの外周部とでしか行えないため、端子数が多い半導体素子には不向きといえる。
面積が狭く端子数が多い半導体素子の場合には、半導体素子の接続端子は、半導体素子の底面にアレイ状に配置して形成されることが多い。そのため、インターポーザ側の外部接続端子も同一なアレイ状の配置として、インターポーザとプリント基板との接続には微少な半田ボールを用いるフリップチップ接続方式が採用される。インターポーザ内の配線は、上部から垂直方向にドリルもしくはレーザーで窄孔し、孔内に金属めっきを行うことにより、上下の電気的銅通がとられる。
しかし、この方式によるインターポーザでは、外部接続端子のピッチは150〜200μm程度まで微細化できるため、接続端子数を増やすことはできるが、接合の信頼性や安定性は低下し、高い信頼性が要求される車載用などには向いていない。
いずれの場合であっても、半導体素子の小型化、多ピン化、高速化に対応して、インターポーザの半導体素子のとの接続部分のファインピッチ化及び高速信号対応が進んでいる。微細化の進展を考慮すると、端子部分のピッチは80〜100μmが必要である。
この点について、図2を用いて説明する。
しかし、最終的には、保持材27は不要であるため、モールド加工をした後に、取り外して棄てることになり、コストアップに繋がる。
この一対策は、リードフレーム型基板を製造するうえで、金属板の第1の面には接続用ポスト形成用のレジストパターン、第2の面には配線パターン形成用のレジストパターンを形成し、第1の面の上から銅を所望の厚さまでエッチングしたのち、第1の面にプリモールド用樹脂を塗布しプリモールド層を形成し、その後に、第2の面のエッチングを行い配線を形成して、その後に両面のレジストを剥離するということになる。
即ち、上記の一対策において、金属板の厚さ方向途中までエッチングした面にプリモールド樹脂を塗布する工程は技術的に困難である。塗付の厚さは、リードフレームに必要な剛性を与えるのに十分な程度必要であり、なおかつ、接続用ポストの底面は、完全に露出していなければならない。
また、表面張力のために、樹脂が球状になって、狭い範囲にとどまる場合もあり、その場合は注入した樹脂が少量であっても、高さが大きくなり、接続用ポストの底面に達してしまう不良も発生しやすいと云う問題も心配される。
それから、ディスペンサー等の装置を用いて、塗付面底に複数の注入箇所を設定することも考えられるが、やはりプリモールド樹脂の粘性のために、ある注入箇所から他の箇所に移動する間に、樹脂が糸をひき、それが接続用ポストの底面に付着するという不良も発生しやすいと云う問題も心配される。
(ロ)前記第1の面と第2の面に、前記感光性レジストまたは前記ドライフィルムにパターン露光を行った後に現像することで、該第1の面には接続用ポスト形成用のレジストパターンを、又、該第2の面には配線パターン形成用のレジストパターンを形成し、
(ハ)前記第1の面の側を、前記金属板の中途までエッチングを行い、前記接続用ポストを形成し、
(ニ)前記第1の面の側に、プリモールド用の樹脂を、該エッチングが成された面が埋没する厚さまで充填し、
(ホ)前記プリモールド用の樹脂を、前記接続用ポストの底面が露出するまで、厚さ方向に均一に除去し、
(ヘ)その後、前記第2の面の側をエッチングすることで配線パターンを形成する、
以上を経ることを特徴とするリードフレーム型基板の製造方法である。
これにより、プリモールド樹脂の上面の高さは、接続用ポストの底面とほぼ同じ高さとなり、リードフレーム型基板の剛性を保ち、なおかつ接続用ポスト底面が完全に露出するという目標を、確実に達成することができる。
これにより、液状樹脂を用いるよりも、簡便に所望のリードフレーム型基板を製造することができる。
これにより、プリモールド樹脂を充填する際の、気泡等の発生を低減することができ、より高品質なリードフレーム型基板を製造することができる。
プリモールド樹脂のこの高さは、リードフレーム型基板の支持体として、十分な剛性をもち、なおかつ、接続用ポストが、完全に露出するという条件を兼ね備えている。そのため、十分な機械的強度をもち、なおかつ接続においても高い信頼性をもつ接合強度を得られる。
製造した個々の単位のLGAのサイズは10mm角で、168ピンの平面視でアレイ状の外部接続部をもつもので、基板に多面付けして、以下の製造工程を経た後に切断、断裁を行い、個々のLGAタイプのリードフレーム型基板を得た。
次いで、図1(b)に示すように、銅基板1の両面ロールコーターで感光性レジスト2(東京応化(株)製、OFPR4000)を5μmの厚さになるようにコーティングした後、90℃でプリベークをした。
次に、所望のパターンを有するパターン露光用フォトマスクを介して、両面からパターン露光し、その後1%水酸化ナトリウム溶液で現像処理を行った後に、水洗およびポストベークを行い、図1(c)に示すようにレジストパターン3を得た。なお、銅基板の一方の面側(半導体素子が搭載される面とは反対側の面であり、本実施例では以下、第1の面側と記す)には、接続用ポストを形成するためのレジストパターンを形成し、他方の面側(半導体素子が搭載される面であり、本実施例では以下、第2の面側と記す)には、配線パターンを形成するためのレジストパターンを形成した。
この他、半導体素子10の周囲のランド4のうち幾つかを、半導体素子の下面に位置する接続用ポスト5に電気的に接続させる必要がある。そのため、半導体素子10周辺のランド4の幾つかと各々接続した配線パターン6を半導体素子下面に位置する接続用ポスト5と接続するよう基板の外周から中心方向に向けて、例えば、放射状に、形成している(図示せず)。
塩化第二鉄溶液の比重は1.38、液温50℃とした。第1回目のエッチングの際、接続用ポスト形成用のレジストパターンが形成された部位の銅基板には、エッチング処理が行われない。そのため、銅基板の厚み方向に、第1回目のエッチング処理で形成されたエッチング面から銅基板下側面までの高さを有して延在する、プリント基板との外部接続を可能とした接続用ポストを形成することが出来る。
なお、第1回目のエッチングでは、エッチング処理を行う部位の銅基板をエッチング処理で完全に溶解除去するものではなく、所定の厚さの銅基板となった段階でエッチング処理を終了するよう、中途までエッチング処理を行う。
次に、第1の面に関して、20%水酸化ナトリウム水溶液によって、レジストの剥離を行った、剥離液の温度は100℃とた。
プレスに際しては、真空加圧式ラミネート装置を用い、プレス部の温度は100℃、真空チャンバー内の真空度は0.2torr、プレス時間は30秒にてフィルム樹脂のプレス加工を行った。
また、真空チャンバー内でのプレス加工を行うことは、樹脂内に生じた空隙を解消する効果があり、樹脂内のボイドの発生を抑えることができる。
その後に、図1(g)に示すように、第1の面を覆っている樹脂を、接続用ポストの底面が露出するまで研磨除去した。装置としては、バフロール回転式研磨装置を用い、バフロールの番手は、800番相当を使用した。
次いで、図1(h)に示すように、第2の面のレジストパターンの剥離を行い、所望のリードフレーム型LGA基板を得た。
次いで、面付けされた半導体基板に断裁を行い、個々の半導体基板を得た。
2 感光性レジスト
3 レジストパターン
4 ワイヤボンディング用ランド
5 接続用ポスト
6 配線パターン
7 下面
11 プリモールド層
12 めっき層
13 固定用接着剤
21 リードフレーム(平坦部)
10、22 半導体素子
23 リード
24 メタルワイヤー
25 モールド用樹脂
26 取り出し電極
27 保持材
Claims (5)
- (イ)金属板の第1の面と第2の面に、感光性レジストをコートするか、又はドライフィルムを貼付するかのいずれかを行い、
(ロ)前記第1の面と第2の面に、前記感光性レジストまたは前記ドライフィルムにパターン露光を行った後に現像することで、該第1の面には接続用ポスト形成用のレジストパターンを、又、該第2の面には配線パターン形成用のレジストパターンを形成し、
(ハ)前記第1の面の側を、前記金属板の中途までエッチングを行い、前記接続用ポストを形成し、
(ニ)前記第1の面の側に、プリモールド用の樹脂を、該エッチングが成された面が埋没する厚さまで充填し、
(ホ)前記プリモールド用の樹脂を、前記接続用ポストの底面が露出するまで、厚さ方向に均一に除去し、
(ヘ)その後、前記第2の面の側をエッチングすることで配線パターンを形成する、
以上を経ることを特徴とするリードフレーム型基板の製造方法。 - 前記プリモールド用の樹脂がフィルムタイプであること、を特徴とする請求項1に記載のリードフレーム型基板の製造方法。
- 前記プリモールド用の樹脂を充填する場合に、真空チャンバー内で該充填を行うこと、を特徴とする請求項1又は2のいずれかに記載のリードフレーム型基板の製造方法。
- 請求項1乃至3のいずれかに記載のリードフレーム型基板の製造方法によって得られた該リードフレーム型基板に、半導体が実装されており、該リードフレーム型基板と該半導体素子とがワイヤーボンディングにて電気的接続されていること、を特徴とする半導体基板。
- 金属板の第1の面に接続用ポストを有し、該金属板の第2の面に配線を有し、該接続用ポストと該配線と以外の領域がプリモールド用樹脂層で形成されたリードフレーム型基板であって、
該プリモールド樹脂の上面の高さが、接続用ポストの底面と同じ高さに成っていること、
を特徴とするリードフレーム型基板。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
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JP2008250860A JP5629969B2 (ja) | 2008-09-29 | 2008-09-29 | リードフレーム型基板の製造方法と半導体装置の製造方法 |
TW098132878A TWI521661B (zh) | 2008-09-29 | 2009-09-29 | 導線架基板之製造方法與半導體裝置 |
US12/998,099 US8546940B2 (en) | 2008-09-29 | 2009-09-29 | Manufacturing method of lead frame substrate and semiconductor apparatus |
CN200980137966.7A CN102165581B (zh) | 2008-09-29 | 2009-09-29 | 引线框基板的制造方法 |
KR1020117006757A KR20110081955A (ko) | 2008-09-29 | 2009-09-29 | 리드 프레임 기판의 제조 방법과 반도체 장치 |
KR1020167003070A KR101613828B1 (ko) | 2008-09-29 | 2009-09-29 | 리드 프레임 기판의 제조 방법 |
PCT/JP2009/004993 WO2010035509A1 (ja) | 2008-09-29 | 2009-09-29 | リードフレーム基板の製造方法と半導体装置 |
US14/038,114 US8703598B2 (en) | 2008-09-29 | 2013-09-26 | Manufacturing method of lead frame substrate |
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JP2014150182A (ja) * | 2013-02-01 | 2014-08-21 | Denso Corp | 半導体装置の製造方法 |
KR101637189B1 (ko) * | 2015-06-12 | 2016-07-20 | 주식회사 에스에프에이반도체 | 반도체 패키지 제조방법 |
WO2023101044A1 (ko) * | 2021-11-30 | 2023-06-08 | 해성디에스 주식회사 | 프리 몰드 기판 및 프리 몰드 기판의 제조 방법 |
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US10666578B2 (en) * | 2016-09-06 | 2020-05-26 | Taiwan Semiconductor Manufacturing Company Limited | Network-on-chip system and a method of generating the same |
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Publication number | Publication date |
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KR20110081955A (ko) | 2011-07-15 |
US8546940B2 (en) | 2013-10-01 |
WO2010035509A1 (ja) | 2010-04-01 |
CN102165581A (zh) | 2011-08-24 |
US20110169145A1 (en) | 2011-07-14 |
KR20160021304A (ko) | 2016-02-24 |
KR101613828B1 (ko) | 2016-04-19 |
TWI521661B (zh) | 2016-02-11 |
TW201019446A (en) | 2010-05-16 |
US20140021162A1 (en) | 2014-01-23 |
CN102165581B (zh) | 2015-12-16 |
JP5629969B2 (ja) | 2014-11-26 |
US8703598B2 (en) | 2014-04-22 |
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