JP2010073893A5 - - Google Patents

Download PDF

Info

Publication number
JP2010073893A5
JP2010073893A5 JP2008239751A JP2008239751A JP2010073893A5 JP 2010073893 A5 JP2010073893 A5 JP 2010073893A5 JP 2008239751 A JP2008239751 A JP 2008239751A JP 2008239751 A JP2008239751 A JP 2008239751A JP 2010073893 A5 JP2010073893 A5 JP 2010073893A5
Authority
JP
Japan
Prior art keywords
semiconductor element
lead frame
opening
lead
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008239751A
Other languages
Japanese (ja)
Other versions
JP5207896B2 (en
JP2010073893A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2008239751A priority Critical patent/JP5207896B2/en
Priority claimed from JP2008239751A external-priority patent/JP5207896B2/en
Publication of JP2010073893A publication Critical patent/JP2010073893A/en
Publication of JP2010073893A5 publication Critical patent/JP2010073893A5/ja
Application granted granted Critical
Publication of JP5207896B2 publication Critical patent/JP5207896B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Claims (10)

開口部を有し、該開口部の周囲にリード部が櫛歯状に延在するように成形されたリードフレームと、
前記リードフレームの開口部に、フェイスダウンの態様で配置された第１の半導体素子と、
前記第１の半導体素子上にフェイスアップの態様で搭載され、その電極パッドがワイヤを介して前記リードフレームのリード部に接続された第２の半導体素子と、
前記第１の半導体素子及び前記リードフレームをその一面側に搭載する態様で設けられた積層配線層と、
前記積層配線層上の前記リードフレームと前記第１、第２の半導体素子及び前記ワイヤを埋め込むように形成された封止樹脂層とを備え、
前記積層配線層は、前記第１の半導体素子の電極パッド及び前記リードフレームのリード部からそれぞれひき出された配線パターンが、前記積層配線層の他面側に設けられるパッド部と電気的に繋がるようにそれぞれパターン形成された複数の配線層を含むことを特徴とする半導体装置。 A lead frame that has an opening and is shaped so that the lead portion extends in a comb shape around the opening;
A first semiconductor element disposed in a face-down manner at the opening of the lead frame;
A second semiconductor element mounted on the first semiconductor element in a face-up manner, and an electrode pad connected to the lead portion of the lead frame via a wire;
A laminated wiring layer provided in a mode in which the first semiconductor element and the lead frame are mounted on one surface side;
The lead frame on the laminated wiring layer, the first and second semiconductor elements, and a sealing resin layer formed to embed the wire,
In the laminated wiring layer, the wiring pattern drawn out from the electrode pad of the first semiconductor element and the lead portion of the lead frame is electrically connected to the pad portion provided on the other surface side of the laminated wiring layer. A semiconductor device comprising a plurality of wiring layers that are each patterned. 前記リードフレームの開口部は、前記第１の半導体素子が配置される第１の開口部と、その周囲にリード部が櫛歯状に延在するように成形された第２の開口部とを有し、
前記第２の半導体素子は、前記第１の半導体素子より大きいサイズを有し、その周辺部分が前記第１、第２の開口部間のリードフレーム部分で支持された構造を有することを特徴とする請求項１に記載の半導体装置。 The opening portion of the lead frame includes a first opening portion in which the first semiconductor element is disposed and a second opening portion formed so that the lead portion extends in a comb shape around the opening portion. Have
The second semiconductor element has a size larger than that of the first semiconductor element, and a peripheral portion thereof is supported by a lead frame portion between the first and second openings. The semiconductor device according to claim 1. 前記第２の半導体素子は、前記第１の半導体素子より大きいサイズを有し、その周辺部分が前記リードフレームの各リード部で支持された構造を有することを特徴とする請求項１に記載の半導体装置。   2. The device according to claim 1, wherein the second semiconductor element has a size larger than that of the first semiconductor element, and a peripheral portion of the second semiconductor element is supported by each lead portion of the lead frame. Semiconductor device. 前記第１の半導体素子として複数個の半導体素子が、前記リードフレームの開口部に並設されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a plurality of semiconductor elements as the first semiconductor elements are arranged in parallel in the opening of the lead frame. 前記第１、第２の各半導体素子の厚さは、前記リードフレームのリード部の厚さと同じであることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein a thickness of each of the first and second semiconductor elements is the same as a thickness of a lead portion of the lead frame . 開口部を有し、該開口部の周囲にリード部が櫛歯状に延在するように成形されたリードフレームを、フィルム状の基材に貼り付けたものを用意する工程と、
前記基材上の、前記リードフレームの開口部に対応する部分に、第１の半導体素子をフェイスダウンの態様で搭載する工程と、
前記第１の半導体素子上に第２の半導体素子をフェイスアップの態様で搭載し、さらに該第２の半導体素子の電極パッドと前記リードフレームのリード部とをワイヤにより接続する工程と、
前記基材上の前記リードフレームと前記第１、第２の半導体素子及び前記ワイヤを埋め込むように封止樹脂で封止する工程と、
前記基材を除去する工程と、
前記第１の半導体素子の電極パッド及び前記リードフレームのリード部からそれぞれ配線パターンをひき出し、以降、所要の数の配線層を積層する工程であって、前記配線パターンが、積層後の配線層の露出する面側に設けられるパッド部と電気的に繋がるように各配線層を積層する工程とを含むことを特徴とする半導体装置の製造方法。 A step of preparing an adhesive film having a lead frame formed so that the lead portion extends in a comb-teeth shape around the opening, and having a film-like base material;
Mounting the first semiconductor element in a face-down manner on a portion of the base material corresponding to the opening of the lead frame;
Mounting the second semiconductor element on the first semiconductor element in a face-up manner, and further connecting the electrode pad of the second semiconductor element and the lead portion of the lead frame with a wire;
Sealing with a sealing resin so as to embed the lead frame on the substrate, the first and second semiconductor elements, and the wire;
Removing the substrate;
A wiring pattern is drawn out from the electrode pad of the first semiconductor element and the lead portion of the lead frame, and thereafter, a required number of wiring layers are laminated, and the wiring pattern is a wiring layer after lamination. And a step of laminating each wiring layer so as to be electrically connected to a pad portion provided on the exposed surface side of the semiconductor device. 前記リードフレームを前記基材に貼り付けたものを用意する工程において、前記リードフレームを、第１の半導体素子が配置される第１の開口部と、その周囲に前記リード部が櫛歯状に延在するように成形された第２の開口部とを有するように成形し、
前記第１の半導体素子上に前記第２の半導体素子を搭載し、さらに該第２の半導体素子の電極パッドと前記リードフレームのリード部とをワイヤにより接続する工程において、前記第１の半導体素子より大きいサイズを有した第２の半導体素子を、その周辺部分を前記第１、第２の開口部間のリードフレーム部分上に位置合わせして搭載することを特徴とする請求項６に記載の半導体装置の製造方法。 In the step of preparing a substrate in which the lead frame is bonded to the base material, the lead frame includes a first opening in which the first semiconductor element is disposed, and the lead portion in a comb shape around the first opening. A second opening shaped to extend, and
In the step of mounting the second semiconductor element on the first semiconductor element and further connecting the electrode pad of the second semiconductor element and the lead portion of the lead frame with a wire, the first semiconductor element a second semiconductor element having a larger size, according to claim 6, characterized in that mounted by aligning the peripheral portion thereof to the first, on the lead frame part between the second opening A method for manufacturing a semiconductor device. 前記第１の半導体素子上に前記第２の半導体素子を搭載し、さらに該第２の半導体素子の電極パッドと前記リードフレームのリード部とをワイヤにより接続する工程において、前記第１の半導体素子より大きいサイズを有した第２の半導体素子を、その周辺部分を前記リードフレームの各リード部上に位置合わせして搭載することを特徴とする請求項６に記載の半導体装置の製造方法。 In the step of mounting the second semiconductor element on the first semiconductor element and further connecting the electrode pad of the second semiconductor element and the lead portion of the lead frame with a wire, the first semiconductor element 7. The method of manufacturing a semiconductor device according to claim 6 , wherein a second semiconductor element having a larger size is mounted with its peripheral portion positioned on each lead portion of the lead frame. 前記第１の半導体素子を搭載する工程において、前記基材上の、前記リードフレームの開口部に対応する部分に、該第１の半導体素子として複数個の半導体素子を並設することを特徴とする請求項６に記載の半導体装置の製造方法。 In the step of mounting the first semiconductor element, a plurality of semiconductor elements are arranged side by side as the first semiconductor element in a portion corresponding to the opening of the lead frame on the base material. A method for manufacturing a semiconductor device according to claim 6 . 前記第１、第２の各半導体素子の厚さは、前記リードフレームのリード部の厚さと同じであることを特徴とする請求項６に記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein the thickness of each of the first and second semiconductor elements is the same as the thickness of the lead portion of the lead frame.
JP2008239751A 2008-09-18 2008-09-18 Semiconductor device and manufacturing method thereof Active JP5207896B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008239751A JP5207896B2 (en) 2008-09-18 2008-09-18 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008239751A JP5207896B2 (en) 2008-09-18 2008-09-18 Semiconductor device and manufacturing method thereof

Publications (3)

Publication Number Publication Date
JP2010073893A JP2010073893A (en) 2010-04-02
JP2010073893A5 true JP2010073893A5 (en) 2011-08-18
JP5207896B2 JP5207896B2 (en) 2013-06-12

Family

ID=42205410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008239751A Active JP5207896B2 (en) 2008-09-18 2008-09-18 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5207896B2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5100715B2 (en) * 2009-07-13 2012-12-19 株式会社東芝 Semiconductor device and manufacturing method of semiconductor device
KR101131447B1 (en) * 2010-10-05 2012-03-29 앰코 테크놀로지 코리아 주식회사 Method for manufacturing semiconductor package
KR101297015B1 (en) * 2011-11-03 2013-08-14 주식회사 네패스 Method of manufacturing fan-out semiconductor package using lead frame, semiconductor package thereof, and package on package thereof
JP5924110B2 (en) * 2012-05-11 2016-05-25 株式会社ソシオネクスト Semiconductor device, semiconductor device module, and semiconductor device manufacturing method
KR101999114B1 (en) * 2013-06-03 2019-07-11 에스케이하이닉스 주식회사 semiconductor package
US10074628B2 (en) 2013-10-04 2018-09-11 Mediatek Inc. System-in-package and fabrication method thereof
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
KR101809521B1 (en) * 2015-09-04 2017-12-18 주식회사 네패스 Semiconductor package and method of manufacturing the same
KR101819558B1 (en) * 2015-09-04 2018-01-18 주식회사 네패스 Semiconductor package and method of manufacturing the same
EP3151275A3 (en) * 2015-09-11 2017-04-19 MediaTek Inc. System-in-package and fabrication method thereof
KR101944007B1 (en) * 2015-12-16 2019-01-31 주식회사 네패스 Semiconductor package and method of manufacturing the same
JP7096741B2 (en) 2018-09-11 2022-07-06 株式会社東芝 Manufacturing method of semiconductor device
JP2023082375A (en) * 2021-12-02 2023-06-14 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and electronic apparatus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294722A (en) * 1999-04-01 2000-10-20 Nec Corp Laminated chip semiconductor device
JP3649064B2 (en) * 1999-11-10 2005-05-18 松下電器産業株式会社 Manufacturing method of semiconductor device
JP4321758B2 (en) * 2003-11-26 2009-08-26 カシオ計算機株式会社 Semiconductor device
JP5378643B2 (en) * 2006-09-29 2013-12-25 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and manufacturing method thereof
JP2008187203A (en) * 2008-04-25 2008-08-14 Sanyo Electric Co Ltd Method of manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
JP2010073893A5 (en)
JP2009252859A5 (en)
JP2009141041A5 (en)
JP2011119502A5 (en)
JP2011258772A5 (en)
JP2011142264A5 (en)
JP2009130104A5 (en)
JP2010278040A5 (en) Semiconductor device manufacturing method
JP2009055055A5 (en)
JP2014056925A5 (en)
JP2009289908A5 (en)
JP2013069807A5 (en)
JP2010153505A5 (en)
JP2011096903A5 (en) Semiconductor element mounted wiring board and method of manufacturing the same
JP2012054264A5 (en)
JP2011009514A5 (en)
JP2010153498A5 (en)
JP2014022618A5 (en)
JP2010015550A5 (en)
JP2014192386A5 (en)
JP2011222596A5 (en)
TWI429043B (en) Circuit board structure, packaging structure and method for making the same
JP2009246174A5 (en)
JP2009194189A5 (en)
JP2012069918A5 (en) Chip package build up method