JP2009194189A5 - - Google Patents
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- JP2009194189A5 JP2009194189A5 JP2008034089A JP2008034089A JP2009194189A5 JP 2009194189 A5 JP2009194189 A5 JP 2009194189A5 JP 2008034089 A JP2008034089 A JP 2008034089A JP 2008034089 A JP2008034089 A JP 2008034089A JP 2009194189 A5 JP2009194189 A5 JP 2009194189A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- main surface
- spacer
- pad
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims 23
- 238000004519 manufacturing process Methods 0.000 claims 8
- 239000011347 resin Substances 0.000 claims 3
- 229920005989 resin Polymers 0.000 claims 3
- 239000000463 material Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 210000001736 Capillaries Anatomy 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
Claims (7)
(a)上面、前記上面に形成された複数のリード電極、および前記上面とは反対側の下面を有する配線基板を準備する工程;(A) preparing a wiring board having an upper surface, a plurality of lead electrodes formed on the upper surface, and a lower surface opposite to the upper surface;
(b)第1主面、前記第1主面に形成された複数の第1パッド電極、および前記第1主面とは反対側の第1裏面を有する第1半導体チップを、前記第1裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面上に搭載する工程;(B) a first semiconductor chip having a first main surface, a plurality of first pad electrodes formed on the first main surface, and a first back surface opposite to the first main surface; A step of mounting on the upper surface of the wiring board such that is opposed to the upper surface of the wiring board;
(c)前記複数の第1パッド電極が露出するように、前記第1半導体チップの前記第1主面上にスペーサを搭載する工程;(C) mounting a spacer on the first main surface of the first semiconductor chip so that the plurality of first pad electrodes are exposed;
(d)前記第1半導体チップの前記複数の第1パッド電極と前記配線基板の前記複数のリード電極とを、複数の第1ワイヤを介してそれぞれ電気的に接続する工程;(D) electrically connecting the plurality of first pad electrodes of the first semiconductor chip and the plurality of lead electrodes of the wiring board via a plurality of first wires;
(e)第2主面、前記第2主面に形成された複数の第2パッド電極、および前記第2主面とは反対側の第2裏面を有する第2半導体チップを、前記第2裏面が前記スペーサと対向するように、前記スペーサ上に搭載する工程;(E) a second semiconductor chip having a second main surface, a plurality of second pad electrodes formed on the second main surface, and a second back surface opposite to the second main surface; Mounting on the spacer so as to face the spacer;
(f)前記第2半導体チップの前記複数の第2パッド電極と前記配線基板の前記複数のリード電極とを、複数の第2ワイヤを介してそれぞれ電気的に接続する工程;(F) electrically connecting the plurality of second pad electrodes of the second semiconductor chip and the plurality of lead electrodes of the wiring board via a plurality of second wires;
ここで、here,
前記複数の第1パッド電極は、前記配線基板の前記リード電極と電気的に接続されない未接続パッド電極を有しており、The plurality of first pad electrodes have unconnected pad electrodes that are not electrically connected to the lead electrodes of the wiring board,
前記(e)工程に先立って、前記未接続パッド電極上にダミーパターンを配置しておき、Prior to the step (e), a dummy pattern is disposed on the unconnected pad electrode,
前記(e)工程では、前記複数の第2パッド電極のうちの一つが前記ダミーパターン上に位置するように、前記第2半導体チップを前記スペーサ上に搭載する。In the step (e), the second semiconductor chip is mounted on the spacer so that one of the plurality of second pad electrodes is positioned on the dummy pattern.
前記(f)工程では、キャピラリで前記第2ワイヤの一部を前記第2パッド電極に押し付けることで、前記第2ワイヤと前記第2パッド電極とを接続することを特徴とする半導体装置の製造方法。In the step (f), the second wire and the second pad electrode are connected by pressing a part of the second wire against the second pad electrode with a capillary. Method.
前記(f)工程の後、前記第1半導体チップ、前記第2半導体チップ、前記スペーサ、前記複数の第1ワイヤおよび前記複数の第2ワイヤを樹脂で封止することを特徴とする半導体装置の製造方法。After the step (f), the first semiconductor chip, the second semiconductor chip, the spacer, the plurality of first wires, and the plurality of second wires are sealed with resin. Production method.
前記ダミーパターンは、前記第1ワイヤから成り、The dummy pattern consists of the first wire,
前記(d)工程において、前記ダミーパターンを前記未接続パッド電極に接合することを特徴とする半導体装置の製造方法。In the step (d), the dummy pattern is joined to the unconnected pad electrode.
前記ダミーパターンは、樹脂またはペースト材料から成り、The dummy pattern is made of resin or paste material,
前記(e)工程に先立って、前記未接続パッド電極上に前記樹脂または前記ペースト材料を塗布し、熱処理を施すことを特徴とする半導体装置の製造方法。Prior to the step (e), the resin or the paste material is applied onto the unconnected pad electrode, and a heat treatment is performed.
前記ダミーパターンは、前記スペーサの一部から成り、The dummy pattern consists of a part of the spacer,
前記(e)工程に先立って、前記スペーサの前記一部が前記未接続パッド電極上に位置するように、前記第1半導体チップの前記第1主面上に前記スペーサを搭載することを特徴とする半導体装置の製造方法。Prior to the step (e), the spacer is mounted on the first main surface of the first semiconductor chip such that the part of the spacer is positioned on the unconnected pad electrode. A method for manufacturing a semiconductor device.
第1主面、前記第1主面に形成された複数の第1パッド電極、および前記第1主面とは反対側の第1裏面を有し、前記第1裏面が前記配線基板の前記上面と対向するように、前記配線基板の前記上面上に搭載された第1半導体チップと、
前記複数の第1パッド電極が露出するように、前記第1半導体チップの前記第1主面上に搭載されたスペーサと、
第2主面、前記第2主面に形成された複数の第2パッド電極、および前記第2主面とは反対側の第2裏面を有し、前記第2裏面が前記スペーサと対向するように、前記スペーサ上に搭載された第2半導体チップと、
前記第1半導体チップの前記複数の第1パッド電極と前記配線基板の前記複数のリード電極とを、それぞれ電気的に接続する複数の第1ワイヤと、
前記第2半導体チップの前記複数の第2パッド電極と前記配線基板の前記複数のリード電極とを、それぞれ電気的に接続する複数の第2ワイヤと、
を含み、
前記複数の第1パッド電極は、前記配線基板の前記リード電極と電気的に接続されない未接続パッド電極を有しており、
前記未接続パッド電極上には、ダミーパターンが配置されており、
前記第2半導体チップは、前記複数の第2パッド電極のうちの一つが前記ダミーパター
ン上に位置するように、前記スペーサ上に搭載されていることを特徴とする半導体装置。 A wiring board having an upper surface, a plurality of lead electrodes formed on the upper surface, and a lower surface opposite to the upper surface;
A first main surface; a plurality of first pad electrodes formed on the first main surface; and a first back surface opposite to the first main surface , wherein the first back surface is the top surface of the wiring board. A first semiconductor chip mounted on the upper surface of the wiring board so as to be opposed to
A spacer mounted on the first main surface of the first semiconductor chip such that the plurality of first pad electrodes are exposed ;
A second main surface, a plurality of second pad electrodes formed on the second main surface, and a second back surface opposite to the second main surface , wherein the second back surface faces the spacer. A second semiconductor chip mounted on the spacer;
Wherein the plurality of the lead electrodes of the plurality of first pad electrode and the wiring substrate of the first semiconductor chip, a plurality of first wires electrically connected,
Wherein the plurality of the lead electrodes of the plurality of second pad electrode and the wiring substrate of the second semiconductor chip, a plurality of second wires electrically connected,
It includes,
The plurality of first pad electrodes have unconnected pad electrodes that are not electrically connected to the lead electrodes of the wiring board ,
A dummy pattern is disposed on the unconnected pad electrode ,
In the second semiconductor chip, one of the plurality of second pad electrodes is the dummy pattern.
The semiconductor device is mounted on the spacer so as to be located on the surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008034089A JP5184132B2 (en) | 2008-02-15 | 2008-02-15 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008034089A JP5184132B2 (en) | 2008-02-15 | 2008-02-15 | Semiconductor device and manufacturing method thereof |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009194189A JP2009194189A (en) | 2009-08-27 |
JP2009194189A5 true JP2009194189A5 (en) | 2011-02-10 |
JP5184132B2 JP5184132B2 (en) | 2013-04-17 |
Family
ID=41075942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008034089A Expired - Fee Related JP5184132B2 (en) | 2008-02-15 | 2008-02-15 | Semiconductor device and manufacturing method thereof |
Country Status (1)
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JP (1) | JP5184132B2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5673423B2 (en) | 2011-08-03 | 2015-02-18 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of semiconductor device |
JP2013093483A (en) * | 2011-10-27 | 2013-05-16 | Semiconductor Components Industries Llc | Semiconductor device and manufacturing method of the same |
JP2016048756A (en) | 2014-08-28 | 2016-04-07 | マイクロン テクノロジー, インク. | Semiconductor device |
KR102185706B1 (en) * | 2017-11-08 | 2020-12-02 | 삼성전자주식회사 | Fan-out semiconductor package |
US10643919B2 (en) | 2017-11-08 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
KR102438456B1 (en) | 2018-02-20 | 2022-08-31 | 삼성전자주식회사 | Semiconductor package and method of manufacturing the semiconductor package |
CN110444528B (en) * | 2018-05-04 | 2021-04-20 | 晟碟信息科技(上海)有限公司 | Semiconductor device including dummy pull-down wire bond |
CN116314114B (en) * | 2023-05-24 | 2023-08-04 | 遂宁合芯半导体有限公司 | Semiconductor packaging structure |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20030018204A (en) * | 2001-08-27 | 2003-03-06 | 삼성전자주식회사 | Multi chip package having spacer |
JP2005197491A (en) * | 2004-01-08 | 2005-07-21 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JP4494240B2 (en) * | 2005-02-03 | 2010-06-30 | 富士通マイクロエレクトロニクス株式会社 | Resin-sealed semiconductor device |
JP5205867B2 (en) * | 2007-08-27 | 2013-06-05 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
JP5529371B2 (en) * | 2007-10-16 | 2014-06-25 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and manufacturing method thereof |
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2008
- 2008-02-15 JP JP2008034089A patent/JP5184132B2/en not_active Expired - Fee Related
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