JP2010067725A - Laminated capacitor, and method for manufacturing the same - Google Patents

Laminated capacitor, and method for manufacturing the same Download PDF

Info

Publication number
JP2010067725A
JP2010067725A JP2008231506A JP2008231506A JP2010067725A JP 2010067725 A JP2010067725 A JP 2010067725A JP 2008231506 A JP2008231506 A JP 2008231506A JP 2008231506 A JP2008231506 A JP 2008231506A JP 2010067725 A JP2010067725 A JP 2010067725A
Authority
JP
Japan
Prior art keywords
internal electrode
dielectric constant
constant material
capacitance
internal electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008231506A
Other languages
Japanese (ja)
Inventor
Yasutomo Suga
康友 須賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP2008231506A priority Critical patent/JP2010067725A/en
Publication of JP2010067725A publication Critical patent/JP2010067725A/en
Withdrawn legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated capacitor capable of suppressing capacitance reduction and capacitance dispersion even when displacement in lamination occurs and capable of reducing also crosstalk. <P>SOLUTION: The laminated capacitor 10 has a structure including a dielectric layer 14 and external electrodes 22, 24 which are formed on the end faces of a laminate 12 configured by alternately laminating a pair of internal electrodes 16, 18 opposed to each other on the same layer through a high dielectric constant material 20. By filling the high dielectric constant material 20 between the internal electrodes 16, 18, large capacitance can be obtained. By utilizing a low dielectric constant material for the dielectric layer 14 and shortening the length of the internal electrodes 16, 18, floating capacitance is reduced and crosstalk can be reduced. Further since capacitance per layer can be adjusted by changing an interval d between the internal electrodes 16, 18, the number of laminated layers of the internal electrodes 16, 18 can be optimized, contact defects of the internal electrodes 16, 18 with the external electrodes 22, 24 can be suppressed and the capacitance dispersion can be reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、積層コンデンサ及びその製造方法に関し、更に具体的には、積層ずれが発生しても容量低下及び容量のばらつきを抑制でき、かつアレイ型でもクロストークを低減することができる積層コンデンサ及びその製造方法に関するものである。   The present invention relates to a multilayer capacitor and a method of manufacturing the same, more specifically, a multilayer capacitor capable of suppressing a decrease in capacitance and variation in capacitance even when a stacking error occurs, and reducing crosstalk even in an array type. It relates to the manufacturing method.

積層セラミックコンデンサに求められる課題の一つは、容量のばらつきの抑制である。特に、低積層品は、内部電極一層あたりの容量寄与度が大きく、容量ばらつきの抑制が課題となっている。また、アレイ型積層セラミックコンデンサは、内部電極の引き出し幅が狭く、外部電極とのコンタクト不良が発生して容量が低下しやすいという問題がある。上述した容量のばらつきを発生させる原因の一つは、積層ずれで発生する内部パターン有効電極面積の減少による容量低下である。   One of the issues required for multilayer ceramic capacitors is suppression of variation in capacitance. In particular, low-lamination products have a large capacity contribution per internal electrode layer, and it is an issue to suppress capacity variation. In addition, the array type multilayer ceramic capacitor has a problem that the lead-out width of the internal electrode is narrow and a contact failure with the external electrode occurs, resulting in a decrease in capacitance. One of the causes of the above-described variation in capacitance is a decrease in capacitance due to a reduction in the internal pattern effective electrode area caused by stacking deviation.

前記積層ずれによる容量低下対策として、例えば、下記特許文献１には、矩形状の誘電体層上に、該誘電体層の一対の端辺に各々導出され、且つ中央部側で互いに対峙する一対の内部電極を形成するとともに、該誘電体層を複数積層し成る該積層体の両端面に、前記内部電極と接続する一対の外部端子電極を形成して成る積層セラミックコンデンサにおいて、前記一対の内部電極の一方の対峙する電極幅を、他方の電極幅よりも狭くすることによって、積層ずれの因子を排除する技術が開示されている。当該特許文献１の技術は、低容量を取得するためには有効である。特に、アレイ型コンデンサでは、一層当たりの容量が低くなるために内部電極の積層数を多くすることができ、内部電極と外部電極のコンタクト不良が起こりにくくなるため、容量のばらつきを低減できるという利点がある。
特開平１１−３４００８４号公報 As a countermeasure for reducing the capacitance due to the stacking deviation, for example, in Patent Document 1 below, a pair of dielectric layers that are respectively led to a pair of edges of the dielectric layer and face each other on the center side. A laminated ceramic capacitor in which a pair of external terminal electrodes connected to the internal electrodes are formed on both end faces of the multilayer body formed by laminating a plurality of dielectric layers. There is disclosed a technique for eliminating the factor of misalignment by making the electrode width of one of the electrodes opposite to that of the other electrode. The technique of Patent Document 1 is effective for obtaining a low capacity. In particular, in an array type capacitor, since the capacitance per layer is low, the number of laminated internal electrodes can be increased, and contact defects between the internal electrode and the external electrode are less likely to occur, so that variation in capacitance can be reduced. There is.
JP-A-11-340084

しかしながら、以上のような背景技術では、より高容量が必要になったときに、十分に容量を取得できないという不都合が生じる。また、背景技術をアレイ型積層セラミックコンデンサに適用した場合、高容量を得るためには、誘電体の誘電率を高くする，電極幅を長くする，内部電極の積層数を増やすという必要があるため、素子間での浮遊容量が大きくなりクロストークが問題となる。   However, the background art as described above has a disadvantage that a sufficient capacity cannot be obtained when a higher capacity is required. Also, when the background technology is applied to an array type multilayer ceramic capacitor, in order to obtain a high capacity, it is necessary to increase the dielectric constant of the dielectric, increase the electrode width, and increase the number of stacked internal electrodes. As a result, stray capacitance between elements increases and crosstalk becomes a problem.

本発明は、以上の点に着目したもので、その目的は、積層ずれが発生しても容量低下及び容量のばらつきを抑制できるとともに、アレイ型に適用した場合でもクロストークを低減することができる積層コンデンサ及びその製造方法を提供することである。   The present invention focuses on the above points, and the object of the present invention is to suppress a decrease in capacitance and variation in capacitance even when a stacking error occurs, and to reduce crosstalk even when applied to an array type. A multilayer capacitor and a method for manufacturing the same are provided.

前記目的を達成するため、本発明の積層コンデンサは、同一層内で一端側が所定の間隔をあけて対向する一対以上の内部電極と、低誘電率材料からなる誘電体層とを交互に積層した積層体の端面に、該端面に露出した前記内部電極の引出側の端部と接続する外部電極を設けた積層コンデンサであって、前記内部電極の対向する端部間に、高誘電率材料を充填したことを特徴とする。主要な形態の一つは、前記内部電極の引出側の幅を、前記対向側の幅よりも狭く設定したことを特徴とする。   In order to achieve the above object, the multilayer capacitor of the present invention is formed by alternately laminating a pair of internal electrodes opposed to each other at a predetermined interval and dielectric layers made of a low dielectric constant material in the same layer. A multilayer capacitor in which an external electrode connected to an end of the internal electrode exposed on the end face is provided on an end face of the multilayer body, and a high dielectric constant material is provided between the opposing ends of the internal electrode. It is characterized by filling. One of the main forms is characterized in that the width on the lead-out side of the internal electrode is set narrower than the width on the opposite side.

本発明の積層コンデンサの製造方法は、低誘電率材料のグリーンシート上に、一端側が所定の間隔をあけて対向し、他端側が前記グリーンシートの端部に引き出された内部電極パターンを一対以上形成する工程，前記内部電極パターンの対向する端部間に、高誘電率材料を充填する工程，前記グリーンシートを、前記内部電極パターンの位置を合わせて積層する工程，該工程で得られた積層体の端面に、前記内部電極パターンの引出部と接続する外部電極パターンを形成する工程，前記積層体を焼成する工程，を含むことを特徴とする。   The method for manufacturing a multilayer capacitor according to the present invention comprises a pair of one or more internal electrode patterns on a green sheet of a low dielectric constant material with one end facing each other with a predetermined interval and the other end being drawn out to the end of the green sheet. A step of forming, a step of filling a high dielectric constant material between opposing ends of the internal electrode pattern, a step of laminating the green sheet by aligning the position of the internal electrode pattern, and a lamination obtained in the step The method includes a step of forming an external electrode pattern connected to the lead portion of the internal electrode pattern on an end surface of the body, and a step of firing the laminate.

他の発明の積層コンデンサの製造方法は、低誘電率材料のグリーンシート上に、一端側が所定の間隔をあけて対向し、他端側が前記グリーンシートの端部に引き出された一対の内部電極パターンを複数形成する工程，前記内部電極パターンの対向する端部間に、高誘電率材料を充填する工程，前記グリーンシートを、前記内部電極パターンの位置を合わせて積層する工程，該工程で得られた積層体を、分割後の各チップが同一層内に一対以上の内部電極パターンを含むように複数の積層チップに切断する工程，前記積層チップの端面に、前記内部電極パターンの引出部と接続する外部電極パターンを形成する工程，前記積層チップを焼成する工程，を含むことを特徴とする。主要な形態の一つは、前記内部電極パターンの形成及び高誘電率材料の充填を、印刷法により行ったことを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a multilayer capacitor, wherein a pair of internal electrode patterns are formed on a green sheet of a low dielectric constant material so that one end faces each other with a predetermined interval and the other end is drawn to an end of the green sheet. A plurality of layers, a step of filling a high dielectric constant material between opposing ends of the internal electrode pattern, a step of laminating the green sheet by aligning the positions of the internal electrode patterns, obtained in the step Cutting the laminated body into a plurality of laminated chips so that each divided chip includes a pair of internal electrode patterns in the same layer, and connecting the leading portion of the internal electrode pattern to the end face of the laminated chip A step of forming an external electrode pattern, and a step of firing the laminated chip. One of the main forms is characterized in that the formation of the internal electrode pattern and the filling of the high dielectric constant material are performed by a printing method.

他の発明の積層コンデンサは、前記いずれかに記載の製造方法によって形成されたことを特徴とする。本発明の前記及び他の目的，特徴，利点は、以下の詳細な説明及び添付図面から明瞭になろう。   Another aspect of the invention is a multilayer capacitor formed by any one of the manufacturing methods described above. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

本発明は、同一層内で一端側が所定の間隔をあけて対向する一対以上の内部電極と、低誘電率材料からなる誘電体層とを交互に積層した積層体の端面に、該端面に露出した前記内部電極の引出側の端部と接続する外部電極を設けるとともに、前記内部電極の対向する端部間に、高誘電率材料を充填することとした。このため、積層ずれが発生した場合でも、容量低下や容量のばらつきを抑制するとともに、アレイ型に適用した場合でもクロストークを低減できる積層コンデンサが得られるという効果がある。   The present invention exposes an end face of a laminate in which a pair of internal electrodes and one or more internal electrodes facing each other at a predetermined interval in the same layer and a dielectric layer made of a low dielectric constant material are alternately laminated. An external electrode connected to the end of the internal electrode on the lead side is provided, and a high dielectric constant material is filled between the opposing ends of the internal electrode. For this reason, even when a stacking error occurs, it is possible to obtain a multilayer capacitor that can suppress a decrease in capacitance and variation in capacitance, and can reduce crosstalk even when applied to an array type.

以下、本発明を実施するための最良の形態を、実施例に基づいて詳細に説明する。   Hereinafter, the best mode for carrying out the present invention will be described in detail based on examples.

最初に、図１〜図３を参照しながら本発明の実施例１を説明する。図１(A)及び(B)は本実施例の主要部を示す平面図，図１(C)は積層コンデンサの断面図である。図２は、本実施例の一製造工程を示す平面図であり、図３は、本実施例と背景技術の積層コンデンサにおける取得容量と容量のばらつきの関係を示す図である。図１(C)に示すように、本実施例の積層コンデンサ１０は、誘電体層１４と、高誘電率材料２０を挟んで同一層内で対向した一対の内部電極１６，１８とを交互に積層した積層体１２の端面に、外部電極２２，２４を設けた構造となっている。前記内部電極１６，１８は、図１(A)及び(B)に示すように、一方の端部側の対向部１６Ａ，１８Ａが所定の間隔ｄをおいて対向しており、他方の端部側の引出部１６Ｂ，１８Ｂが前記外部電極２２，２４に接続されている。前記引出部１６Ｂ，１８Ｂの幅ｃ（図２参照）は、前記対向部１６Ａ，１８Ａの幅よりも狭く設定されている。なお、本実施例では、前記内部電極１６，１８は、同一層内に２対形成されている。   First, Embodiment 1 of the present invention will be described with reference to FIGS. 1A and 1B are plan views showing the main part of this embodiment, and FIG. 1C is a cross-sectional view of the multilayer capacitor. FIG. 2 is a plan view showing one manufacturing process of the present embodiment, and FIG. 3 is a diagram showing a relationship between acquired capacitance and capacitance variation in the multilayer capacitor of the present embodiment and the background art. As shown in FIG. 1 (C), the multilayer capacitor 10 of this embodiment includes a dielectric layer 14 and a pair of internal electrodes 16 and 18 that are opposed to each other in the same layer with the high dielectric constant material 20 interposed therebetween. External electrodes 22 and 24 are provided on the end face of the laminated body 12 that has been laminated. As shown in FIGS. 1 (A) and 1 (B), the internal electrodes 16 and 18 have opposing ends 16A and 18A on one end side facing each other with a predetermined distance d, and the other end portion. Side lead portions 16B and 18B are connected to the external electrodes 22 and 24, respectively. The width c (see FIG. 2) of the lead portions 16B and 18B is set to be narrower than the width of the facing portions 16A and 18A. In this embodiment, two pairs of the internal electrodes 16 and 18 are formed in the same layer.

前記積層コンデンサ１０の製造方法の一例を説明すると、まず、常誘電体のような低誘電率材料（例えば、チタン酸ストロンチウム等を主成分とする酸化物）を使用して、誘電体のグリーンシートＬを作製する。そして、該グリーンシートＬ上に、例えば、Ｎｉ等の卑金属ペーストを用いて印刷法によって内部電極１６，１８のパターンを形成する。このときの内部電極パターンＰは、図２に示すように、対向部１６Ａ，１８Ａの間に所定の間隔ｄを有するように、引出部１６Ｂ，１８Ｂが複数連結した形状となっている。そして、前記内部電極パターンＰが、同一のグリーンシートＬ上に複数形成されている。ここで、内部電極１６，１８の対向部１６Ａ，１８Ａの長さａが大きいと、素子間の浮遊容量増加につながるため、極力小さくすることが好ましい。また、内部電極１６，１８の引出部１６Ｂ，１８Ｂの幅ｃが大きいと内部電極露出のおそれがあるため、積層精度や外部電極塗布位置の精度などを考慮して設計する必要がある。   An example of a method of manufacturing the multilayer capacitor 10 will be described. First, a dielectric green sheet using a low dielectric constant material such as a paraelectric material (for example, an oxide containing strontium titanate as a main component). L is produced. Then, the pattern of the internal electrodes 16 and 18 is formed on the green sheet L by a printing method using a base metal paste such as Ni. As shown in FIG. 2, the internal electrode pattern P at this time has a shape in which a plurality of lead portions 16B and 18B are connected so as to have a predetermined distance d between the facing portions 16A and 18A. A plurality of the internal electrode patterns P are formed on the same green sheet L. Here, if the lengths a of the facing portions 16A and 18A of the internal electrodes 16 and 18 are large, the stray capacitance between the elements is increased, so it is preferable to make it as small as possible. Further, if the widths c of the lead portions 16B and 18B of the internal electrodes 16 and 18 are large, the internal electrodes may be exposed. Therefore, it is necessary to design in consideration of the stacking accuracy and the accuracy of the external electrode application position.

次に、前記対向部１６Ａ，１８Ａ間に、印刷法を用いて強誘電体材料ペースト（例えば、チタン酸バリウムを主成分とする酸化物等）を印刷し(図１(B)参照)、高誘電率材料２０を充填する。このようにして内部電極パターンＰと高誘電率材料２０が形成されたグリーンシートＬを、前記内部電極パターンＰの位置が合うように所定の枚数積層し、該積層体を図２に破線で示す位置で複数の積層生チップに切断する。図示の例では、各積層生チップが、内部電極１６，１８を２対有するように分割されている。以上のようにして得られた積層生チップに、外部電極２２，２４のパターン（例えば、Ｎｉ等の卑金属を主成分とする金属）を形成して焼成することで、積層コンデンサ１０が得られる。   Next, a ferroelectric material paste (for example, an oxide containing barium titanate as a main component) is printed between the facing portions 16A and 18A using a printing method (see FIG. 1B). Fill with dielectric material 20. A predetermined number of green sheets L on which the internal electrode pattern P and the high dielectric constant material 20 are formed in this way are stacked so that the positions of the internal electrode patterns P are aligned, and the stacked body is shown by a broken line in FIG. Cut into multiple stacked raw chips at the position. In the illustrated example, each stacked raw chip is divided so as to have two pairs of internal electrodes 16 and 18. The multilayer capacitor 10 is obtained by forming a pattern of the external electrodes 22 and 24 (for example, a metal containing a base metal such as Ni as a main component) on the multilayer green chip obtained as described above and firing it.

このような構成の積層コンデンサ１０では、内部電極１６，１８間に、強誘電体のような高誘電率材料２０を充填させることによって、同一平面間における対向電極との間では大きな容量を取得することができる。また、積層ずれ量をｐ，内部電極１６，１８間の間隔をｄとすると、ｐ＞ｄのときに積層方向における対向電極間の取得容量は極めて小さくなる。従って、コンデンサとしての容量ばらつきは、前記間隔ｄの形成精度が支配することになるが、本実施例によれば、上述したように印刷法によって内部電極パターンＰ（内部電極１６及び１８）を形成しているため、極めて高い精度で間隔ｄを形成することができる。一方、常誘電体のような低誘電率材料のシートを利用して誘電体層１４を形成しているため、素子間での浮遊容量は小さくなる。なお、ここでいう素子間とは、同一平面における回路を構成しないパターン間のことであって、図１(B)に点線で囲った部分のように、隣接する内部電極１６間や内部電極１８間のことを示している。   In the multilayer capacitor 10 having such a configuration, a large capacitance is obtained between the internal electrodes 16 and 18 and a counter electrode in the same plane by filling a high dielectric constant material 20 such as a ferroelectric. be able to. Further, when the stacking deviation amount is p and the interval between the internal electrodes 16 and 18 is d, the acquired capacity between the opposing electrodes in the stacking direction becomes extremely small when p> d. Accordingly, although the capacitance variation as a capacitor is governed by the formation accuracy of the interval d, according to the present embodiment, the internal electrode pattern P (internal electrodes 16 and 18) is formed by the printing method as described above. Therefore, the distance d can be formed with extremely high accuracy. On the other hand, since the dielectric layer 14 is formed using a sheet of a low dielectric constant material such as a paraelectric material, the stray capacitance between elements is reduced. Note that the term “between elements” here refers to between patterns that do not constitute a circuit on the same plane, and between adjacent internal electrodes 16 and internal electrodes 18 as shown by a dotted line in FIG. It shows that in between.

また、内部電極１６，１８の対向部の長さａを小さくすることで、浮遊容量をより小さくすることができるため、クロストークが低減できる。更に、内部電極１６，１８間の間隔ｄの設計を変えることで、一層当たりの容量を設計することができるため、内部電極の積層数を最適化することで内部電極１６，１８と外部電極２２，２４のコンタクト不良を抑制可能となり、容量のばらつきを低減することができる。   Moreover, since the stray capacitance can be further reduced by reducing the length a of the opposing portion of the internal electrodes 16 and 18, crosstalk can be reduced. Furthermore, since the capacity per layer can be designed by changing the design of the distance d between the internal electrodes 16 and 18, the internal electrodes 16 and 18 and the external electrode 22 are optimized by optimizing the number of stacked internal electrodes. , 24 can be suppressed, and variation in capacitance can be reduced.

図３には、本実施例の製造方法と、低誘電率材料を挟んで内部電極がずれるように積層する従来の製造方法で作製した積層コンデンサにおける取得容量と容量のばらつきの関係が示されている。従来の方法で作製したコンデンサは、積層された上下の内部電極層間で容量を取得する構造となっている。同図において、横軸は取得容量（ｐＦ）を表し、縦軸は、容量ＣＶ値（％）を示している。なお、ＣＶ値とは、標準偏差σと平均の比（σ／ａｖｅ）である。測定装置としては、ＨＰ４２７８ＡとＨＰ１６０３４Ｈ（ともにヒューレット・パッカード社製）を用い、１ＭＨｚ−１Ｖ、２５℃の条件下で測定を行った。図３に示すように、従来の手法では、ＣＶ値が３〜１０％であるのに対し、本実施例の手法では、取得容量が低い場合でもＣＶ値が２％以下と大幅に改善されていることが確認できた。   FIG. 3 shows the relationship between the obtained capacitance and the variation in capacitance in the multilayer capacitor manufactured by the manufacturing method of this example and the conventional manufacturing method in which the internal electrodes are stacked so that the internal electrodes are shifted with the low dielectric constant material interposed therebetween. Yes. A capacitor manufactured by a conventional method has a structure in which a capacitance is acquired between the stacked upper and lower internal electrode layers. In the figure, the horizontal axis represents the acquired capacitance (pF), and the vertical axis represents the capacitance CV value (%). The CV value is a ratio of the standard deviation σ to the average (σ / ave). As a measuring apparatus, HP4278A and HP16034H (both manufactured by Hewlett-Packard) were used, and measurement was performed under conditions of 1 MHz-1 V and 25 ° C. As shown in FIG. 3, in the conventional method, the CV value is 3 to 10%, but in the method of this example, the CV value is greatly improved to 2% or less even when the acquisition capacity is low. It was confirmed that

このように、実施例１によれば、次のような効果がある。
(1)同一層内で対向する内部電極１６，１８間に、強誘電体のような高誘電率材料２０を充填することで、同一平面内では対向電極間で大きな容量を取得できる。
(2)誘電体層１４に、常誘電体のような低誘電率材料を利用しているため、素子間での浮遊容量が小さくなる。また、内部電極１６，１８の対向部１６Ａ，１８Ｂの長さａを小さくすることで浮遊容量をより小さくすることができるため、アレイ型のコンデンサであっても、クロストークが低減できる。
(3)内部電極パターンＰを印刷法により形成するため、高い精度で対向電極間の間隔ｄを設定することができる。
(4)前記間隔ｄの設計を変えることで一層当たりの容量を調整することができるため、内部電極１６，１８の積層数を最適化することで、内部電極１６，１８と外部電極２２，２４のコンタクト不良の抑制が可能となり、容量のばらつきを低減することができる。 Thus, according to the first embodiment, there are the following effects.
(1) By filling the internal electrodes 16 and 18 facing each other in the same layer with a high dielectric constant material 20 such as a ferroelectric, a large capacity can be obtained between the opposing electrodes in the same plane.
(2) Since a low dielectric constant material such as a paraelectric material is used for the dielectric layer 14, stray capacitance between elements is reduced. Further, since the stray capacitance can be further reduced by reducing the length a of the opposing portions 16A and 18B of the internal electrodes 16 and 18, crosstalk can be reduced even with an array type capacitor.
(3) Since the internal electrode pattern P is formed by a printing method, the interval d between the counter electrodes can be set with high accuracy.
(4) Since the capacity per layer can be adjusted by changing the design of the distance d, the internal electrodes 16 and 18 and the external electrodes 22 and 24 are optimized by optimizing the number of stacked internal electrodes 16 and 18. The contact failure can be suppressed, and the variation in capacitance can be reduced.

なお、本発明は、上述した実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々変更を加え得ることができる。例えば、以下のものも含まれる。
(1)前記実施例で示した形状，寸法は一例であり、必要に応じて適宜変更してよい。材料についても同様であり、必要に応じて適宜変更してよい。
(2)前記実施例に示した内部電極１６，１８の積層数も一例であり、必要に応じて適宜変更してよい。また、前記実施例では、同一層上に、対向する内部電極１６，１８を２対設けることとしたが、これも一例であり、３対以上の内部電極を含むようにしてもよい。
(3)上述した製造方法も一例であり、同様の効果を奏するように適宜変更してよい。例えば、前記実施例では、複数の内部電極パターンＰを形成したグリーンシートＬの積層体をカットして複数の積層生チップを形成したが、これも一例であり、グリーンシートＬ上に内部電極１６，１８を一対のみ形成するようにしてよい。
(4)本発明は、クロストークの低減が可能であるため、アレイ型の積層コンデンサに好適であるが、２端子の積層コンデンサにも適用可能である。 In addition, this invention is not limited to the Example mentioned above, A various change can be added in the range which does not deviate from the summary of this invention. For example, the following are also included.
(1) The shapes and dimensions shown in the above embodiments are examples, and may be appropriately changed as necessary. The same applies to the material, and it may be changed as needed.
(2) The number of stacked internal electrodes 16 and 18 shown in the above embodiment is also an example, and may be changed as necessary. In the above embodiment, two pairs of opposed internal electrodes 16 and 18 are provided on the same layer. However, this is also an example, and three or more pairs of internal electrodes may be included.
(3) The above-described manufacturing method is also an example, and may be changed as appropriate to achieve the same effect. For example, in the above-described embodiment, the laminated body of the green sheets L on which the plurality of internal electrode patterns P are formed is cut to form a plurality of laminated green chips. , 18 may be formed as a pair.
(4) Since the present invention can reduce crosstalk, it is suitable for an array type multilayer capacitor, but is also applicable to a two-terminal multilayer capacitor.

本発明によれば、同一層内で一端側が所定の間隔をあけて対向する一対以上の内部電極と、低誘電率材料からなる誘電体層とを交互に積層した積層体の端面に、前記内部電極の引出側の端部と接続する外部電極を設けるとともに、前記内部電極の対向する端部間に高誘電率材料を設けることとした。これにより、積層ずれが発生した場合でも、容量低下や容量のばらつきを低減できるため、積層コンデンサの用途に適用できる。特に、クロストークの低減が可能であることから、アレイ型の積層コンデンサの用途に好適である。   According to the present invention, on the end face of a laminate in which one or more internal electrodes opposite to each other at a predetermined interval in the same layer and dielectric layers made of a low dielectric constant material are alternately laminated, An external electrode connected to the end of the electrode on the extraction side is provided, and a high dielectric constant material is provided between the opposing ends of the internal electrode. As a result, even when a stacking error occurs, it is possible to reduce the capacity drop and the variation in the capacity. In particular, since crosstalk can be reduced, it is suitable for an array type multilayer capacitor.

本発明の実施例１を示す図であり、(A)及び(B)は主要部を示す平面図，(C)は本実施例の積層コンデンサの断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows Example 1 of this invention, (A) and (B) are top views which show the principal part, (C) is sectional drawing of the multilayer capacitor of a present Example. 前記実施例１の一製造工程を示す平面図である。6 is a plan view showing one manufacturing process of Example 1. FIG. 前記実施例１と背景技術のコンデンサにおける取得容量と容量のばらつきの関係を示す図である。It is a figure which shows the relationship between the acquisition capacity | capacitance and the dispersion | variation in a capacity | capacitance in the said Example 1 and the capacitor | condenser of background art.

符号の説明Explanation of symbols

１０：積層コンデンサ
１２：積層体
１４：誘電体層
１６，１８：内部電極
１６Ａ，１８Ａ：対向部
１６Ｂ，１８Ｂ：引出部
２０：高誘電率材料
２２，２４：外部電極
Ｌ：グリーンシート
Ｐ：内部電極パターン 10: Multilayer capacitor 12: Laminated body 14: Dielectric layer 16, 18: Internal electrodes 16A, 18A: Opposing portions 16B, 18B: Leading portion 20: High dielectric constant material 22, 24: External electrode L: Green sheet P: Internal Electrode pattern

Claims (6)

同一層内で一端側が所定の間隔をあけて対向する一対以上の内部電極と、低誘電率材料からなる誘電体層とを交互に積層した積層体の端面に、該端面に露出した前記内部電極の引出側の端部と接続する外部電極を設けた積層コンデンサであって、
前記内部電極の対向する端部間に、高誘電率材料を充填したことを特徴とする積層コンデンサ。 The internal electrode exposed on the end face of a laminated body in which a pair of internal electrodes facing each other at a predetermined interval in the same layer and a dielectric layer made of a low dielectric constant material are alternately laminated. A multilayer capacitor provided with an external electrode connected to the end of the lead-out side,
A multilayer capacitor, wherein a high dielectric constant material is filled between opposing ends of the internal electrode. 前記内部電極の引出側の幅を、前記対向側の幅よりも狭く設定したことを特徴とする請求項１記載の積層コンデンサ。   2. The multilayer capacitor according to claim 1, wherein a width of the internal electrode on the lead side is set to be narrower than a width on the opposite side. 低誘電率材料のグリーンシート上に、一端側が所定の間隔をあけて対向し、他端側が前記グリーンシートの端部に引き出された内部電極パターンを一対以上形成する工程，
前記内部電極パターンの対向する端部間に、高誘電率材料を充填する工程，
前記グリーンシートを、前記内部電極パターンの位置を合わせて積層する工程，
該工程で得られた積層体の端面に、前記内部電極パターンの引出部と接続する外部電極パターンを形成する工程，
前記積層体を焼成する工程，
を含むことを特徴とする積層コンデンサの製造方法。 A step of forming one or more pairs of internal electrode patterns with one end facing each other with a predetermined interval on the green sheet of low dielectric constant material and the other end extending to the end of the green sheet;
Filling a high dielectric constant material between opposing ends of the internal electrode pattern;
Laminating the green sheet by aligning the positions of the internal electrode patterns;
A step of forming an external electrode pattern connected to the lead portion of the internal electrode pattern on the end face of the laminate obtained in the step;
Firing the laminate,
A method for producing a multilayer capacitor comprising the steps of: 低誘電率材料のグリーンシート上に、一端側が所定の間隔をあけて対向し、他端側が前記グリーンシートの端部に引き出された一対の内部電極パターンを複数形成する工程，
前記内部電極パターンの対向する端部間に、高誘電率材料を充填する工程，
前記グリーンシートを、前記内部電極パターンの位置を合わせて積層する工程，
該工程で得られた積層体を、分割後の各チップが同一層内に一対以上の内部電極パターンを含むように複数の積層チップに切断する工程，
前記積層チップの端面に、前記内部電極パターンの引出部と接続する外部電極パターンを形成する工程，
前記積層チップを焼成する工程，
を含むことを特徴とする積層コンデンサの製造方法。 Forming a plurality of a pair of internal electrode patterns on one side of the green sheet of a low dielectric constant material with one end facing each other with a predetermined interval and the other end drawn to the end of the green sheet;
Filling a high dielectric constant material between opposing ends of the internal electrode pattern;
Laminating the green sheet by aligning the positions of the internal electrode patterns;
Cutting the laminated body obtained in the step into a plurality of laminated chips so that each divided chip includes one or more internal electrode patterns in the same layer;
Forming an external electrode pattern connected to a lead portion of the internal electrode pattern on an end face of the multilayer chip;
Firing the laminated chip;
A method for producing a multilayer capacitor comprising the steps of: 前記内部電極パターンの形成及び高誘電率材料の充填を、印刷法により行ったことを特徴とする請求項３又は４記載の積層コンデンサの製造方法。   5. The method of manufacturing a multilayer capacitor according to claim 3, wherein the formation of the internal electrode pattern and the filling of the high dielectric constant material are performed by a printing method. 請求項３〜５のいずれかに記載の製造方法によって形成したことを特徴とする積層コンデンサ。   A multilayer capacitor formed by the manufacturing method according to claim 3.
JP2008231506A 2008-09-09 2008-09-09 Laminated capacitor, and method for manufacturing the same Withdrawn JP2010067725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008231506A JP2010067725A (en) 2008-09-09 2008-09-09 Laminated capacitor, and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008231506A JP2010067725A (en) 2008-09-09 2008-09-09 Laminated capacitor, and method for manufacturing the same

Publications (1)

Publication Number Publication Date
JP2010067725A true JP2010067725A (en) 2010-03-25

Family

ID=42193072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008231506A Withdrawn JP2010067725A (en) 2008-09-09 2008-09-09 Laminated capacitor, and method for manufacturing the same

Country Status (1)

Country Link
JP (1) JP2010067725A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103650655A (en) * 2011-06-28 2014-03-19 瑞典爱立信有限公司 Electronic device with heat-dissipating structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103650655A (en) * 2011-06-28 2014-03-19 瑞典爱立信有限公司 Electronic device with heat-dissipating structure

Similar Documents

Publication Publication Date Title
KR100587006B1 (en) Multi-layer chip capacitor and method for manufacturing the same
KR101565640B1 (en) A multilayer ceramic capacitor and a method for manufactuaring the same
KR101514512B1 (en) A multilayer ceramic capacitor and a method for manufactuaring the same
KR101548798B1 (en) Multi-layered ceramic electronic part and board for mounting the same
KR101762032B1 (en) Multi-layer ceramic electronic part and method for manufacturing the same
KR101983129B1 (en) Multi-layered ceramic electronic parts and method of manufacturing the same
JP5653886B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
KR102061507B1 (en) Multi-layered ceramic electronic part and board for mounting the same
JP2010092896A (en) Multilayer ceramic electronic component and method of manufacturing the same
JP2018182286A (en) Multilayer ceramic capacitor and mounting board of the same
KR20120058128A (en) Multi-layered ceramic capacitor
JP4375006B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
KR20160084217A (en) Laminated ceramic electronic parts and and board having the same mounted thereon
JP2012227197A (en) Multilayer ceramic capacitor
KR101843184B1 (en) Stackup type components and manufacturing method thereof
JPH07135124A (en) Multilayered ceramic capacitor
JP2014212291A (en) Multilayer ceramic electronic component, manufacturing method therefor and mounting board
JP2005136131A (en) Laminated capacitor
JP2015053512A (en) Multilayer ceramic capacitor
KR101565725B1 (en) A multilayer ceramic capacitor and a method for manufactuaring the same
JP2010067725A (en) Laminated capacitor, and method for manufacturing the same
JP5869335B2 (en) Multilayer capacitor
KR101503996B1 (en) Multi-layered ceramic electronic part and board for mounting the same
JP2009130247A (en) Lamination chip capacitor
JP2005327999A (en) Laminated ceramic capacitor

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20111206