JP2009530820A - 炭化ケイ素ベースのアモルファスシリコン薄膜トランジスタを有するスタック不揮発性メモリとその製造方法 - Google Patents
炭化ケイ素ベースのアモルファスシリコン薄膜トランジスタを有するスタック不揮発性メモリとその製造方法 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 38
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 23
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 22
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 239000010408 film Substances 0.000 claims abstract description 17
- 230000007423 decrease Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims description 2
- 230000005641 tunneling Effects 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 claims 1
- 230000004044 response Effects 0.000 claims 1
- 230000006870 function Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 238000007667 floating Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000004397 blinking Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
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Abstract
【選択図】図1
Description
解する。酸化物もしくは他のスペーサー材料300が、図2から完成したばかりのトランジスタの上に形成される。酸化物もしくは他の絶縁層316がその後この上に形成され、上述のプロセスは必要な数のトランジスタスタックに対して繰り返される。
要約すると、本発明の不揮発性メモリトランジスタは炭化ケイ素もしくは炭素豊富なシリコンチャネル薄膜上に製造される。これはトンネル障壁を減らし、低電圧と低電場での消去を容易にする。本発明のセルはメモリデバイスの密度を大きく増加させるために積み重ねることができる。
Claims (48)
- 基板上に垂直に積層される複数の薄膜メモリセルを含むスタック不揮発性薄膜メモリデバイスであって、前記各メモリセルが、
前記基板の上に形成される絶縁層、
所定の炭素濃度を持つアモルファスシリコンを含み、前記絶縁層の上に形成されるチャネル領域層、
前記チャネル領域層の上に形成される誘電体スタック、
前記誘電体スタックの上に形成される制御ゲート、
を含む複数の薄膜メモリセルである、スタック不揮発性薄膜メモリデバイス。 - 前記制御ゲートがポリシリコンもしくは金属の内の一つを含む、請求項1のデバイス。
- 前記金属がTiNもしくはTaNの内の一つである、請求項2のデバイス。
- 前記絶縁層が酸化物層である、請求項1のデバイス。
- 各メモリセル間に垂直に形成される絶縁材料をさらに含む、請求項1のデバイス。
- 前記所定の炭素濃度が、前記アモルファスシリコン層が炭化ケイ素層であるようになっている、請求項1のデバイス。
- 前記誘電体スタックの両側で前記チャネル領域層中に形成されるソース/ドレイン領域のペアをさらに含む、請求項1のデバイス。
- シリコン基板上に垂直に積層される複数の薄膜メモリセルを含むスタック不揮発性薄膜メモリデバイスであって、前記各メモリセル層が、
前記基板の上に形成される酸化物層、
所定の炭素濃度を持ち、前記酸化物の上に形成されるアモルファスシリコン層、
前記チャネル領域層の上に形成される誘電体スタック、
前記誘電体スタックの対向側面上で前記アモルファスシリコン層中に形成されるソース/ドレイン領域のペア、
前記誘電体スタックの上に形成される制御ゲート、
を含む複数の薄膜メモリセルである、スタック不揮発性薄膜メモリデバイス。 - 前記不揮発性薄膜メモリデバイスがフラッシュメモリデバイスである、請求項8のデバイス。
- 前記所定の炭素濃度がメモリセルの各層ごとに減少してゆく、請求項8のデバイス。
- 前記誘電体スタックが酸化物‐窒化物‐酸化物構造を含む、請求項8のデバイス。
- 前記誘電体スタックの対向側面上に形成されるスペーサー材料をさらに含む、請求項8のデバイス。
- 前記複数のスタックメモリセルの最上層中の各ソース/ドレイン領域上に形成される金属コンタクトをさらに含む、請求項8のデバイス。
- 基板の上に垂直に積層される薄膜メモリセルの複数の層を含む不揮発性メモリデバイスを製造するための方法であって、各層を製造するための前記方法は、
絶縁層を形成するステップ、
前記絶縁層の上にアモルファスシリコン膜を形成するステップ、
炭素豊富なシリコン膜を形成するために、前記アモルファスシリコン膜中の炭素濃度を増加させるステップ、
前記アモルファスシリコン層の上に誘電体スタックを形成するステップ、
前記誘電体スタックの上に制御ゲートを形成するステップ、
を含む方法。 - 前記誘電体層を形成するステップが、酸化物‐窒化物‐酸化物層を形成するステップを含む、請求項14の方法。
- 前記誘電体層を形成するステップが、酸化物‐高k誘電体‐酸化物層を形成するステップを含む、請求項14の方法。
- 前記高k誘電体がAl2O3、HfO2、LaO3、もしくはLaAlO3の内の一つを含む、請求項16の方法。
- 前記制御ゲートを形成するステップが、前記誘電体スタックの上に金属層を形成するステップを含む、請求項14の方法。
- 前記金属層がTiNもしくはTaNの内の一つを含む、請求項18の方法。
- 前記誘電体スタックの対向側面上にスペーサーを形成するステップをさらに含む、請求項14の方法。
- 前記炭素濃度を増加させるステップが、Si:C成長温度を制御することによって前記炭素濃度を調整するステップを含む、請求項14の方法。
- 前記炭素豊富なシリコン膜と前記誘電体スタックとの間にアモルファスシリコンキャップ層を形成するステップをさらに含む、請求項14の方法。
- 前記炭素濃度を増加させるステップが、最下位層が上位の層よりも大きな炭素濃度を有するように前記アモルファスシリコンの前記炭素濃度を増加させるステップを含む、請求項14の方法。
- 前記炭素濃度を増加させるステップが、前記層が増加する程、各層の前記アモルファスシリコン膜中に少ない炭素を導入するステップを含む、請求項14の方法。
- 前記炭素豊富な膜中の前記誘電体スタックの対向側面上にソース/ドレイン領域を形成するステップをさらに含む、請求項14の方法。
- 前記ソース/ドレイン領域が注入、固体ソース拡散、もしくはプラズマドーピングの内の一つによって形成される、請求項25の方法。
- 金属低ショットキー障壁コンタクトを持つ前記炭素豊富なシリコン膜上にソース/ドレインコンタクトを形成するステップをさらに含む、請求項14の方法。
- ショットキー障壁を通るゲート誘導トンネリングによって、前記炭素豊富なシリコン膜中にソース/ドレインコンタクトを形成するステップをさらに含む、請求項14の方法。
- 前記誘電体スタックが段階的化学量論組成を含む、請求項14の方法。
- 薄膜メモリセルの各層の間に酸化物層を形成するステップをさらに含む、請求項14の方法。
- 前記炭素豊富なシリコン膜がチャネル領域を含み、前記チャネル領域は“U”型である、請求項14の方法。
- 基板上に垂直に積層される複数の薄膜フィンFETメモリセルを含むスタック不揮発性薄膜メモリデバイスであって、前記各メモリセル層が
前記基板上に垂直に形成されるソース/ドレイン領域のペア、
前記基板の上、および前記垂直なソース/ドレイン領域のペアの間に垂直に形成されるチャネル領域であって、前記チャネル領域層は所定の炭素濃度を持つアモルファスシリコンを含む、チャネル領域、
前記チャネル領域の周囲に形成される誘電体スタック、
前記誘電体スタックの周囲に形成される制御ゲート、
を含むメモリセルである、スタック不揮発性薄膜メモリデバイス。 - 前記誘電体スタックと前記制御ゲートとの間に形成される酸化物層をさらに含む、請求項32のデバイス。
- 前記制御ゲートが2ゲート構造として形成される、請求項32のデバイス。
- 前記制御ゲートが3ゲート構造として形成される、請求項32のデバイス。
- 前記酸化物層の厚みが、前記制御ゲートが2制御ゲートもしくは3制御ゲートであるかどうかを決定する、請求項33のデバイス。
- 前記2制御ゲートでは、前記チャネル領域の前記上面上の前記酸化物層が、前記側壁上の前記酸化物層よりも薄い、請求項36のデバイス。
- 前記3制御ゲートでは前記酸化物層が実質的に等しい厚みである、請求項36のデバイス。
- スタック不揮発性薄膜メモリデバイスを製造するための方法であって、前記方法は、
基板の上に垂直に積層される複数の薄膜フィンFETメモリセル層を形成するステップを含み、各メモリセル層を形成するための前記方法は、
前記基板上に垂直にソース/ドレイン領域のペアを形成するステップ、
前記基板の上、および前記垂直なソース/ドレイン領域のペアの間に垂直にアモルファスシリコン膜のチャネル領域を形成するステップ、
炭素豊富なシリコン膜を形成するために、前記アモルファスシリコン膜中の炭素濃度を増加させるステップ、
前記チャネル領域の周囲に誘電体スタックを形成するステップ、
前記誘電体スタックの周囲に制御ゲートを形成するステップ、
を含む、方法。 - 前記炭素濃度を増加させるステップが、続いて形成される垂直に積層された薄膜フィンFETメモリセル層毎に少なくなるパーセンテージで前記炭素濃度を増加させるステップを含む、請求項39の方法。
- 制御信号を発生させるプロセッサと、
前記プロセッサに接続されるメモリデバイスであって、前記デバイスは、基板の上に形成される薄膜メモリセルの複数の層を含むメモリアレイを持ち、各層は、
前記基板の上に形成される絶縁層、
所定の炭素濃度を持つアモルファスシリコン層を含む、前記絶縁層の上に形成されるチャネル領域層、
前記チャネル領域層の上に形成される誘電体スタック、
前記誘電体スタックの上に形成される制御ゲート、
を含む、メモリデバイスと、
を含むメモリシステム。 - 前記誘電体スタックの対向側面上で前記チャネル領域層中に形成されるソース/ドレイン領域のペアをさらに含む、請求項41のシステム。
- 前記所定の炭素濃度が、続いて形成される薄膜メモリセルの層毎に減少する、請求項41のシステム。
- 前記メモリアレイがNAND型アーキテクチャを含む、請求項41のシステム。
- 前記メモリアレイがNOR型アーキテクチャを含む、請求項41のシステム。
- 少なくとも二つのメモリデバイスと、複数のコンタクトを含むメモリモジュールであって、
前記メモリデバイスは各々、基板の上に形成される薄膜メモリセルの複数の層を持つメモリアレイを含み、各層は、
前記基板の上に形成される絶縁層、
所定の炭素濃度を持つアモルファスシリコン層を含み、前記絶縁層の上に形成されるチャネル領域層、
前記チャネル領域層の上に形成される誘電体スタック、
前記誘電体スタックの上に形成される制御ゲート、
を含み、
前記複数のコンタクトは、前記メモリアレイとホストシステムとの間に選択的コンタクトを提供するように構成される、
メモリモジュール。 - 前記ホストシステムに応じて前記メモリデバイスの動作を制御するための、前記メモリアレイに接続されるメモリコントローラをさらに含む、請求項46のメモリモジュール。
- メモリデバイスと、ハウジングと、複数のコンタクトを含むメモリモジュールであって、
前記メモリデバイスは、基板の上に形成される薄膜メモリセルの複数の層を持つメモリアレイを含むメモリデバイスであって、各層は、
前記基板の上に形成される絶縁層、
所定の炭素濃度を持つアモルファスシリコン層を含み、前記絶縁層の上に形成されるチャネル領域層、
前記チャネル領域層の上に形成される誘電体スタック、
前記誘電体スタックの上に形成される制御ゲート、
を含み、
前記ハウジングは前記メモリデバイスを囲み、
前記複数のコンタクトは、前記ハウジングに接続され、前記メモリアレイとホストシス
テムとの間に選択的コンタクトを提供するように構成される、
メモリモジュール。
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JP2013521664A (ja) * | 2010-03-04 | 2013-06-10 | ユニバーシティ オブ フロリダ リサーチ ファンデーション インコーポレーティッド | 電気的浸透性ソース層を含む半導体デバイス及びこれの製造方法 |
US10089930B2 (en) | 2012-11-05 | 2018-10-02 | University Of Florida Research Foundation, Incorporated | Brightness compensation in a display |
WO2014174937A1 (ja) * | 2013-04-24 | 2014-10-30 | 独立行政法人産業技術総合研究所 | 異種材料接合を有する半導体デバイス |
JPWO2014174937A1 (ja) * | 2013-04-24 | 2017-02-23 | 国立研究開発法人産業技術総合研究所 | 異種材料接合を有する半導体デバイス |
JP2022501838A (ja) * | 2018-09-17 | 2022-01-06 | イオン ビーム サービス | 炭化ケイ素上のmosfetチャネルにおけるキャリアの移動度を改善する装置 |
JP7100771B2 (ja) | 2018-09-17 | 2022-07-13 | イオン ビーム サービス | 炭化ケイ素上のmosfetチャネルにおけるキャリアの移動度を改善する装置 |
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US9111798B2 (en) | 2015-08-18 |
WO2007109068A3 (en) | 2008-01-31 |
JP5051478B2 (ja) | 2012-10-17 |
CN101405849B (zh) | 2011-03-30 |
US20090039357A1 (en) | 2009-02-12 |
KR100997350B1 (ko) | 2010-11-29 |
US20130224923A1 (en) | 2013-08-29 |
US20140339572A1 (en) | 2014-11-20 |
KR20080114806A (ko) | 2008-12-31 |
WO2007109068A2 (en) | 2007-09-27 |
CN101405849A (zh) | 2009-04-08 |
US7439594B2 (en) | 2008-10-21 |
US7994566B2 (en) | 2011-08-09 |
US20070215954A1 (en) | 2007-09-20 |
US8404536B2 (en) | 2013-03-26 |
US20110275182A1 (en) | 2011-11-10 |
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