JP2009290129A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2009290129A
JP2009290129A JP2008143526A JP2008143526A JP2009290129A JP 2009290129 A JP2009290129 A JP 2009290129A JP 2008143526 A JP2008143526 A JP 2008143526A JP 2008143526 A JP2008143526 A JP 2008143526A JP 2009290129 A JP2009290129 A JP 2009290129A
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heat sink
cut
semiconductor device
solder
resin sealing
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JP5077076B2 (en
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Shigeo Yoshizaki
茂雄 吉崎
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same, both of which can reduce resin remained on a determining unit and can surely ooze out solder to the determining unit. <P>SOLUTION: A semiconductor device 1 includes: a heat sink 2 having a surface 2A, a backside 2B faced thereto, and a determining unit 20 for determining solder wettability provided on a part of a side face 2C; a semiconductor chip 4 arranged on the surface 2A of the heat sink 2; a lead 5 electrically connected to a terminal 40 of the semiconductor chip 4; and a resin sealing portion 7 which exposes the backside 2B and the determining unit 20 of the heat sink 2 and covers the semiconductor chip 4, a part of the lead 5, and the surface 2A of the heat sink 2. The determining unit of the heat sink 2 is arranged at a position not beyond the outermost of the resin sealing portion 7; and a plating film 205, which has wettability with respect to solder extending from the surface 2A side to the backside 2B side of the heat sink 2 at part of the surface of the determining unit 20 and reduces adhesive force of resin of the resin sealing portion 7 as compared with another part of the determining unit 20, is provided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に放熱板を備えた面実装型の半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a surface-mount type semiconductor device provided with a heat sink and a manufacturing method thereof.

放熱板（ヒートシンク）を有する面実装型の半導体装置が知られている。この種の半導体装置にはパワートランジスタ、制御用モノリシックＩＣ等の半導体チップが封止（モールド）され、半導体チップの動作により発生する熱は放熱板を通して外部に放熱される。   A surface-mount type semiconductor device having a heat sink (heat sink) is known. In this type of semiconductor device, a semiconductor chip such as a power transistor or a control monolithic IC is sealed (molded), and heat generated by the operation of the semiconductor chip is radiated to the outside through a heat radiating plate.

半導体装置は、放熱板と、その表面上にマウントされた半導体チップと、半導体チップの側面周囲に配設されたリードと、半導体チップの端子とリードとの間を電気的に接続するワイヤと、放熱板、半導体チップ及びリードの一部（インナーリード）をモールドする樹脂封止部とを備えている。放熱板の半導体チップがマウントされた領域を除く表面上及び放熱板の一部の領域を除く側面上は樹脂封止部によりモールドされる。放熱板の裏面は、半導体装置を実装基板に実装する際に半田を介して接合するために、樹脂を形成しないで露出されている。   The semiconductor device includes a heat sink, a semiconductor chip mounted on the surface thereof, a lead disposed around the side surface of the semiconductor chip, a wire for electrically connecting the terminal and the lead of the semiconductor chip, A heat sink, a semiconductor chip, and a resin sealing part for molding a part of the lead (inner lead) are provided. The surface of the heat sink excluding the region where the semiconductor chip is mounted and the side surface excluding a part of the heat sink are molded by a resin sealing portion. The back surface of the heat radiating plate is exposed without forming a resin so as to be bonded via solder when the semiconductor device is mounted on the mounting substrate.

半導体装置の製造過程において、放熱板は、切断領域を介在して枠体及びその他の複数の放熱板に連接された（一体に製造された）ロール材から切断され、個々に分割されたものである。分割前のロール材の表面には半田に対する濡れ性を持つメッキ膜が施されている。メッキ膜には例えばニッケル（Ｎｉ）膜が使用されている。   In the manufacturing process of a semiconductor device, a heat sink is cut from a roll material connected to a frame body and a plurality of other heat sinks through a cutting region (manufactured integrally), and is divided individually. is there. A plated film having wettability to solder is applied to the surface of the roll material before division. For example, a nickel (Ni) film is used as the plating film.

放熱板の切断領域の切断面は、樹脂封止部から露出させ、半導体装置を実装した際の半田接合の良否を判定する判定部として使用されている。すなわち、放熱板の裏面に形成した半田が半田リフローによって判定部（切断面）に染み出した場合には良好な半田接合であると判定され、染み出していない場合には半田接合が不良であると判定される。この判定は、いわゆる外観検査であり、目視により人為的に行われ、又はカメラやコンピュータを利用して自動的に行われる。   The cut surface of the cutting area of the heat radiating plate is exposed from the resin sealing portion, and is used as a determination unit that determines whether solder bonding is good or not when the semiconductor device is mounted. That is, when the solder formed on the back surface of the heat sink exudes to the judgment part (cut surface) by solder reflow, it is determined that the solder joint is good, and when it does not exude, the solder joint is poor. It is determined. This determination is a so-called appearance inspection, and is performed manually by visual inspection or automatically using a camera or a computer.

なお、この種の半導体装置に関しては、例えば下記特許文献１に記載されている。
特開平１０−２２９１５８号公報 This type of semiconductor device is described, for example, in Patent Document 1 below.
JP-A-10-229158

しかしながら、前述の半導体装置においては、以下の点について配慮がなされていなかった。半導体装置の製造過程において、レジンモールド法を利用して樹脂封止部を成型した後、判定部にも樹脂封止部の樹脂が付着するので、この樹脂残りを取り除く工程が組み込まれている。この樹脂残りはパンチング加工により取り除かれる。ところが、この判定部の樹脂残りを確実に取り除くことが困難であった。特に、放熱板の切断領域の裏面から放熱板の板厚方向の一部の領域、つまり外観検査において半田の染み出しを確認する領域の樹脂残りを取り除くことができない。このため、外観検査において、判定部の半田の染み出しを確認することが難しいので、半田接合の良否を正確に行うことが困難であった。   However, in the semiconductor device described above, no consideration has been given to the following points. In the manufacturing process of the semiconductor device, after the resin sealing portion is molded using the resin mold method, the resin of the resin sealing portion adheres to the determination portion. This resin residue is removed by punching. However, it has been difficult to reliably remove the resin residue from the determination portion. In particular, it is not possible to remove a resin residue in a partial region in the thickness direction of the heat sink from the back surface of the cut region of the heat sink, that is, a region where solder exudation is confirmed in appearance inspection. For this reason, in the appearance inspection, it is difficult to confirm the exudation of the solder in the determination unit, and thus it is difficult to accurately perform the solder joint.

本発明者は、判定部の樹脂残りの原因を以下の通り解析した。半導体装置の製造過程において、リードが連接されたリードフレームと放熱板が連接されたロール材とをかしめにより接合した後にロール材の切断領域が切断され、ロール材（枠体）から放熱板が分離される。この放熱板を枠体から分離するための切断には、ロール材を台座上に取り付け、切断領域において放熱板を枠体からパンチにより切り落とす打抜き加工が使用される。この切断面を観察すると、打抜き加工が開始されてから暫くの間は判定部の切断面は表面側から裏面側に向かって板厚方向に細かな筋が入る剪断面であるが、打抜き加工の終了間近に判定部の切断面はザラザラと荒れた破断面に変化していた。すなわち、この破断面と樹脂とが強固に接着され、破断面において樹脂残りが発生する。   The inventor has analyzed the cause of the remaining resin in the determination section as follows. In the semiconductor device manufacturing process, the lead frame connected with the lead and the roll material connected with the heat sink are joined together by caulking, and then the cutting area of the roll material is cut to separate the heat sink from the roll material (frame). Is done. For the cutting for separating the heat radiating plate from the frame, a punching process is used in which a roll material is attached on a pedestal and the heat radiating plate is cut off from the frame by a punch in a cutting region. When this cut surface is observed, for a while after the punching process is started, the cut surface of the judgment part is a sheared surface in which fine streaks enter the thickness direction from the front surface side toward the back surface side. Near the end, the cut surface of the judgment part changed to a rough and rough fracture surface. That is, the fracture surface and the resin are firmly bonded, and a resin residue is generated on the fracture surface.

本発明は上記課題を解決するためになされたものである。従って、本発明は、判定部の樹脂残りを軽減し、判定部への半田の染み出しを確実に実行することができる半導体装置を提供することである。   The present invention has been made to solve the above problems. Accordingly, an object of the present invention is to provide a semiconductor device that can reduce the resin residue of the determination unit and reliably execute solder seepage to the determination unit.

更に、本発明は、判定部の樹脂残りを軽減し、判定部への半田の染み出しを確実に実行することができる半導体装置の製造方法を提供することである。   Furthermore, this invention is providing the manufacturing method of the semiconductor device which can reduce the resin residue of a determination part and can perform the seepage of the solder to a determination part reliably.

更に、本発明は、外観検査において、半田接合の良否判定を確実に実行することができる半導体装置の製造方法を提供することである。   It is another object of the present invention to provide a method for manufacturing a semiconductor device capable of reliably executing a solder joint quality determination in an appearance inspection.

上記課題を解決するために、本発明の実施の形態に係る第１の特徴は、半導体装置において、表面及びそれに対向する裏面を有し、側面の一部に半田濡れ性を判定する判定部を有する放熱板と、放熱板の表面上に配設された半導体チップと、半導体チップの端子に電気的に接続されたリードと、放熱板の裏面及び判定部は露出させ、半導体チップ、リードの一部及び放熱板の表面上を被覆する樹脂封止部とを備え、放熱板の判定部を樹脂封止部の最外郭を越えない位置に配設し、判定部の一部の表面において放熱板の表面側から裏面側に渡って半田に対して濡れ性を有しかつ前記判定部の他の一部の表面に比べて前記樹脂封止部の樹脂の付着力を減少するメッキ膜を備える。   In order to solve the above-mentioned problem, a first feature according to an embodiment of the present invention is that a semiconductor device includes a determination unit that has a front surface and a back surface opposite to the front surface and determines solder wettability on a part of the side surface. A heat sink, a semiconductor chip disposed on the surface of the heat sink, a lead electrically connected to a terminal of the semiconductor chip, a back surface of the heat sink and a determination portion are exposed, and one of the semiconductor chip and the lead is exposed. And a resin sealing portion that covers the surface of the heat sink, and the determination portion of the heat sink is disposed at a position that does not exceed the outermost wall of the resin seal portion, and the heat sink on a part of the surface of the determination portion A plating film that has wettability with respect to the solder from the front surface side to the back surface side and that reduces the adhesive force of the resin of the resin sealing portion compared to the other part of the surface of the determination portion.

第１の特徴に係る半導体装置において、放熱板の判定部は第１の切断面とこの第１の切断面よりも外側に突出する第２の切断面を放熱板の側面周囲に沿って備え、メッキ膜は第１の切断面に備えていることが好ましい。   In the semiconductor device according to the first feature, the determination unit of the heat sink includes a first cut surface and a second cut surface protruding outward from the first cut surface along the periphery of the side surface of the heat sink. The plating film is preferably provided on the first cut surface.

本発明の実施の形態に係る第２の特徴は、半導体装置の製造方法において、放熱板が切断領域を介在して連接された枠体において、切断領域の幅方向の一部を樹脂封止部の最外郭を越えない位置において第１の打抜き加工により切断する工程と、切断領域の第１の打抜き加工により切断された第１の切断面に半田に対して濡れ性を持つメッキ膜を形成する工程と、切断領域の幅方向の残りの一部を樹脂封止部の最外郭を越えない位置において第２の打抜き加工により切断し、枠体から放熱板を分離するとともに、切断領域の第１の切断面及び第２の打抜き加工により切断された第２の切断面を有し、半田濡れ性を判定する判定部を形成する工程とを備える。   A second feature according to the embodiment of the present invention is that, in the method of manufacturing a semiconductor device, in the frame body in which the heat sinks are connected via the cutting region, a part of the cutting region in the width direction is resin-sealed. And a plating film having wettability with respect to solder is formed on the first cut surface cut by the first punching process in the cutting region. The process and the remaining part of the cutting area in the width direction are cut by a second punching process at a position not exceeding the outermost contour of the resin sealing portion, the heat sink is separated from the frame, and the first of the cutting area And a step of forming a determination unit for determining solder wettability, and a second cut surface cut by the second punching process.

本発明の実施の形態に係る第３の特徴は、半導体装置の製造方法において、放熱板が切断領域を介在して連接された枠体において、枠体の切断領域の幅方向の一部を樹脂封止部の最外郭を越えない位置において第１の打抜き加工により切断する工程と、切断領域の第１の打抜き加工により切断された第１の切断面に、半田に対して濡れ性を有しかつ前記第１の切断面に比べて前記樹脂封止部の樹脂の接着力を減少するメッキ膜を形成する工程と、リードが連接されたリードフレームに枠体を装着する工程と、切断領域の幅方向の残りの一部を樹脂封止部の最外郭を越えない位置において第２の打抜き加工により切断し、枠体から放熱板を分離するとともに、切断領域の第１の切断面及び第２の打抜き加工により切断された第２の切断面を有し、半田濡れ性を判定する判定部を形成する工程と、放熱板の表面上に半導体チップをマウントする工程と、半導体チップの端子とリードとの間を電気的に接続する工程と、放熱板の表面に対向する裏面及び判定部は露出させ、半導体チップ、リードの一部及び放熱板の表面上を樹脂封止部により被覆する工程と、リードフレームからリードを切断する工程とを備える。   According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, in the frame body in which the heat sinks are connected via the cutting area, a part of the cutting area of the frame body in the width direction is resin. The step of cutting by the first punching process at a position not exceeding the outermost contour of the sealing portion, and the first cut surface cut by the first punching process of the cutting region have wettability to the solder And a step of forming a plating film that reduces the adhesive force of the resin of the resin sealing portion compared to the first cut surface, a step of attaching a frame to a lead frame to which leads are connected, and a cutting region The remaining part in the width direction is cut by the second punching process at a position that does not exceed the outermost contour of the resin sealing portion, the heat sink is separated from the frame body, and the first cut surface and the second cut surface of the cutting region are separated. Having a second cut surface cut by punching A step of forming a determination portion for determining solder wettability, a step of mounting a semiconductor chip on the surface of the heat sink, a step of electrically connecting the terminals and leads of the semiconductor chip, and the surface of the heat sink And a step of covering the semiconductor chip, a part of the lead and the surface of the heat sink with a resin sealing portion, and a step of cutting the lead from the lead frame.

第３の特徴に係る半導体装置の製造方法において、樹脂封止部を形成する工程の後に、リードを切断する工程を利用して樹脂封止部の判定部に付着した不必要な樹脂を除去する工程を更に備えることが好ましい。   In the semiconductor device manufacturing method according to the third feature, after the step of forming the resin sealing portion, unnecessary resin adhering to the determination portion of the resin sealing portion is removed using a step of cutting the lead. It is preferable to further include a step.

また、第３の特徴に係る半導体装置の製造方法において、リードを切断する工程の後に、実装基板の表面上に半田を介して放熱板の裏面を接合し、半田の判定部への半田濡れ性を検査する工程を更に備えたことが好ましい。   Further, in the method of manufacturing a semiconductor device according to the third feature, after the step of cutting the leads, the back surface of the heat sink is joined to the surface of the mounting substrate via solder, and the solder wettability to the determination part of the solder It is preferable to further include a step of inspecting

本発明によれば、判定部の樹脂残りを軽減し、判定部への半田の染み出しを確実に実行することができる半導体装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can reduce the resin residue of a determination part and can perform the seepage of the solder to a determination part reliably can be provided.

更に、本発明によれば、判定部の樹脂残りを軽減し、判定部への半田の染み出しを確実に実行することができる半導体装置の製造方法を提供することができる。   Furthermore, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device that can reduce the resin residue of the determination unit and reliably execute the leakage of solder to the determination unit.

更に、本発明によれば、外観検査において、半田接合の良否判定を確実に実行することができる半導体装置の製造方法を提供することができる。   Furthermore, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of reliably executing the solder joint quality determination in the appearance inspection.

次に、図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、現実のものとは異なる。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれている場合がある。   Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

また、以下に示す実施の形態はこの発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の技術的思想は各構成部品の配置等を下記のものに特定するものでない。この発明の技術的思想は、特許請求の範囲において、種々の変更を加えることができる。   Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is to arrange the components and the like as follows. Not specific. The technical idea of the present invention can be variously modified within the scope of the claims.

本発明の実施の形態は、放熱板を有するスモールアウトラインパッケージ構造を備えた樹脂封止型半導体装置（ＨＳＯＰ）に本発明を適用した例を説明するものである。   The embodiment of the present invention describes an example in which the present invention is applied to a resin-encapsulated semiconductor device (HSOP) having a small outline package structure having a heat sink.

（第１の実施の形態）
［半導体装置の構造］
図１乃至図３に示すように、本発明の第１の実施の形態に係る半導体装置１は、表面２Ａ及びそれに対向する裏面２Ｂを有し、側面２Ｃの一部に半田濡れ性を判定する判定部２０を有する放熱板２と、放熱板２の表面２Ａ上に配設された半導体チップ４と、半導体チップ４の側面に沿って配設され、半導体チップ４の端子４０に電気的に接続されたリード５と、放熱板２の裏面２Ｂ及び判定部２０は露出させ、半導体チップ４、リード５の一部（インナーリード部）５０及び放熱板２の表面２Ａ上を被覆する樹脂封止部７とを備え、放熱板２の判定部２０を樹脂封止部７の最外郭を越えない位置に配設し、判定部２０の一部の表面（第１の切断面２０１）において放熱板２の表面２Ａ側から裏面２Ｂ側に渡って半田に対して濡れ性を有しかつ判定部２０の他の一部の表面（第２の切断面２０２）に比べて樹脂封止部７の樹脂の接着力を減少するメッキ膜２０５を備える。 (First embodiment)
[Structure of semiconductor device]
As shown in FIGS. 1 to 3, the semiconductor device 1 according to the first embodiment of the present invention has a front surface 2A and a back surface 2B opposite to the front surface 2A, and determines solder wettability on a part of the side surface 2C. The heat sink 2 having the determination unit 20, the semiconductor chip 4 disposed on the surface 2 </ b> A of the heat sink 2, and disposed along the side surface of the semiconductor chip 4 and electrically connected to the terminal 40 of the semiconductor chip 4. The resin-encapsulated portion that exposes the formed lead 5, the back surface 2 </ b> B of the heat sink 2, and the determination portion 20, and covers the semiconductor chip 4, a part of the lead 5 (inner lead portion) 50 and the surface 2 </ b> A of the heat sink 2 7, the determination part 20 of the heat sink 2 is disposed at a position not exceeding the outermost contour of the resin sealing part 7, and the heat sink 2 on a part of the surface of the determination part 20 (first cut surface 201). Having wettability with respect to solder from the front surface 2A side to the back surface 2B side, and Comprising a plating film 205 to reduce the adhesive force of the resin of the resin sealing portion 7 relative to other part of the surface of the tough 20 (second cutting plane 202).

半導体チップ４は、比較的大電流を制御する、例えばパワートランジスタ、モノリシックＩＣ、制御用モノリシックＩＣ（ＭＩＣ）等である。半導体チップ４は、シリコン単結晶基板、III−Ｖ族化合物半導体基板等の基板により構成されている。半導体チップ４は、その裏面を放熱板２の表面２Ａに向かい合わせ、この表面２Ａ上に接着層３を使用して接着されている。ここで、例えばパワートランジスタ等の半導体チップ４の裏面から給電する場合には導電性を有する接着層３が使用され、例えば制御用モノリシックＩＣ等の半導体チップ４の裏面からの給電を必要としない場合には絶縁性を有する接着層３が使用される。   The semiconductor chip 4 is, for example, a power transistor, a monolithic IC, a control monolithic IC (MIC), or the like that controls a relatively large current. The semiconductor chip 4 is composed of a substrate such as a silicon single crystal substrate or a III-V group compound semiconductor substrate. The semiconductor chip 4 has its back surface facing the front surface 2A of the heat radiating plate 2 and is bonded to the front surface 2A using the adhesive layer 3. Here, for example, when power is supplied from the back surface of the semiconductor chip 4 such as a power transistor, the conductive adhesive layer 3 is used, and power supply from the back surface of the semiconductor chip 4 such as a control monolithic IC is not required. In this case, an adhesive layer 3 having insulating properties is used.

半導体チップ４の表面に配設された端子４０はボンディングパッドである。この端子４０にはワイヤ６の一端がボンディングされ、端子４０とワイヤ６との間は電気的かつ機械的に接続されている。ワイヤ６の他端はリード５のインナーリード部５０にボンディングされ、ワイヤ６とインナーリード部５０との間は電気的かつ機械的に接続されている。ワイヤ６には例えば金（Ａｕ）ワイヤ、アルミニウム（Ａｌ）ワイヤ等が使用される。   Terminals 40 arranged on the surface of the semiconductor chip 4 are bonding pads. One end of the wire 6 is bonded to the terminal 40, and the terminal 40 and the wire 6 are electrically and mechanically connected. The other end of the wire 6 is bonded to the inner lead portion 50 of the lead 5, and the wire 6 and the inner lead portion 50 are electrically and mechanically connected. For the wire 6, for example, a gold (Au) wire, an aluminum (Al) wire, or the like is used.

リード５のアウターリード部５１の一端はインナーリード部５０に連接され、アウターリード部５１の他端は樹脂封止部７の外部に引き延ばされる。インナーリード部５０、アウターリード部５１のそれぞれは同一リードフレーム（ここでは図示していない。）から切断されかつ成型されたものである。リードフレームは例えば銅（Ｃｕ）、Ｃｕ合金、鉄（Ｆｅ）−ニッケル（Ｎｉ）合金等の導電性材料により製造され、リードフレームの厚みは例えばＣｕを使用する場合には０．１ｍｍ−２．０ｍｍに設定される。   One end of the outer lead portion 51 of the lead 5 is connected to the inner lead portion 50, and the other end of the outer lead portion 51 is extended outside the resin sealing portion 7. Each of the inner lead part 50 and the outer lead part 51 is cut and molded from the same lead frame (not shown here). The lead frame is made of a conductive material such as copper (Cu), Cu alloy, iron (Fe) -nickel (Ni) alloy, and the thickness of the lead frame is 0.1 mm-2. Set to 0 mm.

放熱板２は、半導体チップ４を搭載する（マウントする）タブに相当する機能を有し、半導体チップ４の回路動作により発生する熱を樹脂封止部７の外部すなわち半導体装置１の外部に放出する機能を有する。更に、第１の実施の形態において、放熱板２は半導体チップ４に給電するための電源板としての機能も有する。従って、放熱板２には、例えば熱伝導性並びに電気伝導性に優れたＣｕ板を実用的に使用することができる。放熱板２は、リードフレームの厚さよりも厚く、例えば０．２ｍｍ−２．５ｍｍに設定される。   The heat radiating plate 2 has a function corresponding to a tab on which the semiconductor chip 4 is mounted (mounted), and releases heat generated by the circuit operation of the semiconductor chip 4 to the outside of the resin sealing portion 7, that is, outside the semiconductor device 1. It has the function to do. Further, in the first embodiment, the heat radiating plate 2 also has a function as a power source plate for supplying power to the semiconductor chip 4. Therefore, for example, a Cu plate excellent in thermal conductivity and electrical conductivity can be used for the heat radiating plate 2. The heat radiating plate 2 is thicker than the lead frame, for example, 0.2 mm-2.5 mm.

放熱板２の側面の一部、具体的には図２及び図３に示す樹脂封止部７の短辺の中央部に判定部２０が配設されている。樹脂封止部７の長辺にはリード５のアウターリード部５１が複数本規則的に配列されている。放熱板２の表面２Ａ及び側面２Ｃの大半は樹脂封止部７に被覆されている。判定部２０は、樹脂封止部７の最外郭を越えない位置すなわち樹脂封止部７の短辺においてその最も外側の表面の位置と同一の位置に配設されているか、又は短辺に窪みを設け短辺の最も外側の表面よりも内側の位置に配設されている。このように判定部２０を樹脂封止部７の最外郭から突出させないことにより、半導体装置１の実効的な長辺方向の寸法を、判定部２０の突出したサイズではなく、樹脂封止部７の外形サイズによって規定することができるので、パッケージサイズの小型化を実現することができる。   The determination part 20 is arrange | positioned in a part of side surface of the heat sink 2, specifically the center part of the short side of the resin sealing part 7 shown in FIG.2 and FIG.3. A plurality of outer lead portions 51 of the leads 5 are regularly arranged on the long side of the resin sealing portion 7. Most of the surface 2 </ b> A and the side surface 2 </ b> C of the heat sink 2 are covered with the resin sealing portion 7. The determination unit 20 is disposed at a position that does not exceed the outermost contour of the resin sealing portion 7, that is, at the short side of the resin sealing portion 7, at the same position as the position of the outermost surface, or is recessed on the short side. Is provided at a position inside the outermost surface of the short side. Thus, by preventing the determination unit 20 from projecting from the outermost outline of the resin sealing portion 7, the effective long-side dimension of the semiconductor device 1 is not the protruding size of the determination unit 20, but the resin sealing portion 7. Therefore, the package size can be reduced.

判定部２０は、放熱板２の裏面２Ｂを実装基板（図示していない。）の表面に半田を介して向かい合わせ、半田リフローすることにより、実装基板の表面に半導体装置１を実装する際に、放熱板２の裏面２Ｂから半田を染み出させ、半田の這い上がり（半田の濡れ性）を確認する領域として機能する。つまり、判定部２０に半田が這い上がっていれば半田接合が良好に行われたことを意味し、這い上がっていなければ半田接合が不良であることを意味する。この判定は製造プロセス中に組み込まれる外観検査において行われる。   When the semiconductor device 1 is mounted on the surface of the mounting substrate, the determination unit 20 faces the back surface 2B of the heat radiating plate 2 to the surface of the mounting substrate (not shown) via solder and performs solder reflow. The solder exudes from the back surface 2B of the heat radiating plate 2 and functions as a region for confirming solder creeping (solder wettability). That is, if the solder is climbing up to the determination unit 20, it means that the soldering has been satisfactorily performed, and if not, it means that the soldering is not good. This determination is performed in an appearance inspection incorporated in the manufacturing process.

判定部２０は、製造方法において説明するが、製造プロセス（組立プロセス）中において放熱板２とそれを連接する枠体との間の切断領域、及び放熱板２とそれに連接された他の半導体装置１に使用される放熱板２との間の切断領域で切断された放熱板２の端面（切断面）に相当する。第１の実施の形態に係る半導体装置１において、判定部２０は、第１の切断面２０１とこの第１の切断面２０１よりも外側に突出する第２の切断面２０２を放熱板２の側面２Ｃの周囲に沿って備え、第１の切断面２０１にメッキ膜２０５を備えている。すなわち、判定部２０は切断面が異なり段差を有する２つの第１の切断面２０１及び第２の切断面２０２を備え、第１の実施の形態においては、窪んでいる方の第１の切断面２０１にメッキ膜２０５が形成され、突出している方の第２の切断面２０２には切断面がそのまま露出されメッキ膜２０５が形成されていない。   Although the determination unit 20 will be described in the manufacturing method, in the manufacturing process (assembly process), the cutting region between the heat sink 2 and the frame body that connects the heat sink 2 and other semiconductor devices connected to the heat sink 2. 1 corresponds to an end surface (cut surface) of the heat sink 2 cut at a cutting area between the heat sink 2 and the heat sink 2. In the semiconductor device 1 according to the first embodiment, the determination unit 20 uses the first cut surface 201 and the second cut surface 202 protruding outward from the first cut surface 201 as the side surface of the heat sink 2. A plating film 205 is provided on the first cut surface 201. That is, the determination unit 20 includes two first cut surfaces 201 and a second cut surface 202 having different steps and different steps, and in the first embodiment, the first cut surface that is recessed. A plated film 205 is formed on 201, and the cut surface is exposed as it is on the protruding second cut surface 202, and the plated film 205 is not formed.

メッキ膜２０５には半田との濡れ性が良い材料が使用される。更にこのメッキ膜２０５は、第１の切断面２０１の特に破断面２０１Ｂ（図１２参照。）及び第２の切断面２０２の特に破断面２０２Ｂ（図１２参照。）に比べて、メッキ膜２０５の表面における樹脂封止部７の樹脂（樹脂残り）の接着力を減少する機能を備える。メッキ膜２０５には、例えば、半田の組成に錫（Ｓｎ）系の材料が使用されている場合には、メッキ膜２０５にはＮｉメッキ膜が使用される。Ｎｉメッキ膜の厚さは例えば１μｍ−１０μｍに設定される。また、メッキ膜２０５には、Ａｕメッキ膜、Ａｇメッキ膜、パラジウム（Ｐｄ）メッキ膜等も使用することができる。なお、メッキ膜２０５は、実装の際に半田接合が行われる放熱板２の裏面２Ｂには少なくも配設されており、更に第１の実施の形態においては判定部２の第２の切断面２０２以外の表面２Ａ、裏面２Ｂ及び側面２Ｃの大半に配設されている。   A material having good wettability with solder is used for the plating film 205. Further, the plating film 205 is formed by comparing the plating film 205 with the fracture surface 201B (see FIG. 12) of the first cut surface 201 and the fracture surface 202B (see FIG. 12) of the second cut surface 202. A function of reducing the adhesive force of the resin (resin residue) of the resin sealing portion 7 on the surface is provided. For the plating film 205, for example, when a tin (Sn) -based material is used for the solder composition, a Ni plating film is used for the plating film 205. The thickness of the Ni plating film is set to 1 μm to 10 μm, for example. As the plating film 205, an Au plating film, an Ag plating film, a palladium (Pd) plating film, or the like can be used. In addition, the plating film 205 is disposed at least on the back surface 2B of the heat radiating plate 2 to which solder bonding is performed at the time of mounting. Further, in the first embodiment, the second cut surface of the determination unit 2 is provided. It is disposed on most of the front surface 2A, the back surface 2B, and the side surface 2C other than 202.

樹脂封止部７は、半導体チップ４、放熱板２の表面２Ａ、放熱板２の判定部２０以外の側面２Ｃ、ワイヤ６及びリード５のインナーリード部５０を被覆する。樹脂封止部７は、例えばトランスファーモールド法を使用して成型され、例えばエポキシ系樹脂を使用して成型される。   The resin sealing portion 7 covers the semiconductor chip 4, the surface 2 </ b> A of the heat sink 2, the side surface 2 </ b> C other than the determination portion 20 of the heat sink 2, the wire 6, and the inner lead portion 50 of the lead 5. The resin sealing portion 7 is molded using, for example, a transfer molding method, and is molded using, for example, an epoxy resin.

［半導体装置の製造方法（組立方法）］
次に、前述の第１の実施の形態に係る半導体装置１の製造方法を説明する。 [Manufacturing Method of Semiconductor Device (Assembly Method)]
Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described.

まず最初に、放熱板２が切断領域２２を介在して連接された枠体２１が準備される（図４参照。）。この枠体２１は、切断領域２２を介して複数連ねた放熱体２を支持し、一般的に帯状のロール材として製作されている。枠体２１は、放熱体２及び切断領域２２とともに一体に製造されており、例えばＣｕ板材を打抜き加工又はエッチング加工により形成したものである。   First, a frame body 21 is prepared in which the heat radiating plates 2 are connected via a cutting region 22 (see FIG. 4). The frame body 21 supports a plurality of the radiators 2 connected via the cutting region 22 and is generally manufactured as a belt-shaped roll material. The frame body 21 is integrally manufactured together with the heat radiating body 2 and the cutting region 22, and is formed by punching or etching a Cu plate material, for example.

図４に示すように、枠体２１において、樹脂封止部４０の最外郭を越えない位置であって切断領域２２の幅方向の一部が第１の打抜き加工により切断され、第１の切断面２０１が形成される。第１の実施の形態において、切断領域２２の幅方向とは、帯状のロール材が延伸する方向（図４中、左右方向）に対して直交する方向（図４中、上下方向）である。また、切断領域２２の幅方向の一部とは、切断領域２２の幅方向の約半分の部分であり、少なくとも判定部２０として、半田の染み出しによる這い上がりが確認できるに足りる部分である。なお、第１の切断面２０１は、第１の実施の形態においては打抜き加工により形成されているが、本発明はこれに限定されるものではなく、ロール材として製作される際の打抜き加工又はエッチング加工により予め形成されていてもよい。この予め形成された判定部２０の第１の切断面２０１に相当する一部の領域は、前述のように外観検査における半田接合の良否判定に使用される。ここで、第１の切断面２０１が打抜き加工により製作された場合には切断面という表現が適切であり、エッチング加工により製作された場合には第１の切断面２０１はエッチング加工面と表現した方が適切であるが、第１の実施の形態においては、このエッチング加工面も第１の切断面２０１の概念に含めて説明する。   As shown in FIG. 4, in the frame body 21, a part in the width direction of the cutting region 22 that is a position not exceeding the outermost contour of the resin sealing portion 40 is cut by the first punching process, and the first cutting is performed. A surface 201 is formed. In the first embodiment, the width direction of the cutting region 22 is a direction (vertical direction in FIG. 4) orthogonal to a direction in which the belt-shaped roll material extends (horizontal direction in FIG. 4). The part of the cutting region 22 in the width direction is a half of the cutting region 22 in the width direction, and at least the determination unit 20 is a portion enough to confirm the creeping up due to the solder seepage. The first cut surface 201 is formed by punching in the first embodiment. However, the present invention is not limited to this, and the first cut surface 201 is punched when manufactured as a roll material. It may be formed in advance by etching. A part of the region corresponding to the first cut surface 201 of the determination unit 20 formed in advance is used for determining the quality of solder bonding in the appearance inspection as described above. Here, when the first cut surface 201 is manufactured by punching, the expression “cut surface” is appropriate. When the first cut surface 201 is manufactured by etching, the first cut surface 201 is expressed as an etching processed surface. In the first embodiment, this etched surface is also included in the concept of the first cut surface 201 and will be described.

図５に示すように、少なくとも放熱板２の裏面２Ｂ上及び判定部２０として使用される第１の切断面２０１上にメッキ膜２０５が形成される。ここでは、放熱板２の表面２Ａ上、裏面２Ｂ上及び側面２Ｃ上の全面にメッキ膜２０５が形成される。メッキ膜２０５にはＮｉメッキ膜が使用される。   As shown in FIG. 5, a plating film 205 is formed on at least the back surface 2 </ b> B of the heat radiating plate 2 and the first cut surface 201 used as the determination unit 20. Here, the plating film 205 is formed on the entire surface of the heat sink 2 on the front surface 2A, the back surface 2B, and the side surface 2C. A Ni plating film is used for the plating film 205.

次に、図６に示すように、枠体２１に連接された放熱板２がリードフレーム５５に装着される。ここでは、放熱板２の表面２Ａに形成した突出部（符号は特に付けない。）をリードフレーム５５に形成した穴部（同様に、符号は特に付けない。）に通し、突出部先端をかしめることにより、放熱板２がリードフレーム５５に装着される。   Next, as shown in FIG. 6, the heat sink 2 connected to the frame body 21 is attached to the lead frame 55. Here, the protrusions (not particularly labeled) formed on the surface 2A of the heat radiating plate 2 are passed through the holes (similarly, not labeled) in the lead frame 55, and the tip of the protrusion is extended. By crimping, the heat sink 2 is attached to the lead frame 55.

図７に示すように、枠体２１において、切断領域２２の幅方向の残りの一部が第２の打抜き加工により切断され、枠体２１から放熱板２が分離される。この分離された放熱板２のメッキ膜２０５が形成された第１の切断面２０１及び第２の打抜き加工により切断された第２の切断面２０２は判定部２０として機能する。この判定部２０は、後工程の外観検査工程において、半田接合の良否の判定に使用される。なお、判定部２０として実質的に機能する領域はメッキ膜２０５が形成された第１の切断面２０１である。   As shown in FIG. 7, in the frame body 21, the remaining part of the cutting region 22 in the width direction is cut by the second punching process, and the heat radiating plate 2 is separated from the frame body 21. The first cut surface 201 on which the separated plating film 205 of the heat sink 2 is formed and the second cut surface 202 cut by the second punching process function as the determination unit 20. The determination unit 20 is used to determine whether the solder joint is good or bad in a visual inspection process that is a subsequent process. Note that the region that substantially functions as the determination unit 20 is the first cut surface 201 on which the plating film 205 is formed.

ここで、第１の実施の形態においては、放熱板２の枠体２１からの分離工程、すなわち放熱板２の切断工程が、半導体チップ４の放熱板２への装着前に行われる。放熱板２の厚さが厚く設定されているので、半導体チップ４を放熱板２に装着した後にこのような厚みのある放熱板２を切断した場合には、半導体チップ４に切断時のストレスが加わり、半導体チップ４に悪影響を及ぼすおそれがある。第１の実施の形態に係る製造方法においてはこのような悪影響を防止することができる。   Here, in the first embodiment, the step of separating the heat sink 2 from the frame body 21, that is, the step of cutting the heat sink 2 is performed before the semiconductor chip 4 is mounted on the heat sink 2. Since the thickness of the heat sink 2 is set to be thick, when the heat sink 2 having such a thickness is cut after the semiconductor chip 4 is mounted on the heat sink 2, the stress at the time of cutting is applied to the semiconductor chip 4. In addition, the semiconductor chip 4 may be adversely affected. Such an adverse effect can be prevented in the manufacturing method according to the first embodiment.

図８に示すように、放熱板２の表面２Ａ上に接着層３を介在させて半導体チップ４が装着される（半導体チップ４のマウントが行われる）。引き続き、図９に示すように、半導体チップ４の端子４０にワイヤ６の一端がボンディングされ、リード５のインナーリード部５０にワイヤ６の他端がボンディングされ、双方の間がワイヤ６により電気的に接続される。   As shown in FIG. 8, the semiconductor chip 4 is mounted on the surface 2A of the heat sink 2 with the adhesive layer 3 interposed (the semiconductor chip 4 is mounted). Subsequently, as shown in FIG. 9, one end of the wire 6 is bonded to the terminal 40 of the semiconductor chip 4, the other end of the wire 6 is bonded to the inner lead portion 50 of the lead 5, and the both are electrically connected by the wire 6. Connected to.

トランスファーモールド法が使用され、図１０に示すように、樹脂封止部７が形成される。樹脂封止部７は、放熱板２の裏面２Ｂ及び判定部２０を露出させ、放熱板２の側面２Ｃ、表面２Ａ、半導体チップ４、リード５のインナーリード部５０及びワイヤ６を被覆する。判定部２０は樹脂封止部２０の最外郭よりも樹脂封止部２０の内部側に位置する。   A transfer molding method is used to form the resin sealing portion 7 as shown in FIG. The resin sealing portion 7 exposes the back surface 2B and the determination portion 20 of the heat radiating plate 2 and covers the side surface 2C, the surface 2A of the heat radiating plate 2, the semiconductor chip 4, the inner lead portion 50 of the lead 5, and the wire 6. The determination unit 20 is located on the inner side of the resin sealing unit 20 with respect to the outermost shell of the resin sealing unit 20.

図１１に示すように、リードフレーム５５において、第１回目のリード加工（一次分離加工）が行われるとともに、この工程を兼用して判定部２０の表面に付着された樹脂封止部７の樹脂残りが除去される。第１回目のリード加工は、リード５の隣り合って配設されたアウターリード部５１を相互に連結する連結部５６を取り除く加工である。連結部５６は樹脂封止部７を形成する際の樹脂の流出を堰き止めるダムとしての機能を有する。第１回目のリード加工は打抜き加工により行われる。   As shown in FIG. 11, in the lead frame 55, the first lead processing (primary separation processing) is performed, and the resin of the resin sealing portion 7 attached to the surface of the determination portion 20 also using this step. The rest is removed. The first lead processing is processing for removing the connecting portion 56 that connects the outer lead portions 51 arranged adjacent to each other of the leads 5. The connecting portion 56 has a function as a dam for blocking outflow of resin when the resin sealing portion 7 is formed. The first lead processing is performed by punching.

判定部２０の樹脂残りの除去は、以下の通り行われる。まず最初に、判定部２０は、図１２に示すように、第１の打抜き加工により生成された第１の切断面２０１と、この第１の切断面２０１の表面上に形成されたメッキ膜２０５と、第２の打抜き加工により生成された第２の切断面２０２とを備えている。ここでは、放熱板２の裏面２Ｂに台座を当接させ、放熱板２の表面２Ａから裏面２Ｂに向かってパンチを移動させて第１の打抜き加工及び第２の打抜き加工が行われている。従って、第１の切断面２０１には、表面２Ａから裏面２Ｂの直前まで剪断面２０１Ａが生成され、裏面２Ｂに近い領域には破断面２０１Ｂが生成される。同様に、第２の切断面２０２には、表面２Ａから裏面２Ｂの直前まで剪断面２０２Ａが生成され、裏面２Ｂに近い領域には破断面２０２Ｂが生成される。   Removal of the resin residue of the determination unit 20 is performed as follows. First, as illustrated in FIG. 12, the determination unit 20 includes a first cut surface 201 generated by the first punching process and a plating film 205 formed on the surface of the first cut surface 201. And a second cut surface 202 generated by the second punching process. Here, the pedestal is brought into contact with the back surface 2B of the heat radiating plate 2, and the punch is moved from the front surface 2A of the heat radiating plate 2 toward the back surface 2B, so that the first punching process and the second punching process are performed. Therefore, on the first cut surface 201, a shear surface 201A is generated from the front surface 2A to immediately before the back surface 2B, and a fracture surface 201B is generated in a region near the back surface 2B. Similarly, on the second cut surface 202, a shear surface 202A is generated from the front surface 2A to immediately before the back surface 2B, and a fracture surface 202B is generated in a region near the back surface 2B.

判定部２０の第２の切断面２０２の樹脂封止部７の形成に伴う樹脂残り７０の除去においては、図１３に示すように放熱板２の表面２Ａに台座１０が当接され、図１４に示すように放熱板２の裏面２Ｂから表面２Ａに向かってパンチガイド１１に沿ってパンチ１２が移動する。このパンチ１２の移動、すなわちパンチング加工によって、第２の切断面２０２に付着された樹脂残り７０が取り除かれる。ところが、第２の切断面２０２において、剪断面２０２Ａに付着した樹脂残り７０は剥離されるが、破断面２０２Ｂの粗い表面と樹脂残り７０との接着性が強固であり、破断面２０２Ｂに付着した樹脂残り７０の一部が更に樹脂残り７１として破断面２０２Ｂに強固に付着する。この樹脂残り７１の部分は、半田との濡れ性を持たないので、半田の染み出しによる半田の這い上がりを生じない。すなわち、樹脂残り７１の部分において、半田接合の良否を判定することが難しい。   In the removal of the resin residue 70 accompanying the formation of the resin sealing portion 7 on the second cut surface 202 of the determination unit 20, the pedestal 10 is brought into contact with the surface 2A of the heat sink 2 as shown in FIG. As shown in FIG. 2, the punch 12 moves along the punch guide 11 from the back surface 2B of the heat radiating plate 2 toward the front surface 2A. By the movement of the punch 12, that is, punching, the resin residue 70 attached to the second cut surface 202 is removed. However, in the second cut surface 202, the resin residue 70 attached to the shear surface 202A is peeled off, but the adhesion between the rough surface of the fracture surface 202B and the resin residue 70 is strong, and the resin residue 70 is adhered to the fracture surface 202B. A part of the resin residue 70 further adheres firmly to the fracture surface 202B as the resin residue 71. Since the remaining resin portion 71 has no wettability with the solder, the solder does not creep up due to the leakage of the solder. That is, it is difficult to determine whether the solder bonding is good or not in the resin remaining 71 portion.

一方、判定部２０の第１の切断面２０１の樹脂封止部７の形成に伴う樹脂残り７０の除去においては、図１５及び図１６に示すように放熱板２の裏面２Ｂから表面２Ａに向かってパンチガイド１１に沿ってパンチ１２が移動すると、このパンチング加工によって、剪断面２０１Ａ及び破断面２０２Ｂにメッキ膜２０５を介して付着された樹脂残り７０は完全に剥離される。第１の切断面２０１の剪断面２０１Ａ及び破断面２０１Ｂがメッキ膜２０５により完全に覆われ、メッキ膜２０５と樹脂残り７０との間の接着性は破断面２０２Ｂと樹脂残り７０との間の接着性に比べて遙かに小さいので、樹脂残り７０が付着してもこの樹脂残り７０は剥離し易い。従って、判定部２０の第１の切断面２０１には樹脂残り７０が存在せず、更にメッキ膜２０５が形成されているので、半田との濡れ性が良好で、半田の染み出しによる半田の這い上がりが生じ易い。すなわち、第１の切断面２０１の部分において、半田接合の良否を判定することができる。   On the other hand, in the removal of the resin residue 70 that accompanies the formation of the resin sealing portion 7 of the first cut surface 201 of the determination unit 20, as shown in FIG. 15 and FIG. When the punch 12 moves along the punch guide 11, the remaining resin 70 attached to the shearing surface 201 </ b> A and the fracture surface 202 </ b> B via the plating film 205 is completely peeled off by this punching process. The shear surface 201A and the fracture surface 201B of the first cut surface 201 are completely covered with the plating film 205, and the adhesion between the plating film 205 and the resin residue 70 is the adhesion between the fracture surface 202B and the resin residue 70. Therefore, even if the resin residue 70 adheres, the resin residue 70 is easily peeled off. Therefore, since the resin residue 70 does not exist on the first cut surface 201 of the determination unit 20 and the plating film 205 is further formed, the wettability with the solder is good, and the solder oozes due to the seepage of the solder. Rising is likely to occur. That is, whether or not the solder joint is good can be determined at the first cut surface 201.

次に、リード５のアウターリード部５１の少なくとも実装基板の端子に半田接合される領域に半田メッキ膜が形成される（図示しない。）。そして、図１７に示すように、リードフレーム５５に第２回目のリード加工（二次分離加工）が行われ、リードフレーム５５からリード５のアウターリード部５１が切り離されるとともに、アウターリード部５１が成型される。この段階において、第１の実施の形態に係る半導体装置１が完成する。   Next, a solder plating film is formed in a region of the outer lead portion 51 of the lead 5 which is soldered to at least the terminal of the mounting substrate (not shown). Then, as shown in FIG. 17, second lead processing (secondary separation processing) is performed on the lead frame 55, the outer lead portion 51 of the lead 5 is separated from the lead frame 55, and the outer lead portion 51 is Molded. At this stage, the semiconductor device 1 according to the first embodiment is completed.

次に、このように製造された半導体装置１は実装基板９の表面上に実装される。半導体装置１を実装基板９に実装する場合には、実装基板９の表面上に配設された端子９１上に半導体装置１のアウターリード部５１を載置し、更に別の端子９２に放熱板２の裏面２Ｂを当接する。そして、半田リフローが行われる。図１８に示すように、放熱板２の裏面２Ｂ側から判定部２０の第１の切断面２０１に半田８が染み出し半田８が這い上がってきた場合、アウターリード部５１の半田接合並びに放熱板２の半田接合が良好に行われたと判定される。逆に、判定部２０の第１の切断面２０１に半田８の這い上がりを確認することができない場合には半田接合が不良であると判定される。これらの判定は、外観検査工程において人為的な目視により行われ、又カメラ及びコンピュータを用いた自動認識により行われる。   Next, the semiconductor device 1 manufactured in this way is mounted on the surface of the mounting substrate 9. When the semiconductor device 1 is mounted on the mounting substrate 9, the outer lead portion 51 of the semiconductor device 1 is placed on the terminal 91 disposed on the surface of the mounting substrate 9, and the heat sink is further connected to another terminal 92. 2 is contacted. Then, solder reflow is performed. As shown in FIG. 18, when the solder 8 oozes out from the back surface 2 </ b> B side of the heat sink 2 to the first cut surface 201 of the determination unit 20 and the solder 8 crawls up, solder bonding of the outer lead portion 51 and the heat sink It is determined that the soldering of No. 2 has been performed satisfactorily. Conversely, if it is not possible to confirm the creeping up of the solder 8 on the first cut surface 201 of the determination unit 20, it is determined that the solder joint is defective. These determinations are made by human visual inspection in the appearance inspection process, or by automatic recognition using a camera and a computer.

［半導体装置の特徴］
このように構成される第１の実施の形態に係る半導体装置１においては、判定部２０の一部（第１の切断面２０１）にメッキ膜２０５を備えたので、判定部２０の樹脂残り７１を軽減し、判定部２０への半田８の染み出しを確実に実行することができる。更に、第１の実施の形態に係る半導体装置１においては、判定部２０が樹脂封止部７の最外郭を越えない位置に配設されているので、パッケージサイズが樹脂封止部７の外形サイズにより決定することができ、小型化を図ることができる。 [Features of semiconductor devices]
In the semiconductor device 1 according to the first embodiment configured as described above, since the plating film 205 is provided on a part (the first cut surface 201) of the determination unit 20, the remaining resin 71 of the determination unit 20 is provided. And the bleeding of the solder 8 to the determination unit 20 can be reliably executed. Furthermore, in the semiconductor device 1 according to the first embodiment, since the determination unit 20 is disposed at a position that does not exceed the outermost contour of the resin sealing unit 7, the package size is the outer shape of the resin sealing unit 7. The size can be determined and the size can be reduced.

更に、第１の実施の形態に係る半導体装置１の製造方法においては、放熱板２の切断領域２２に第１の打抜き加工により第１の切断面２０１を形成し、この第１の切断面２０１の表面に少なくともメッキ膜２０５を形成し、この後に切断領域２２に第２の打抜き加工により第２の切断面２０２を形成するとともに枠体２１から放熱板２を分離したので、判定部２０の樹脂残り７１を軽減し、判定部２０への半田８の染み出しを確実に実行することができる。   Furthermore, in the method for manufacturing the semiconductor device 1 according to the first embodiment, the first cut surface 201 is formed in the cut region 22 of the heat sink 2 by the first punching process. Since at least the plating film 205 is formed on the surface of the substrate, and then the second cut surface 202 is formed in the cutting region 22 by the second punching process and the heat sink 2 is separated from the frame body 21, the resin of the determination unit 20 The remaining 71 can be reduced, and the solder 8 can ooze out to the determination unit 20 with certainty.

更に、第１の実施の形態に係る半導体装置１の製造方法においては、外観検査工程において、判定部２０への半田８の染み出しを確実に実行することができるので、半田接合の良否判定を確実に実行することができる。   Furthermore, in the manufacturing method of the semiconductor device 1 according to the first embodiment, since the solder 8 can be surely oozed out to the determination unit 20 in the appearance inspection process, it is determined whether the solder joint is good or bad. It can be executed reliably.

（第２の実施の形態）
本発明の第２の実施の形態は、前述の第１の実施の形態に係る半導体装置１において、放熱板２上に複数の半導体チップを搭載した例を説明するものである。 (Second Embodiment)
The second embodiment of the present invention describes an example in which a plurality of semiconductor chips are mounted on the heat sink 2 in the semiconductor device 1 according to the first embodiment described above.

［半導体装置の第１の構造］
図１９に示すように、第２の実施の形態の第１の構造に係る半導体装置１は、放熱板２の表面２Ａ上に配設された第１の半導体チップ４１と、この第１の半導体チップ４１上に積層された第２の半導体チップ４２とを備えている。すなわち、半導体装置１は、複数の第１の半導体チップ４１及び第２の半導体チップ４２を１つの樹脂封止部７により封止している。 [First Structure of Semiconductor Device]
As shown in FIG. 19, the semiconductor device 1 according to the first structure of the second embodiment includes a first semiconductor chip 41 disposed on the surface 2 </ b> A of the heat sink 2, and the first semiconductor. And a second semiconductor chip 42 stacked on the chip 41. That is, in the semiconductor device 1, a plurality of first semiconductor chips 41 and second semiconductor chips 42 are sealed with one resin sealing portion 7.

第１の半導体チップ４１は例えばＭＯＳＦＥＴを集積化した制御用モノリシックＩＣ等であり、第２の半導体チップ４２は例えば制御用モノリシックＩＣにより動作が制御されるＩＧＢＴ等のパワー系デバイスである。なお、本発明は、制御用モノリシックＩＣやＩＧＢＴに限定されるものではない。   The first semiconductor chip 41 is, for example, a control monolithic IC in which MOSFETs are integrated, and the second semiconductor chip 42 is, for example, a power system device such as an IGBT whose operation is controlled by the control monolithic IC. The present invention is not limited to a control monolithic IC or IGBT.

第１の半導体チップ４１の端子４０１はリード５にワイヤ５を通して電気的に接続される。第２の半導体チップ４２の端子４０２はリード５にワイヤ５を通して電気的に接続される。   The terminal 401 of the first semiconductor chip 41 is electrically connected to the lead 5 through the wire 5. The terminal 402 of the second semiconductor chip 42 is electrically connected to the lead 5 through the wire 5.

［半導体装置の第２の構造］
図２０に示すように、第２の実施の形態の第２の構造に係る半導体装置１は、放熱板２の表面２Ａ上に配設された第１の半導体チップ４１と、この第１の半導体チップ４１とは異なる領域において放熱板２の表面２Ａ上に配設された第２の半導体チップ４２と、更に第１の半導体チップ４１と第２の半導体チップ４２との間の領域において放熱板２の表面２Ａ上に配設された第３の半導体チップ４３とを備えている。すなわち、半導体装置１は、複数の第１の半導体チップ４１、第２の半導体チップ４２及び第３の半導体チップ４３を１つの樹脂封止部７により封止している。 [Second Structure of Semiconductor Device]
As shown in FIG. 20, the semiconductor device 1 according to the second structure of the second embodiment includes a first semiconductor chip 41 disposed on the surface 2A of the heat sink 2 and the first semiconductor. The second semiconductor chip 42 disposed on the surface 2A of the heat sink 2 in a region different from the chip 41, and further, the heat sink 2 in a region between the first semiconductor chip 41 and the second semiconductor chip 42. And a third semiconductor chip 43 disposed on the surface 2A. That is, in the semiconductor device 1, a plurality of first semiconductor chips 41, second semiconductor chips 42, and third semiconductor chips 43 are sealed with one resin sealing portion 7.

第１の半導体チップ４１及び第２の半導体チップは例えばＩＧＢＴ等のパワー系デバイスである。第３の半導体チップ４３は例えばＩＧＢＴ等のパワー系デバイスの動作を制御する制御用モノリシックＩＣ等である。   The first semiconductor chip 41 and the second semiconductor chip are power devices such as IGBTs. The third semiconductor chip 43 is, for example, a control monolithic IC that controls the operation of a power device such as an IGBT.

第２の実施の形態に係る半導体装置１においては、基本的には第１の実施の形態に係る半導体装置１と同様の判定部２０を備えており、第１の実施の形態に係る半導体装置１により得られる作用効果と同様の効果を奏することができる。   The semiconductor device 1 according to the second embodiment basically includes the determination unit 20 similar to that of the semiconductor device 1 according to the first embodiment, and the semiconductor device according to the first embodiment. The same effect as that obtained by 1 can be obtained.

（その他の実施の形態）
上記のように、本発明を複数の実施の形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものでない。本発明は様々な代替実施の形態、実施例及び運用技術に適用することができる。 (Other embodiments)
As described above, the present invention has been described with a plurality of embodiments. However, the description and the drawings, which form a part of this disclosure, do not limit the present invention. The present invention can be applied to various alternative embodiments, examples, and operational technologies.

本発明の第１の実施の形態に係る半導体装置の断面図（図２に示すＦ１−Ｆ１切断線により切断した断面図）である。It is sectional drawing (sectional drawing cut | disconnected by the F1-F1 cutting line shown in FIG. 2) of the semiconductor device which concerns on the 1st Embodiment of this invention. 図１に示す半導体装置の斜視図である。FIG. 2 is a perspective view of the semiconductor device shown in FIG. 1. 図１に示す半導体装置の底面図（図２に示す矢印Ｆ３方向から見た図）である。FIG. 3 is a bottom view of the semiconductor device shown in FIG. 1 (viewed from the direction of arrow F3 shown in FIG. 2). 第１の実施の形態に係る半導体装置の製造方法を説明する第１の工程図であり、放熱板が連接された枠体の要部平面図である。It is a 1st process figure explaining the manufacturing method of the semiconductor device concerning a 1st embodiment, and is a principal part top view of a frame with which a heat sink was connected. 第２の工程図であり、枠体の要部平面図である。It is a 2nd process drawing and is a principal part top view of a frame. 第３の工程図であり、枠体及びリードフレームの要部平面図である。It is a 3rd process drawing and is a principal part top view of a frame and a lead frame. 第４の工程図であり、枠体の要部平面図である。It is a 4th process drawing and is a principal part top view of a frame. 第５の工程図であり、半導体チップ、リードフレーム及び放熱板の要部断面図である。FIG. 10 is a fifth process diagram, and is a cross-sectional view of main parts of a semiconductor chip, a lead frame, and a heat sink. 第６の工程図であり、半導体チップ、リードフレーム及び放熱板の要部断面図である。FIG. 10 is a sixth process diagram, and is a cross-sectional view of main parts of a semiconductor chip, a lead frame, and a heat sink. 第７の工程図であり、半導体チップ、リードフレーム、放熱板及び樹脂封止部の要部断面図である。FIG. 10 is a seventh process diagram, and is a sectional view of main parts of a semiconductor chip, a lead frame, a heat sink, and a resin sealing portion. 第８の工程図であり、リードフレーム及び樹脂封止部の要部平面図である。It is an 8th process drawing and is a principal part top view of a lead frame and a resin sealing part. 第９の工程図であり、判定部の要部斜視図である。It is a 9th process drawing and is a principal part perspective view of a judgment part. 第１０の工程図であり、判定部（第２の切断面）の樹脂残りの状態を示す要部断面図である。It is a 10th process drawing and is a principal part sectional view showing the state of the resin remaining of the judgment part (second cut surface). 第１１の工程図であり、判定部（第２の切断面）の樹脂残りの剥離状態を示す要部断面図である。It is an 11th process drawing and is a principal part sectional view showing the peeling state of the resin residue of the judgment part (second cut surface). 第１２の工程図であり、判定部（第１の切断面）の樹脂残りの状態を示す要部断面図である。It is a 12th process drawing and is a principal part sectional view showing the state of the resin remaining of a judgment part (first cut surface). 第１３の工程図であり、判定部（第１の切断面）の樹脂残りの剥離状態を示す要部断面図である。It is a 13th process drawing and is a principal part sectional view showing the peeling state of the resin residue of the judgment part (first cut surface). 第１４の工程図であり、半導体装置の側面図である。It is a 14th process drawing and is a side view of a semiconductor device. 第１５の工程図であり、外観検査工程における判定部及び実装基板の要部斜視図である。It is a 15th process drawing and is a principal part perspective view of a judgment part and a mounting board in an appearance inspection process. 本発明の第２の実施の形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. 第２の実施の形態に係る半導体装置の斜視図である。It is a perspective view of the semiconductor device which concerns on 2nd Embodiment.

符号の説明Explanation of symbols

１…半導体装置
２…放熱板
２Ａ…表面
２Ｂ…裏面
２Ｃ…側面
２０…判定部
２０１…第１の切断面
２０１Ａ、２０２Ａ…剪断面
２０１Ｂ、２０２Ｂ…破断面
２０２…第２の切断面
２０５…メッキ膜
２１…枠体
２２…切断領域
４、４１−４３…半導体チップ
４０…端子
５…リード
５１…インナーリード部
５２…アウターリード部
５５…リードフレーム
６…ワイヤ
７…樹脂封止部
７０、７１…樹脂残り
８…半田
９…実装基板
９１、９２…端子 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Heat sink 2A ... Front surface 2B ... Back surface 2C ... Side surface 20 ... Determination part 201 ... 1st cut surface 201A, 202A ... Shear surface 201B, 202B ... Fracture surface 202 ... 2nd cut surface 205 ... Plating Film 21 ... Frame 22 ... Cutting region 4, 41-43 ... Semiconductor chip 40 ... Terminal 5 ... Lead 51 ... Inner lead part 52 ... Outer lead part 55 ... Lead frame 6 ... Wire 7 ... Resin sealing part 70, 71 ... Resin remainder 8 ... Solder 9 ... Mounting board 91, 92 ... Terminal

Claims (6)

表面及びそれに対向する裏面を有し、側面の一部に半田濡れ性を判定する判定部を有する放熱板と、
前記放熱板の前記表面上に配設された半導体チップと、
前記半導体チップの端子に電気的に接続されたリードと、
前記放熱板の前記裏面及び前記判定部は露出させ、前記半導体チップ、前記リードの一部及び前記放熱板の前記表面上を被覆する樹脂封止部と、を備え、
前記放熱板の前記判定部を前記樹脂封止部の最外郭を越えない位置に配設し、前記判定部の一部の表面において前記放熱板の前記表面側から前記裏面側に渡って半田に対して濡れ性を有しかつ前記判定部の他の一部の表面に比べて前記樹脂封止部の樹脂の付着力を減少するメッキ膜を備えていることを特徴とする半導体装置。 A heat sink having a front surface and a back surface facing it, and having a determination part for determining solder wettability on a part of the side surface;
A semiconductor chip disposed on the surface of the heat sink;
A lead electrically connected to a terminal of the semiconductor chip;
The rear surface of the heat sink and the determination portion are exposed, and the semiconductor chip, a part of the lead, and a resin sealing portion that covers the surface of the heat sink,
The determination part of the heat radiating plate is disposed at a position not exceeding the outermost contour of the resin sealing part, and solder is applied from the front side to the back side of the heat radiating plate on a part of the surface of the determination part. A semiconductor device comprising a plating film that has wettability to the resin and that reduces the adhesive force of the resin in the resin sealing portion as compared to the other part of the surface of the determination portion. 前記放熱板の前記判定部は第１の切断面とこの第１の切断面よりも外側に突出する第２の切断面を前記放熱板の前記側面周囲に沿って備え、前記メッキ膜は前記第１の切断面に備えていることを特徴とする請求項１に記載の半導体装置。   The determination portion of the heat sink includes a first cut surface and a second cut surface protruding outward from the first cut surface along the periphery of the side surface of the heat sink, and the plating film includes the first cut surface. The semiconductor device according to claim 1, wherein the semiconductor device is provided on one cut surface. 放熱板が切断領域を介在して連接された枠体において、前記切断領域の幅方向の一部を樹脂封止部の最外郭を越えない位置において第１の打抜き加工により切断する工程と、
前記切断領域の前記第１の打抜き加工により切断された第１の切断面に半田に対して濡れ性を持つメッキ膜を形成する工程と、
前記切断領域の幅方向の残りの一部を前記樹脂封止部の最外郭を越えない位置において第２の打抜き加工により切断し、前記枠体から前記放熱板を分離するとともに、前記切断領域の前記第１の切断面及び前記第２の打抜き加工により切断された第２の切断面を有し、半田濡れ性を判定する判定部を形成する工程と、
を備えたことを特徴とする半導体装置の製造方法。 A step of cutting a part of the cutting region in the width direction by a first punching process at a position not exceeding the outermost contour of the resin sealing portion in the frame body in which the heat sink is connected via the cutting region;
Forming a plating film having wettability with respect to solder on the first cut surface cut by the first punching of the cut region;
The remaining part in the width direction of the cutting region is cut by a second punching process at a position not exceeding the outermost contour of the resin sealing portion, the heat sink is separated from the frame body, and the cutting region A step of forming a determination unit that has the first cut surface and the second cut surface cut by the second punching process and determines solder wettability;
A method for manufacturing a semiconductor device, comprising: 放熱板が切断領域を介在して連接された枠体において、前記枠体の前記切断領域の幅方向の一部を樹脂封止部の最外郭を越えない位置において第１の打抜き加工により切断する工程と、
前記切断領域の前記第１の打抜き加工により切断された第１の切断面に、半田に対して濡れ性を有しかつ前記第１の切断面に比べて前記樹脂封止部の樹脂の接着力を減少するメッキ膜を形成する工程と、
リードが連接されたリードフレームに前記枠体を装着する工程と、
前記切断領域の幅方向の残りの一部を前記樹脂封止部の最外郭を越えない位置において第２の打抜き加工により切断し、前記枠体から前記放熱板を分離するとともに、前記切断領域の前記第１の切断面及び前記第２の打抜き加工により切断された第２の切断面を有し、半田濡れ性を判定する判定部を形成する工程と、
前記放熱板の表面上に半導体チップをマウントする工程と、
前記半導体チップの端子と前記リードとの間を電気的に接続する工程と、
前記放熱板の前記表面に対向する裏面及び前記判定部は露出させ、前記半導体チップ、前記リードの一部及び前記放熱板の前記表面上を前記樹脂封止部により被覆する工程と、
前記リードフレームから前記リードを切断する工程と、
を備えたことを特徴とする半導体装置の製造方法。 In a frame body in which heat sinks are connected via a cutting region, a part of the frame in the width direction of the cutting region is cut by a first punching process at a position not exceeding the outermost contour of the resin sealing portion. Process,
The first cut surface cut by the first punching process of the cut region has wettability with respect to solder and has a resin adhesive force of the resin sealing portion as compared with the first cut surface. Forming a plating film that reduces
Attaching the frame to a lead frame to which leads are connected; and
The remaining part in the width direction of the cutting region is cut by a second punching process at a position not exceeding the outermost contour of the resin sealing portion, the heat sink is separated from the frame body, and the cutting region A step of forming a determination unit that has the first cut surface and the second cut surface cut by the second punching process and determines solder wettability;
Mounting a semiconductor chip on the surface of the heat sink;
Electrically connecting the terminals of the semiconductor chip and the leads;
Exposing the back surface of the heat sink opposite to the front surface and the determination portion, and covering the semiconductor chip, a part of the lead, and the surface of the heat sink with the resin sealing portion;
Cutting the lead from the lead frame;
A method for manufacturing a semiconductor device, comprising: 前記樹脂封止部を形成する工程の後に、前記リードを切断する工程を利用して前記樹脂封止部の前記判定部に付着した不必要な樹脂残りを除去する工程を更に備えたことを特徴とする請求項４に記載の半導体装置の製造方法。   After the step of forming the resin sealing portion, the method further includes a step of removing unnecessary resin residue attached to the determination portion of the resin sealing portion using a step of cutting the lead. A method for manufacturing a semiconductor device according to claim 4. 前記リードを切断する工程の後に、実装基板の表面上に半田を介して前記放熱板の前記裏面を接合し、前記半田の前記判定部への半田濡れ性を検査する工程を更に備えたことを特徴とする請求項４又は請求項５に記載の半導体装置の製造方法。   After the step of cutting the lead, the method further comprises a step of bonding the back surface of the heat sink to the surface of the mounting substrate via solder and inspecting the solder wettability of the solder to the determination unit. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is manufactured.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10229158A (en) * 1996-12-10 1998-08-25 Matsushita Electric Ind Co Ltd Semiconductor device for high frequency
JP2005005522A (en) * 2003-06-12 2005-01-06 Nec Tokin Corp Chip type capacitor and its manufacturing method, and lead frame used for capacitor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10229158A (en) * 1996-12-10 1998-08-25 Matsushita Electric Ind Co Ltd Semiconductor device for high frequency
JP2005005522A (en) * 2003-06-12 2005-01-06 Nec Tokin Corp Chip type capacitor and its manufacturing method, and lead frame used for capacitor

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