JP2009267100A - Method of manufacturing wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board by which a wiring board having a gold plating layer deposited thereon by electrolytic plating, the plating layer having a uniform crystal structure with less thickness irregularities, can be manufactured in a highly productive manner. <P>SOLUTION: The method of manufacturing the wiring board includes the steps of: forming a plurality of insulating substrates 1 each having a wiring conductor 2 on its upper surface in a mother substrate 10 large enough to include the insulating substrates 1 configured such that the insulating substrates 1 are lined up vertically and horizontally with cutting areas A interposed on boundaries between the insulating substrates 1; forming a first tie-bar T1 electrically connected to the wiring conductor 2 on the upper surface of each cutting area A while forming a second tie-bar T2 electrically connected to the first tie-bar T1 on the undersurface of the cutting area A; and supplying electric charges to the wiring conductor 2 via the first and second tie-bars T1 and T2 for electrolytic plating to deposit a gold plating layer G on the exposed surface of the wiring conductor 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は半導体素子を搭載するための配線基板の製造方法に関し、より詳細には絶縁基板の上面に半導体素子の電極が電気的に接続される配線導体を有するとともに該配線導体の露出表面に電解めっきによる金めっき層が被着されて成る配線基板の製造方法に関するものである。   The present invention relates to a method of manufacturing a wiring board for mounting a semiconductor element. More specifically, the present invention has a wiring conductor to which an electrode of a semiconductor element is electrically connected on an upper surface of an insulating substrate, and electrolysis is performed on an exposed surface of the wiring conductor. The present invention relates to a method of manufacturing a wiring board formed by depositing a gold plating layer by plating.

従来より半導体集積回路素子等の半導体素子を搭載する配線基板として、図６に示すように、ガラスクロス基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた複数の絶縁板や絶縁層を積層して成り、中央部に半導体素子Ｓを収容するための貫通孔Ｃを有する絶縁基板１の上面から下面にかけて半導体素子Ｓの電極が電気的に接続される銅箔や銅めっき層から成る配線導体２が配設された配線基板本体３と、配線基板本体３の下面に貫通孔Ｃを塞ぐように接着剤層４を介して接合されており、貫通孔Ｃ内に露出する上面に半導体素子Ｓが搭載される銅板から成る金属放熱板５とから成る配線基板が知られている。   Conventionally, as a wiring board on which a semiconductor element such as a semiconductor integrated circuit element is mounted, a plurality of insulating plates in which a glass cloth base material is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin as shown in FIG. A copper foil or a copper plating in which the electrodes of the semiconductor element S are electrically connected from the upper surface to the lower surface of the insulating substrate 1 having a through hole C for accommodating the semiconductor element S in the center. The wiring board main body 3 in which the wiring conductor 2 composed of layers is disposed is bonded to the lower surface of the wiring board main body 3 via the adhesive layer 4 so as to close the through hole C, and is exposed in the through hole C. There is known a wiring board including a metal heat radiating plate 5 made of a copper plate on which a semiconductor element S is mounted.

なお、この配線基板は、配線基板本体３における上面から下面にかけて上下の配線導体２を接続するためのスルーホールめっき導体が被着されたスルーホール６が形成されており、スルーホール６の内部には熱硬化性樹脂から成る孔埋め樹脂７が充填されている。さらに孔埋め樹脂７の一部は絶縁基板１の上面およびその表面の配線導体２の一部を覆ってレジスト層を形成しており、絶縁基板１の下面およびその表面の配線導体２は同じく熱硬化性樹脂から成るレジスト層８で被覆されている。   The wiring board has a through hole 6 formed with a through hole plating conductor for connecting the upper and lower wiring conductors 2 from the upper surface to the lower surface of the wiring board body 3. Is filled with a hole-filling resin 7 made of a thermosetting resin. Further, a part of the hole filling resin 7 covers the upper surface of the insulating substrate 1 and a part of the wiring conductor 2 on the surface thereof to form a resist layer, and the lower surface of the insulating substrate 1 and the wiring conductor 2 on the surface thereof are similarly heated. It is covered with a resist layer 8 made of a curable resin.

そして、この配線基板は、貫通孔Ｃ内に露出する金属放熱板５の上面に半導体素子Ｓを接着剤９を介して搭載するとともに半導体素子Ｓの電極と絶縁基板１上面に露出する配線導体２とをボンディングワイヤＷを介して接続した後、貫通孔Ｃ内およびその周辺の上面に図示しない封止樹脂を半導体素子ＳおよびボンディングワイヤＷを覆うように被着させることにより製品としての半導体装置となる。なお、この配線基板においては、配線導体２とボンディングワイヤＷとの接続を良好なものとするために絶縁基板１の上面に形成された配線導体２の露出表面には通常、金めっき層Ｇが電解めっき法により被着されている。   In this wiring board, the semiconductor element S is mounted on the upper surface of the metal heat dissipating plate 5 exposed in the through hole C via the adhesive 9, and the electrode of the semiconductor element S and the wiring conductor 2 exposed on the upper surface of the insulating substrate 1 are provided. And a semiconductor device as a product by attaching a sealing resin (not shown) on the upper surface in and around the through hole C so as to cover the semiconductor element S and the bonding wire W. Become. In this wiring board, the gold plating layer G is usually formed on the exposed surface of the wiring conductor 2 formed on the upper surface of the insulating substrate 1 in order to improve the connection between the wiring conductor 2 and the bonding wire W. It is applied by electrolytic plating.

ところで、このような配線基板において配線導体２の露出表面に金めっき層Ｇを電解めっき法により被着させるには、従来以下のような方法が採用されていた。先ず、図７および図８に示すように、配線基板本体３の複数個分を包含する大きさの母基板２０中に、絶縁基板１の上面に配線導体２を有する配線基板本体３の複数個を各境界に切断領域Ａを介在させて縦横の並びに一体的に配列形成するとともに切断領域Ａの上面に配線導体２に電気的に接続されたタイバーＴを形成する。   By the way, in order to deposit the gold plating layer G on the exposed surface of the wiring conductor 2 in such a wiring board by the electrolytic plating method, the following method has been conventionally employed. First, as shown in FIGS. 7 and 8, a plurality of wiring board bodies 3 having wiring conductors 2 on the upper surface of the insulating substrate 1 in a mother board 20 having a size including a plurality of wiring board bodies 3. Are formed in an integrated manner vertically and horizontally with a cutting area A interposed at each boundary, and a tie bar T electrically connected to the wiring conductor 2 is formed on the upper surface of the cutting area A.

次に図９に示すように、切断領域ＡをめっきレジストＲ１で覆った状態でタイバーＴを介して配線導体２に電荷を供給して電解めっきすることにより配線導体２の露出表面に金めっき層Ｇを被着する。   Next, as shown in FIG. 9, a gold plating layer is formed on the exposed surface of the wiring conductor 2 by supplying a charge to the wiring conductor 2 through the tie bar T and electrolytic plating with the cutting region A covered with the plating resist R1. G is applied.

次に、めっきレジストＲ１を剥離した後、図１０に示すように、切断領域Ａの上面を露出させるエッチングレジストＲ２を被着させた状態でタイバーＴをエッチング除去し、次にエッチングレジストＲ２を剥離した後、図１１に示すように、母基板２０の切断領域Ａをダイシングマシンやルータ等の切断装置を用いて切断除去し、複数の配線基板本体３を個片に分離する。このような工程を経て絶縁基体１上面の配線導体２の露出表面に金めっき層Ｇが電解めっき法により被着された個片の配線基板本体３を得、しかる後、配線基板本体３の下面に金属放熱版５を接着剤層４を介して接合することにより図６に示したような配線基板が完成する。 Next, after the plating resist R1 is peeled off, as shown in FIG. 10, the tie bar T is removed by etching with the etching resist R2 exposing the upper surface of the cutting region A, and then the etching resist R2 is peeled off. After that, as shown in FIG. 11, the cutting area A of the mother board 20 is cut and removed by using a cutting device such as a dicing machine or a router, and the plurality of wiring board main bodies 3 are separated into individual pieces. Through these steps, an individual wiring board body 3 in which a gold plating layer G is deposited on the exposed surface of the wiring conductor 2 on the upper surface of the insulating substrate 1 by electrolytic plating is obtained, and then the lower surface of the wiring board body 3 is obtained. The metal heat dissipation plate 5 is bonded to the metal via the adhesive layer 4 to complete the wiring board as shown in FIG.

しかしながら、このような方法により配線基板を製作する場合、母基板２０に形成した切断領域Ａが無駄となることから、一枚の母基板からより多くの配線基板を得ようとすると切断領域Ａの幅をできるだけ狭いものとする必要がある。ところが切断領域Ａの幅を狭いものとした場合、切断領域Ａに形成するタイバーＴの幅も必然的に狭いものとなってしまう。このようにタイバーＴの幅が狭いものとなるとタイバーＴの電気抵抗が極めて高いものとなり、その結果、タイバーＴを介して配線導体２に電荷を供給して電解めっきする際に、各配線導体２に十分な電荷を良好に供給することができず、金めっき層Ｇの厚みが大きくばらついたり、金めっき層Ｇの結晶が不均一となったりして、その結果、配線導体２と半導体素子Ｓの電極とをボンディングワイヤＷを介して良好に接続することが困難となる。
特開平１１−２０４９２１号公報 However, when the wiring board is manufactured by such a method, the cutting area A formed on the mother board 20 is wasted, so that it is necessary to obtain more wiring boards from one mother board. The width needs to be as narrow as possible. However, when the width of the cutting area A is narrow, the width of the tie bar T formed in the cutting area A is inevitably narrow. Thus, when the width of the tie bar T becomes narrow, the electric resistance of the tie bar T becomes extremely high. As a result, when the electric charge is supplied to the wiring conductor 2 via the tie bar T and electrolytic plating is performed, each wiring conductor 2 As a result, the thickness of the gold plating layer G varies greatly or the crystal of the gold plating layer G becomes non-uniform. As a result, the wiring conductor 2 and the semiconductor element S It becomes difficult to connect these electrodes to each other through the bonding wires W.
Japanese Patent Application Laid-Open No. 11-204921

本発明は、かかる問題点に鑑み案出されたものであり、その課題は、絶縁基板の上面に形成された配線導体の露出表面に厚みばらつきが少なく、かつ均一な結晶の金めっき層が電解めっき法により被着された配線基板を生産性高く製造することが可能な配線基板の製造方法を提供することにある。   The present invention has been devised in view of such problems, and the problem is that the exposed surface of the wiring conductor formed on the upper surface of the insulating substrate has little thickness variation and a uniform crystalline gold plating layer is electrolyzed. An object of the present invention is to provide a method of manufacturing a wiring board capable of manufacturing a wiring board deposited by a plating method with high productivity.

本発明の配線基板の製造方法は、絶縁基板の上面に半導体素子の電極が電気的に接続される配線導体を有するとともに該配線導体の露出表面に金めっき層が被着されて成る配線基板の製造方法であって、前記絶縁基板の複数個分を包含する大きさの母基板中に、上面に前記配線導体を有する前記絶縁基板の複数個を該絶縁基板の境界に切断領域を介在させて縦横の並びに一体的に形成するとともに、前記切断領域の上面に前記配線導体に電気的に接続された第１のタイバーおよび前記切断領域の下面に前記切断領域を貫通するスルーホール導体を介して前記第１のタイバーと電気的に接続された第２のタイバーを形成し、前記第１および第２のタイバーを介して前記配線導体に電荷を供給して電解めっきすることにより前記配線導体の露出表面に前記金めっき層を被着する工程を含むことを特徴とするものである。   A method of manufacturing a wiring board according to the present invention includes a wiring board having a wiring conductor to which an electrode of a semiconductor element is electrically connected on an upper surface of an insulating substrate, and a gold plating layer being deposited on an exposed surface of the wiring conductor. In the manufacturing method, a plurality of the insulating substrates having the wiring conductors on the upper surface are inserted into a mother substrate having a size including a plurality of the insulating substrates, and a cutting region is interposed at the boundary of the insulating substrate. The first and second tie bars that are integrally formed vertically and horizontally and electrically connected to the wiring conductor on the upper surface of the cutting region and the through hole conductor that penetrates the cutting region on the lower surface of the cutting region A second tie bar electrically connected to the first tie bar is formed, an electric charge is supplied to the wiring conductor via the first and second tie bars, and electrolytic plating is performed, thereby exposing the exposed surface of the wiring conductor. It is characterized in that it comprises the step of depositing said gold plating layer.

本発明の配線基板の製造方法によれば、母基板における切断領域の上面のみならず下面にもタイバーを設け、これらの上下のタイバーを介して各絶縁基板の配線導体に電荷を供給して電解めっきすることにより配線導体の露出表面に金めっき層を被着させることから、切断領域の幅が狭いものであったとしても、タイバーの電気抵抗を低いものとして各配線導体に必要な電荷を良好に供給することができ、その結果、配線導体の露出表面に厚みばらつきが少なく、かつ均一な結晶の金めっき層が被着された配線基板を生産性高く製造することができる。   According to the method for manufacturing a wiring board of the present invention, tie bars are provided not only on the upper surface but also on the lower surface of the cutting area of the mother board, and electric charges are supplied to the wiring conductors of the respective insulating boards via these upper and lower tie bars to perform electrolysis. Since the gold plating layer is deposited on the exposed surface of the wiring conductor by plating, even if the width of the cutting area is narrow, the electric resistance of the tie bar is low and the electric charge necessary for each wiring conductor is good As a result, it is possible to manufacture a wiring board having a uniform thickness on the exposed surface of the wiring conductor and having a uniform crystal gold plating layer deposited thereon with high productivity.

次に、本発明の配線基板の製造方法を図１〜図５に基づいて詳細に説明する。図１は、本発明の実施形態例を示す部分上面図であり、図２は図１のＩ−Ｉ切断線における断面図、図３〜図５は図２と同じ部分を示す工程毎の断面図である。これらの工程を経て図６に示したような配線基板が製造される。なお、図中、１ａは絶縁板、１ｂは絶縁層であり、これらにより絶縁基板１が形成される。また、２ａは内層配線導体層、２ｂは表層配線導体層であり、これらにより配線導体２の一部が形成される。また、３は配線基板本体、Ａは切断領域、Ｇは金めっき層、Ｈはタイバー接続用のスルーホール、Ｔ１は第１のタイバー、Ｔ２は第２のタイバーである。   Next, the manufacturing method of the wiring board of this invention is demonstrated in detail based on FIGS. FIG. 1 is a partial top view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II in FIG. 1, and FIGS. FIG. A wiring board as shown in FIG. 6 is manufactured through these steps. In the figure, reference numeral 1a denotes an insulating plate and 1b denotes an insulating layer, which form the insulating substrate 1. Further, 2a is an inner wiring conductor layer, and 2b is a surface wiring conductor layer, and a part of the wiring conductor 2 is formed by these. 3 is a wiring board body, A is a cutting region, G is a gold plating layer, H is a through hole for connecting a tie bar, T1 is a first tie bar, and T2 is a second tie bar.

先ず、図１におよび図２に示すように、絶縁基板１の上面に配線導体２が形成された配線基板本体３の複数個がこれらの境界に切断領域Ａを介在させて縦横の並びに一体的に配列形成され、さらに切断領域Ａの上面に配線導体２に電気的に接続されたタイバーＴ１が、切断領域Ａの下面に鯛はー接続用のスルーホールＨを介して第１のタイバーに電気的に接続された第２のタイバーＴ２が形成された母基板１０を準備する。   First, as shown in FIG. 1 and FIG. 2, a plurality of wiring board bodies 3 each having a wiring conductor 2 formed on the upper surface of an insulating substrate 1 are integrated vertically and horizontally with a cutting region A interposed therebetween. In addition, the tie bar T1 electrically connected to the wiring conductor 2 on the upper surface of the cutting area A is electrically connected to the first tie bar via the through-hole H for connection to the lower surface of the cutting area A. A mother board 10 having a second tie bar T2 connected thereto is prepared.

母基板１０は、例えばガラスクロス基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた厚みが０．０６〜１．４０ｍｍの絶縁板１ａの両面に、厚みが７〜３５μｍ銅箔から成る内層配線導体層２ａと、ガラスクロス基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた厚みが０．０２〜０．１５ｍｍの絶縁層１ｂと、厚みが３〜３５μｍの銅箔および厚みが１０〜７０μｍの銅めっきから成る表層配線導体層２ｂが順次積層された縦横が５００〜６００ｍｍ程度の大型の積層基板であり、各配線基板本体３には半導体素子を収容するための貫通孔Ｃおよびスルーホール６が穿孔されており、さらに貫通孔Ｃの内壁およびスルーホール６内壁には上下の配線導体２の所定のもの同士を電気的に接続するための厚みが１０〜７０μｍの銅めっきから成る導体層が被着されている。また、各配線基板本体３の上面には配線導体２の一部を覆うとともにスルーホール６の内部を充填するエポキシ樹脂等の熱硬化性樹脂から成る孔埋め樹脂７が被着されており、各配線基板本体３の下面には、配線導体２を覆うエポキシ樹脂等の熱硬化性樹脂から成るレジスト層８が被着されている。なお、絶縁板１ａおよび絶縁層１ｂにより絶縁基板１が形成され、内層配線導体層２ａおよび表層配線導体層２ｂにより配線導体２の一部が形成される。   The mother substrate 10 has a thickness of 7 to 35 μm on both surfaces of an insulating plate 1a having a thickness of 0.06 to 1.40 mm, for example, a glass cloth base material impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. An inner wiring conductor layer 2a made of copper foil, an insulating layer 1b having a thickness of 0.02 to 0.15 mm obtained by impregnating a glass cloth base material with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, and a thickness A surface layer wiring conductor layer 2b composed of a copper foil having a thickness of 3 to 35 μm and a copper plating having a thickness of 10 to 70 μm is sequentially laminated, and is a large laminated substrate having a length and width of about 500 to 600 mm. Through holes C and through holes 6 are received, and the inner walls of the through holes C and the inner walls of the through holes 6 have predetermined upper and lower wiring conductors 2 each other. Conductor layer thickness for electrical connection is made of copper plating of 10~70μm is adhered. Further, a hole-filling resin 7 made of a thermosetting resin such as an epoxy resin that covers a part of the wiring conductor 2 and fills the inside of the through hole 6 is attached to the upper surface of each wiring board body 3. A resist layer 8 made of a thermosetting resin such as an epoxy resin that covers the wiring conductor 2 is attached to the lower surface of the wiring board body 3. The insulating substrate 1 is formed by the insulating plate 1a and the insulating layer 1b, and a part of the wiring conductor 2 is formed by the inner wiring conductor layer 2a and the surface wiring conductor layer 2b.

また、母基板１０の切断領域Ａにおける上面には上面側の表層配線導体層２ｂと同じ導体層から成る第１のタイバーＴ１が各配線基本体３を取り囲むようにして各配線基板本体３の配線導体２に電気的に接続された状態で被着形成されている。さらに、切断領域Ａの下面には、下面側の表層配線導体層２ｂと同じ導体層から成る第２のタイバーＴ２が各配線基板本体３を取り囲むようにして被着形成されており、第１のタイバーＴ１と第２のタイバーＴ２とは切断領域Ａに設けたタイバー接続用のスルーホールＨ内に被着させたスルーホール導体により電気的に接続されている。   Further, on the upper surface in the cutting area A of the mother board 10, the wiring of each wiring board body 3 is arranged so that the first tie bar T1 made of the same conductor layer as the upper surface wiring conductor layer 2b surrounds each wiring basic body 3. The electrode 2 is deposited and connected to the conductor 2. Further, a second tie bar T2 made of the same conductor layer as the surface wiring conductor layer 2b on the lower surface side is attached and formed on the lower surface of the cutting area A so as to surround each wiring board body 3. The tie bar T1 and the second tie bar T2 are electrically connected by a through-hole conductor deposited in a through-hole H for connecting a tie bar provided in the cutting area A.

このような母基板１０は、ガラスクロス基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させた厚みが０．０６〜１．４０ｍｍの絶縁板１ａの両面全面に内層配線導体層２ａ用の厚みが７〜３５μｍの銅箔が貼着された両面銅張板における前記銅箔を内層配線導体層２ａに対応する所定のパターンにエッチングし、次にこの内層配線導体層２ａが形成された両面銅張板の両面に、ガラスクロス基材にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂成分を含浸させた絶縁層１ｂ用の厚みが０．０２〜０．１５ｍｍの未硬化の絶縁シート（プリプレグ）および表層配線導体層２ｂ用の厚みが３〜３５μｍの銅箔を積層するとともに、これらをプレス装置により加圧しながら加熱して絶縁層１ｂ用の絶縁シートを熱硬化させて母基板１０用の積層体を形成し、次にこの積層体に貫通孔Ｃおよびスルーホール６、Ｈをルータやドリルマシン等の切削装置を用いて穿孔し、次に貫通孔Ｃの内壁およびスルーホール６、Ｈの内壁ならびに表層配線導体２ｂ用の銅箔の表面に無電解銅めっきおよび電解銅めっきを施すとともに所謂半田剥離法により表層配線導体層２ｂおよびスルホール導体を形成し、さらに孔埋め樹脂７およびレジスト層８を被着することにより形成される。なお、孔埋め樹脂７は、アクリル変性エポキシ樹脂等の感光性を有する熱硬化性樹脂成分を含有する樹脂ペーストを上面側の絶縁層１ｂおよび表層配線導体層２ｂの上にスルーホール６を充填するようにして塗布するとともにこれを所定のパターンに露光および現像することにより形成される。また、レジスト層８は、同じくアクリル変性エポキシ樹脂等の感光性を有する熱硬化性樹脂成分を含有する樹脂ペーストを下面側の絶縁層１ｂおよび表層配線導体層２ｂの上に塗布するとともにこれを所定のパターンに露光および現像することにより形成される。   Such a mother substrate 10 has an inner-layer wiring conductor on both surfaces of an insulating plate 1a having a thickness of 0.06 to 1.40 mm in which a glass cloth base material is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The copper foil in the double-sided copper-clad board to which a copper foil having a thickness of 7 to 35 μm for the layer 2a is adhered is etched into a predetermined pattern corresponding to the inner wiring conductor layer 2a, and then the inner wiring conductor layer 2a is A thickness of 0.02 to 0.15 mm for an insulating layer 1b in which a glass cloth base material is impregnated with a thermosetting resin component such as an epoxy resin or a bismaleimide triazine resin on both sides of the formed double-sided copper-clad plate Laminated insulating sheets (prepregs) and copper foils having a thickness of 3 to 35 μm for the surface wiring conductor layer 2b are laminated and heated while being pressed by a press device to insulate the insulating layer 1b. The sheet is thermally cured to form a laminated body for the mother board 10, and then through holes C and through holes 6 and H are drilled in the laminated body using a cutting device such as a router or a drill machine, and then penetrated. Electroless copper plating and electrolytic copper plating are applied to the inner wall of the hole C, the inner wall of the through hole 6, H, and the surface of the copper foil for the surface wiring conductor 2b, and the surface wiring conductor layer 2b and the through hole conductor are formed by a so-called solder peeling method. Further, it is formed by depositing a hole filling resin 7 and a resist layer 8. The hole-filling resin 7 fills the through-hole 6 with a resin paste containing a thermosetting resin component having photosensitivity such as an acrylic-modified epoxy resin on the insulating layer 1b and the surface wiring conductor layer 2b on the upper surface side. In this way, it is formed by applying and exposing to a predetermined pattern and developing. The resist layer 8 is also applied to a resin paste containing a thermosetting resin component having photosensitivity, such as an acrylic-modified epoxy resin, on the insulating layer 1b and the surface wiring conductor layer 2b on the lower surface side. This pattern is formed by exposure and development.

次に図３に示すように、切断領域ＡをめっきレジストＲ１で覆った状態で第１のタイバーＴ１および第２のタイバーＴ２を介して配線導体２に電荷を供給して電解めっきすることにより配線導体２の露出表面に例えばニッケルめっき層（不図示）を下地として金めっき層Ｇを被着する。このとき、第１のタイバーＴ１と第２のタイバーＴ２とはタイバー接続用のスルーホールＨ内に被着させたスルーホール導体により互いに電気的に接続されていることから、例え切断領域Ａの幅が１０〜１００μｍ程度と極めて狭いものであったとしても、第１のタイバーＴ１と第２のタイバーＴ２との合計の電気抵抗が極めて高いものとなることはなく、したがって、これらの第１のタイバーＴ１および第２のタイバーＴ２を介して各配線導体２に電荷を供給することによって各配線導体２の露出表面に厚みばらつきが少なく、且つ均一な結晶の金めっき層Ｇを被着させることができる。   Next, as shown in FIG. 3, with the cutting region A covered with the plating resist R1, the wiring conductor 2 is supplied with electric charges through the first tie bar T1 and the second tie bar T2 and electroplated. A gold plating layer G is deposited on the exposed surface of the conductor 2 with a nickel plating layer (not shown) as a base, for example. At this time, the first tie bar T1 and the second tie bar T2 are electrically connected to each other by a through-hole conductor deposited in the through-hole H for connecting the tie bar. Is very narrow, such as about 10 to 100 μm, the total electrical resistance of the first tie bar T1 and the second tie bar T2 does not become extremely high. Therefore, these first tie bars By supplying a charge to each wiring conductor 2 via T1 and the second tie bar T2, a uniform crystal gold plating layer G can be deposited on the exposed surface of each wiring conductor 2 with little variation in thickness. .

次に、めっきレジストＲ１を剥離した後、図４に示すように、切断領域Ａの上下面を露出させるエッチングレジストＲ２を被着させた状態で第１のタイバーＴ１および第２のタイバーＴ２ならびにタイバー接続用のスルーホールＨ内のスルーホール導体をエッチング除去し、次にエッチングレジストＲ２を剥離した後、図５に示すように、母基板１０の切断領域Ａをダイシングマシンやルータ等の切断装置を用いて切断除去し、複数の配線基板本体３を個片に分離する。そして最後に、配線基板本体３の下面に金属放熱板５を接着剤層４を介して接合することにより図６に示した配線基板が完成する。かくして本発明によれば、配線導体の露出表面に厚みばらつきが少なく、かつ均一な結晶の金めっき層が電解めっき法により被着された配線基板を生産性高く製造することができる。   Next, after the plating resist R1 is peeled off, as shown in FIG. 4, the first tie bar T1, the second tie bar T2, and the tie bar are attached with the etching resist R2 that exposes the upper and lower surfaces of the cutting region A. After the through-hole conductor in the connection through-hole H is removed by etching, and then the etching resist R2 is peeled off, a cutting device such as a dicing machine or a router is used to cut the cutting area A of the mother board 10 as shown in FIG. The plurality of wiring board main bodies 3 are separated into individual pieces by cutting and removing them. Finally, the metal heat sink 5 is bonded to the lower surface of the wiring board main body 3 via the adhesive layer 4 to complete the wiring board shown in FIG. Thus, according to the present invention, it is possible to manufacture with high productivity a wiring board in which the exposed surface of the wiring conductor has a small thickness variation and a uniform crystal gold plating layer is deposited by an electrolytic plating method.

なお、本発明は上述の実施形態例に限定されるものではなく、例えば上述の実施形態例では、配線導体２の露出表面に金めっき層Ｇを被着させた後、母基板１０の切断領域の第１のタイバーＴ１および第２のタイバーＴ２ならびにタイバー接続用のスルーホールＨ内のスルーホール導体をエッチング除去し、次に母基板１０の切断領域Ａを切断除去することによって複数の配線基板本体３を個片に分離したが、配線導体２の露出表面に金めっき層Ｇを被着させた後、第１のタイバーＴ１および第２のタイバーＴ２ならびにスルーホールＨ内のスルーホール導体を残したままで母基板１０の切断領域Ａを切断除去することによって複数の配線基板本体３を個片に分離してもよい。   The present invention is not limited to the above-described embodiment example. For example, in the above-described embodiment example, after the gold plating layer G is deposited on the exposed surface of the wiring conductor 2, the cutting region of the mother substrate 10 is cut. The first tie bar T1 and the second tie bar T2 and the through-hole conductor in the through-hole H for connecting the tie bar are removed by etching, and then the cutting area A of the mother board 10 is cut and removed to thereby remove a plurality of wiring board bodies. 3 is separated into individual pieces, but after the gold plating layer G is deposited on the exposed surface of the wiring conductor 2, the first tie bar T1 and the second tie bar T2 and the through-hole conductor in the through-hole H are left. The plurality of wiring board main bodies 3 may be separated into individual pieces by cutting and removing the cutting area A of the mother board 10.

本発明の配線基板の製造方法を説明するための部分上面図である。It is a partial top view for demonstrating the manufacturing method of the wiring board of this invention. 図１のＩ−Ｉ切断線における断面図である。It is sectional drawing in the II cutting | disconnection line of FIG. 本発明の配線基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the wiring board of this invention. 本発明および従来の製造方法により製造される配線基板を示す断面図である。It is sectional drawing which shows the wiring board manufactured by this invention and the conventional manufacturing method. 従来の配線基板の製造方法を説明するための上面図である。It is a top view for demonstrating the manufacturing method of the conventional wiring board. 従来の配線基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the conventional wiring board. 従来の配線基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the conventional wiring board. 従来の配線基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the conventional wiring board. 従来の配線基板の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the conventional wiring board.

符号の説明Explanation of symbols

１：絶縁基板
２：配線導体
１０：母基板
Ａ：切断領域
Ｇ：金めっき層
Ｈ：タイバー接続用のスルーホール
Ｓ：半導体素子
Ｔ１：第１のタイバー
Ｔ２：第２のタイバー 1: Insulating substrate 2: Wiring conductor 10: Mother substrate A: Cutting region G: Gold plating layer H: Through hole for connecting tie bar S: Semiconductor element T1: First tie bar T2: Second tie bar

Claims (1)

絶縁基板の上面に半導体素子の電極が電気的に接続される配線導体を有するとともに該配線導体の露出表面に金めっき層が被着されて成る配線基板の製造方法であって、前記絶縁基板の複数個分を包含する大きさの母基板中に、上面に前記配線導体を有する前記絶縁基板の複数個を該絶縁基板の境界に切断領域を介在させて縦横の並びに一体的に形成するとともに、前記切断領域の上面に前記配線導体に電気的に接続された第１のタイバーおよび前記切断領域の下面に前記切断領域を貫通するスルーホール導体を介して前記第１のタイバーと電気的に接続された第２のタイバーを形成し、前記第１および第２のタイバーを介して前記配線導体に電荷を供給して電解めっきすることにより前記配線導体の露出表面に前記金めっき層を被着する工程を含むことを特徴とする配線基板の製造方法。   A method of manufacturing a wiring board having a wiring conductor to which an electrode of a semiconductor element is electrically connected on an upper surface of an insulating substrate, and having a gold plating layer deposited on an exposed surface of the wiring conductor, In a mother board having a size including a plurality of parts, a plurality of the insulating boards having the wiring conductors on the upper surface are integrally formed vertically and horizontally with a cutting region at the boundary of the insulating board, A first tie bar electrically connected to the wiring conductor on the upper surface of the cutting region and a first tie bar electrically connected to the lower surface of the cutting region via a through-hole conductor penetrating the cutting region. A second tie bar is formed, and an electric charge is supplied to the wiring conductor via the first and second tie bars and electrolytic plating is performed to deposit the gold plating layer on the exposed surface of the wiring conductor. Method for manufacturing a wiring board, which comprises a.

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