JP2009266898A - Semiconductor element mounting structure - Google Patents

Semiconductor element mounting structure Download PDF

Info

Publication number
JP2009266898A
JP2009266898A JP2008111701A JP2008111701A JP2009266898A JP 2009266898 A JP2009266898 A JP 2009266898A JP 2008111701 A JP2008111701 A JP 2008111701A JP 2008111701 A JP2008111701 A JP 2008111701A JP 2009266898 A JP2009266898 A JP 2009266898A
Authority
JP
Japan
Prior art keywords
semiconductor element
substrate
bump
mounting structure
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008111701A
Other languages
Japanese (ja)
Other versions
JP5033045B2 (en
Inventor
Michihiko Ueda
充彦 植田
Yoshiharu Sanagawa
佳治 佐名川
Takamasa Sakai
孝昌 酒井
Shintaro Hayashi
真太郎 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Panasonic Electric Works Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Electric Works Co Ltd filed Critical Panasonic Electric Works Co Ltd
Priority to JP2008111701A priority Critical patent/JP5033045B2/en
Publication of JP2009266898A publication Critical patent/JP2009266898A/en
Application granted granted Critical
Publication of JP5033045B2 publication Critical patent/JP5033045B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element mounting structure capable of reducing a stress generated in a semiconductor element. <P>SOLUTION: The semiconductor element mounting structure is such that the semiconductor element 1 includes an outer peripheral shape of rectangle, and pads 19 of the semiconductor element 1 and connection electrodes 39 of a substrate 3 made of a ceramic substrate are joined to each other via bumps 2 each made of a solder bump at three points corresponding to three apices of an imaginary triangle defined based on the outer peripheral shape of the semiconductor element 1. The semiconductor element 1 is a semiconductor acceleration sensor chip as a kind of an MEMS (microelectro mechanical system) device, and includes a structure in which the three pads 19 are densely disposed on each three points. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体素子を基板に実装した半導体素子の実装構造に関するものである。   The present invention relates to a semiconductor element mounting structure in which a semiconductor element is mounted on a substrate.

電子デバイスの小型高機能化のニーズに伴い、層間絶縁膜として低誘電率（low-k）材料を用いたＩＣチップや、ＭＥＭＳ（Micro Electro Mechanical Systems）デバイスなどの半導体素子の開発が各所で行われているが、この種の半導体素子は、脆弱であり、基板（例えば、プリント配線基板、セラミック基板など）に実装する実装工程で発生する応力が問題視されている。   In response to the need for smaller and more functional electronic devices, IC chips using low dielectric constant (low-k) materials as interlayer dielectrics and semiconductor elements such as MEMS (Micro Electro Mechanical Systems) devices are being developed in various places. However, this type of semiconductor element is fragile, and stress generated in a mounting process for mounting on a substrate (for example, a printed wiring board, a ceramic substrate, etc.) is regarded as a problem.

また、従来から、ワイヤボンディング技術を利用する場合に比べて基板への半導体素子の実装面積を縮小するなどの目的で半導体素子を基板にフリップチップ実装してなる半導体素子の実装構造において、半導体素子と基板との接合強度を向上可能な構造が提案されている（例えば、特許文献１参照）。   Conventionally, in a semiconductor element mounting structure in which a semiconductor element is flip-chip mounted on a substrate for the purpose of reducing the mounting area of the semiconductor element on the substrate compared to the case of using wire bonding technology, the semiconductor element There has been proposed a structure capable of improving the bonding strength between the substrate and the substrate (see, for example, Patent Document 1).

ここで、上記特許文献１に記載された半導体素子の実装構造は、図７に示すように、半導体素子１に機能上必要な複数のパッド１９（１９ａ）とは別に接合強度向上用のダミーのパッド１９（１９ｂ）を設けるとともに、基板３に機能上必要な接続用電極３９（３９ａ）とは別にダミーの接続用電極３９（３９ｂ）を設け、各パッド１９と対応する接続用電極３９とをバンプ２を介して接合することで、半導体素子１と基板３との接合強度を向上させている。
特開平１０−４１６１５号公報 Here, as shown in FIG. 7, the mounting structure of the semiconductor element described in Patent Document 1 is a dummy for improving the bonding strength separately from the plurality of pads 19 (19a) necessary for the function of the semiconductor element 1. In addition to providing the pads 19 (19b), a dummy connection electrode 39 (39b) is provided on the substrate 3 in addition to the connection electrodes 39 (39a) necessary for functions, and the connection electrodes 39 corresponding to the pads 19 are provided. The bonding strength between the semiconductor element 1 and the substrate 3 is improved by bonding via the bumps 2.
Japanese Patent Laid-Open No. 10-41615

ところで、図８に示すように半導体素子１の外周部においてパッド１９が３辺に沿って配置されている場合、半導体素子１をセラミック基板からなる基板３に実装するにあたって、図９（ａ）に示すように半導体素子１の各パッド１９（図８参照）に半田バンプからなるバンプ２を形成した後、半導体素子１の各パッド１９に形成されたバンプ２と基板３における半導体素子１の実装面３ａ側の接続用電極（図示せず）とを位置合わせして、所定温度に加熱すると図９（ｂ）に示すように基板３が熱変形し、その後、常温になると図９（ｃ）に示すように基板３が熱変形のない状態に戻ろうとするが、半導体素子１は基板３が熱変形した状態で固定されていたので、半導体素子１が変形して応力が発生してしまう。   When the pads 19 are arranged along the three sides in the outer peripheral portion of the semiconductor element 1 as shown in FIG. 8, when mounting the semiconductor element 1 on the substrate 3 made of a ceramic substrate, FIG. As shown, after bumps 2 made of solder bumps are formed on each pad 19 (see FIG. 8) of semiconductor element 1, bump 2 formed on each pad 19 of semiconductor element 1 and mounting surface of semiconductor element 1 on substrate 3 are shown. When the connection electrode (not shown) on the 3a side is aligned and heated to a predetermined temperature, the substrate 3 is thermally deformed as shown in FIG. As shown, the substrate 3 tries to return to a state without thermal deformation. However, since the semiconductor element 1 is fixed with the substrate 3 being thermally deformed, the semiconductor element 1 is deformed and stress is generated.

また、図７に示した半導体素子１の実装構造は、外周形状が矩形状の半導体素子１の外周部においてパッド１９が４辺に沿って配置されているので、図８の半導体素子１の実装構造と同様に、半導体素子１と基板３との線膨張率差に起因して半導体素子１が変形して応力が発生してしまう。   Further, in the mounting structure of the semiconductor element 1 shown in FIG. 7, since the pads 19 are arranged along the four sides in the outer peripheral portion of the semiconductor element 1 having a rectangular outer peripheral shape, the mounting of the semiconductor element 1 in FIG. Similar to the structure, due to the difference in linear expansion coefficient between the semiconductor element 1 and the substrate 3, the semiconductor element 1 is deformed and stress is generated.

本発明は上記事由に鑑みて為されたものであり、その目的は、半導体素子に生じる応力を低減することが可能な半導体素子の実装構造を提供することにある。   The present invention has been made in view of the above-described reasons, and an object thereof is to provide a semiconductor element mounting structure capable of reducing stress generated in the semiconductor element.

請求項１の発明は、半導体素子を基板に実装した半導体素子の実装構造であって、半導体素子の外周形状に基づいて規定した仮想三角形の３つの頂点に対応する３箇所で半導体素子のパッドと基板の接続用電極とがバンプを介して接合されてなることを特徴とする。   The invention of claim 1 is a semiconductor element mounting structure in which a semiconductor element is mounted on a substrate, and the pad of the semiconductor element is formed at three locations corresponding to the three vertices of a virtual triangle defined based on the outer peripheral shape of the semiconductor element. The connection electrode of the substrate is bonded via a bump.

この発明によれば、半導体素子の外周形状に基づいて規定した仮想三角形の３つの頂点に対応する３箇所で半導体素子のパッドと基板の接続用電極とがバンプを介して接合されているので、基板への実装時などの温度変化に起因した基板側の変形が半導体素子に当該半導体素子の傾きとして伝わるから、半導体素子が変形するのを抑制することができ、半導体素子に生じる応力を低減することが可能となる。   According to the present invention, the pads of the semiconductor element and the connection electrodes of the substrate are joined via the bumps at three locations corresponding to the three vertices of the virtual triangle defined based on the outer peripheral shape of the semiconductor element. Since deformation on the substrate side due to temperature change such as when mounted on the substrate is transmitted to the semiconductor element as the inclination of the semiconductor element, the deformation of the semiconductor element can be suppressed, and the stress generated in the semiconductor element is reduced. It becomes possible.

請求項２の発明は、請求項１の発明において、前記３箇所のうち少なくとも１箇所では複数のバンプが密集して配置されてなることを特徴とする。   The invention of claim 2 is characterized in that, in the invention of claim 1, a plurality of bumps are densely arranged in at least one of the three places.

この発明によれば、半導体素子としてパッドの数が４個以上のものに対応でき、しかも、前記３箇所のうち複数のバンプが配置される箇所では当該複数のバンプが密集して配置されているので、半導体素子の局所的な変形を抑制することができる。   According to the present invention, it is possible to deal with a semiconductor element having four or more pads, and the plurality of bumps are densely arranged at a place where the plurality of bumps are arranged among the three places. Therefore, local deformation of the semiconductor element can be suppressed.

請求項３の発明は、請求項１または請求項２の発明において、各バンプは、半導体素子の外周部に位置していることを特徴とする。   A third aspect of the present invention is characterized in that, in the first or second aspect of the present invention, each bump is located on the outer peripheral portion of the semiconductor element.

この発明によれば、各バンプが半導体素子の外周部よりも内側に位置している場合に比べて、半導体素子を安定して固定することができる。   According to the present invention, the semiconductor element can be stably fixed as compared with the case where each bump is located inside the outer peripheral portion of the semiconductor element.

請求項４の発明は、請求項１ないし請求項３の発明において、半導体素子がＭＥＭＳデバイスであり、各パッドは、当該ＭＥＭＳデバイスにおける可動部から離間して配置されてなることを特徴とする。   According to a fourth aspect of the present invention, in the first to third aspects of the present invention, the semiconductor element is a MEMS device, and each pad is arranged apart from a movable portion in the MEMS device.

この発明によれば、基板への実装時などの温度変化に起因した可動部の変形を抑制することができ、特性変動を抑制することができる。   According to the present invention, it is possible to suppress deformation of the movable part due to temperature changes such as when mounted on a substrate, and it is possible to suppress characteristic fluctuations.

請求項５の発明は、請求項１ないし請求項４の発明において、各バンプは、半田バンプからなることを特徴とする。   According to a fifth aspect of the present invention, in the first to fourth aspects of the present invention, each bump comprises a solder bump.

この発明によれば、各バンプをＡｕバンプにより構成する場合に比べて、各バンプが柔らかくて応力緩和性が大きいので、基板への実装時などの温度変化に起因して半導体素子に生じる応力をより低減することができるとともに、接合信頼性を向上させることができる。   According to the present invention, since each bump is soft and has a large stress relaxation property as compared with the case where each bump is composed of an Au bump, the stress generated in the semiconductor element due to a temperature change during mounting on the substrate is reduced. In addition to being able to reduce, it is possible to improve the bonding reliability.

請求項６の発明は、請求項１ないし請求項４の発明において、各バンプは、シリコーン系樹脂の導電性ペーストにより形成されてなることを特徴とする。   According to a sixth aspect of the present invention, in the first to fourth aspects of the present invention, each bump is formed of a conductive paste of silicone resin.

この発明によれば、各バンプを金属により形成する場合に比べて、各バンプの弾性率が小さくて応力緩和性が大きいので、基板への実装時などの温度変化に起因して半導体素子に生じる応力をより低減することができるとともに、接合信頼性を向上させることができる。   According to the present invention, since the elastic modulus of each bump is small and the stress relaxation property is large compared with the case where each bump is formed of metal, the bump is generated in the semiconductor element due to a temperature change during mounting on the substrate. The stress can be further reduced and the bonding reliability can be improved.

請求項７の発明は、請求項１ないし請求項６の発明において、半導体素子と基板との間で各バンプを封止する樹脂からなる封止部が設けられてなることを特徴とする。   A seventh aspect of the invention is characterized in that, in the first to sixth aspects of the invention, a sealing portion made of a resin for sealing each bump is provided between the semiconductor element and the substrate.

この発明によれば、各バンプが樹脂からなる封止部により封止されているので、半導体素子と基板とのバンプによる接合信頼性を向上させることができる。   According to this invention, since each bump is sealed with the sealing part which consists of resin, the joining reliability by the bump of a semiconductor element and a board | substrate can be improved.

請求項１の発明では、半導体素子に生じる応力を低減することが可能となるという効果がある。   According to the first aspect of the invention, there is an effect that the stress generated in the semiconductor element can be reduced.

（実施形態１）
本実施形態では図１に示すように、半導体加速度センサチップからなる半導体素子１を基板（例えば、セラミック基板、ガラスエポキシ樹脂基板を用いたプリント配線基板など）３に実装した実装構造について説明する。 (Embodiment 1)
In the present embodiment, as shown in FIG. 1, a mounting structure in which a semiconductor element 1 composed of a semiconductor acceleration sensor chip is mounted on a substrate 3 (for example, a printed wiring board using a ceramic substrate or a glass epoxy resin substrate) will be described.

半導体素子１は、図１および図２に示すように、枠状（本実施形態では、矩形枠状）のフレーム部１１を備え、フレーム部１１の内側に配置される重り部１２が一表面側（図２（ｂ）における上面側）において可撓性を有する４つの短冊状の撓み部１３を介してフレーム部１１に揺動自在に支持されている。言い換えれば、半導体素子１は、枠状のフレーム部１１の内側に配置される重り部１２が重り部１２から四方へ延長された４つの撓み部１３を介してフレーム部１１に揺動自在に支持されている。ここにおいて、半導体素子１は、シリコン基板からなる支持基板１０ａ上のシリコン酸化膜からなる絶縁層（埋込酸化膜）１０ｂ上にｎ形のシリコン層（活性層）１０ｃを有するＳＯＩウェハを加工することにより形成してあり、フレーム部１１は、ＳＯＩウェハの支持基板１０ａ、絶縁層１０ｂ、シリコン層１０ｃそれぞれを利用して形成してある。これに対して、撓み部１３は、ＳＯＩウェハにおけるシリコン層１０ｃを利用して形成してあり、フレーム部１１よりも薄肉となっている。   As shown in FIG. 1 and FIG. 2, the semiconductor element 1 includes a frame portion 11 having a frame shape (in this embodiment, a rectangular frame shape), and a weight portion 12 disposed inside the frame portion 11 is on one surface side. (On the upper surface side in FIG. 2 (b)), the frame portion 11 is swingably supported via four flexible strip-shaped bending portions 13 having flexibility. In other words, the semiconductor element 1 is swingably supported by the frame portion 11 via the four flexure portions 13 extending from the weight portion 12 in the four directions, the weight portion 12 disposed inside the frame-shaped frame portion 11. Has been. Here, the semiconductor element 1 processes an SOI wafer having an n-type silicon layer (active layer) 10c on an insulating layer (buried oxide film) 10b made of a silicon oxide film on a support substrate 10a made of a silicon substrate. The frame portion 11 is formed using the support substrate 10a, the insulating layer 10b, and the silicon layer 10c of the SOI wafer. On the other hand, the bending portion 13 is formed using the silicon layer 10 c in the SOI wafer and is thinner than the frame portion 11.

重り部１２は、上述の４つの撓み部１３を介してフレーム部１１に支持された直方体状のコア部１２ａと、半導体素子１の上記一表面側から見てコア部１２ａの四隅それぞれに連続一体に連結された直方体状の４つの付随部１２ｂとを有している。言い換えれば、重り部１２は、フレーム部１１の内側面に一端部が連結された各撓み部１３の他端部が外側面に連結されたコア部１２ａと、コア部１２ａと一体に形成されコア部１２ａとフレーム部１１との間の空間に配置される４つの付随部１２ｂとを有している。つまり、各付随部１２ｂは、半導体素子１の上記一表面側から見た平面視において、フレーム部１１とコア部１２ａと互いに直交する方向に延長された２つの撓み部１３，１３とで囲まれる空間に配置されており、各付随部１２ｂそれぞれとフレーム部１１との間にはスリット１４が形成され、撓み部１３を挟んで隣り合う付随部１２ｂ間の間隔が撓み部１３の幅寸法よりも長くなっている。ここにおいて、コア部１２ａは、上述のＳＯＩウェハの支持基板１０ａ、絶縁層１０ｂ、シリコン層１０ｃそれぞれを利用して形成し、各付随部１２ｂは、ＳＯＩウェハの支持基板１０ａを利用して形成してある。しかして、半導体素子１の上記一表面側において各付随部１２ｂの表面は、コア部１２ａの表面を含む平面から半導体素子１の上記他表面側（図２（ｂ）における下面側）へ離間して位置している。なお、半導体素子１の上述のフレーム部１１、重り部１２、各撓み部１３は、マイクロマシニング技術を利用して形成すればよい。   The weight portion 12 is continuously integrated with each of the rectangular parallelepiped core portion 12a supported by the frame portion 11 via the four flexure portions 13 and the four corners of the core portion 12a when viewed from the one surface side of the semiconductor element 1. And four accompanying portions 12b having a rectangular parallelepiped shape connected to each other. In other words, the weight portion 12 is formed integrally with the core portion 12a and the core portion 12a in which the other end portion of each bending portion 13 whose one end portion is connected to the inner side surface of the frame portion 11 is connected to the outer surface. It has four accompanying parts 12b arranged in the space between the part 12a and the frame part 11. In other words, each associated portion 12b is surrounded by the frame portion 11 and the core portion 12a and the two bent portions 13 and 13 extending in a direction orthogonal to each other in a plan view as viewed from the one surface side of the semiconductor element 1. The slits 14 are formed between each of the accompanying portions 12 b and the frame portion 11, and the interval between the adjacent accompanying portions 12 b across the bending portion 13 is larger than the width dimension of the bending portion 13. It is getting longer. Here, the core portion 12a is formed using the above-described SOI wafer support substrate 10a, the insulating layer 10b, and the silicon layer 10c, and each accompanying portion 12b is formed using the SOI wafer support substrate 10a. It is. Thus, on the one surface side of the semiconductor element 1, the surface of each associated portion 12b is separated from the plane including the surface of the core portion 12a to the other surface side of the semiconductor element 1 (the lower surface side in FIG. 2B). Is located. In addition, what is necessary is just to form the above-mentioned flame | frame part 11, the weight part 12, and each bending part 13 of the semiconductor element 1 using micromachining technology.

ところで、図２（ａ），（ｂ）それぞれの右下に示したように、半導体素子１の上記一表面に平行な面内でフレーム部１１の一辺に沿った一方向をｘ軸の正方向、この一辺に直交する辺に沿った一方向をｙ軸の正方向、半導体素子１の厚み方向の一方向をｚ軸の正方向と規定すれば、重り部１２は、ｘ軸方向に延長されてコア部１２ａを挟む２つ１組の撓み部１３，１３と、ｙ軸方向に延長されてコア部１２ａを挟む２つ１組の撓み部１３，１３とを介してフレーム部１１に支持されていることになる。なお、上述のｘ軸、ｙ軸、ｚ軸の３軸により規定した直交座標では、半導体素子１において上述のシリコン層１０ｃにより形成された部分の表面における重り部１２の中心位置を原点としている。   By the way, as shown in the lower right of each of FIGS. 2A and 2B, one direction along one side of the frame portion 11 in a plane parallel to the one surface of the semiconductor element 1 is defined as the positive direction of the x axis. If one direction along the side perpendicular to the one side is defined as the positive direction of the y-axis and one direction of the thickness direction of the semiconductor element 1 is defined as the positive direction of the z-axis, the weight portion 12 is extended in the x-axis direction. The pair of flexible portions 13 and 13 sandwiching the core portion 12a and the pair of flexible portions 13 and 13 extending in the y-axis direction and sandwiching the core portion 12a are supported by the frame portion 11. Will be. In the orthogonal coordinates defined by the three axes of the above-described x axis, y axis, and z axis, the center position of the weight portion 12 on the surface of the portion of the semiconductor element 1 formed by the above silicon layer 10c is the origin.

重り部１２のコア部１２ａからｘ軸の正方向に延長された撓み部１３（図２（ａ）の右側の撓み部１３）は、コア部１２ａ近傍に２つ１組のゲージ抵抗Ｒｘ２，Ｒｘ４が形成されるとともに、フレーム部１１近傍に１つのゲージ抵抗Ｒｚ２が形成されている。一方、重り部１２のコア部１２ａからｘ軸の負方向に延長された撓み部１３（図２（ａ）の左側の撓み部１３）は、コア部１２ａ近傍に２つ１組のゲージ抵抗Ｒｘ１，Ｒｘ３が形成されるとともに、フレーム部１１近傍に１つのゲージ抵抗Ｒｚ３が形成されている。ここに、コア部１２ａ近傍に形成された４つのゲージ抵抗Ｒｘ１，Ｒｘ２，Ｒｘ３，Ｒｘ４は、ｘ軸方向の加速度を検出するために形成されたもので、平面形状が細長の長方形状であって、長手方向が撓み部１３の長手方向に一致するように形成してあり、図３における左側のブリッジ回路Ｂｘを構成するように図示しない配線（半導体素子１に形成されている拡散層配線、金属配線など）によって接続されている。なお、ゲージ抵抗Ｒｘ１〜Ｒｘ４は、ｘ軸方向の加速度がかかったときに撓み部１３において応力が集中する応力集中領域に形成されている。   The bending portion 13 (the right-side bending portion 13 in FIG. 2A) extending from the core portion 12a of the weight portion 12 in the positive direction of the x-axis is a pair of gauge resistances Rx2 and Rx4 in the vicinity of the core portion 12a. And one gauge resistor Rz2 is formed in the vicinity of the frame portion 11. On the other hand, the bending portion 13 (the bending portion 13 on the left side of FIG. 2A) extended from the core portion 12a of the weight portion 12 in the negative direction of the x-axis is a pair of gauge resistances Rx1 in the vicinity of the core portion 12a. , Rx3, and one gauge resistor Rz3 is formed in the vicinity of the frame portion 11. Here, the four gauge resistors Rx1, Rx2, Rx3, Rx4 formed in the vicinity of the core portion 12a are formed to detect acceleration in the x-axis direction, and the planar shape is an elongated rectangular shape. 3 is formed so that the longitudinal direction thereof coincides with the longitudinal direction of the bent portion 13 and is not shown in the figure so as to constitute the left bridge circuit Bx in FIG. Connected by wiring). The gauge resistances Rx1 to Rx4 are formed in a stress concentration region where stress is concentrated in the bending portion 13 when acceleration in the x-axis direction is applied.

また、重り部１２のコア部１２ａからｙ軸の正方向に延長された撓み部１３（図２（ａ）の上側の撓み部１３）はコア部１２ａ近傍に２つ１組のゲージ抵抗Ｒｙ１，Ｒｙ３が形成されるとともに、フレーム部１１近傍に１つのゲージ抵抗Ｒｚ１が形成されている。一方、重り部１２のコア部１２ａからｙ軸の負方向に延長された撓み部１３（図２（ａ）の下側の撓み部１３）はコア部１２ａ近傍に２つ１組のゲージ抵抗Ｒｙ２，Ｒｙ４が形成されるとともに、フレーム部１１側の端部に１つのゲージ抵抗Ｒｚ４が形成されている。ここに、コア部１２ａ近傍に形成された４つのゲージ抵抗Ｒｙ１，Ｒｙ２，Ｒｙ３，Ｒｙ４は、ｙ軸方向の加速度を検出するために形成されたもので、平面形状が細長の長方形状であって、長手方向が撓み部１３の長手方向に一致するように形成してあり、図３における中央のブリッジ回路Ｂｙを構成するように図示しない配線（半導体素子１に形成されている拡散層配線、金属配線など）によって接続されている。なお、ゲージ抵抗Ｒｙ１〜Ｒｙ４は、ｙ軸方向の加速度がかかったときに撓み部１３において応力が集中する応力集中領域に形成されている。   Further, the bending portion 13 (the upper bending portion 13 in FIG. 2A) extending from the core portion 12a of the weight portion 12 in the positive direction of the y-axis is a pair of gauge resistances Ry1, in the vicinity of the core portion 12a. Ry3 is formed, and one gauge resistor Rz1 is formed in the vicinity of the frame portion 11. On the other hand, the bending portion 13 (the lower bending portion 13 in FIG. 2A) extended from the core portion 12a of the weight portion 12 in the negative direction of the y-axis is a pair of gauge resistances Ry2 in the vicinity of the core portion 12a. , Ry4 are formed, and one gauge resistor Rz4 is formed at the end on the frame part 11 side. Here, the four gauge resistors Ry1, Ry2, Ry3, Ry4 formed in the vicinity of the core portion 12a are formed to detect acceleration in the y-axis direction, and the planar shape is an elongated rectangular shape. The wiring is formed so that the longitudinal direction thereof coincides with the longitudinal direction of the bending portion 13 and is not shown so as to constitute the central bridge circuit By in FIG. 3 (diffuse layer wiring formed on the semiconductor element 1, metal Connected by wiring). Note that the gauge resistors Ry1 to Ry4 are formed in a stress concentration region where stress is concentrated in the flexure 13 when acceleration in the y-axis direction is applied.

また、フレーム部１１近傍に形成された４つのゲージ抵抗Ｒｚ１，Ｒｚ２，Ｒｚ３，Ｒｚ４は、ｚ軸方向の加速度を検出するために形成されたものであり、図３における右側のブリッジ回路Ｂｚを構成するように図示しない配線（半導体素子１に形成されている拡散層配線、金属配線など）によって接続されている。ただし、２つ１組となる撓み部１３，１３のうち一方の組の撓み部１３，１３に形成したゲージ抵抗Ｒｚ１，Ｒｚ４は長手方向が撓み部１３，１３の長手方向と一致するように形成されているのに対して、他方の組の撓み部１３，１３に形成したゲージ抵抗Ｒｚ２，Ｒｚ３は長手方向が撓み部１３，１３の幅方向（短手方向）と一致するように形成されている。   The four gauge resistors Rz1, Rz2, Rz3, and Rz4 formed in the vicinity of the frame portion 11 are formed to detect acceleration in the z-axis direction, and constitute the right bridge circuit Bz in FIG. Thus, they are connected by wiring (not shown) (diffusion layer wiring, metal wiring, etc. formed in the semiconductor element 1). However, the gauge resistances Rz1 and Rz4 formed in one set of the bending portions 13 and 13 of the pair of bending portions 13 and 13 are formed so that the longitudinal direction thereof coincides with the longitudinal direction of the bending portions 13 and 13. On the other hand, the gauge resistances Rz2 and Rz3 formed on the other set of flexures 13 and 13 are formed such that the longitudinal direction coincides with the width direction (short direction) of the flexures 13 and 13. Yes.

ここで、半導体素子１の基本的な動作の一例について説明する。   Here, an example of a basic operation of the semiconductor element 1 will be described.

いま、半導体素子１に加速度がかかっていない状態で、半導体素子１に対してｘ軸の正方向に加速度がかかったとすると、ｘ軸の負方向に作用する重り部１２の慣性力によってフレーム部１１に対して重り部１２が変位し、結果的にｘ軸方向を長手方向とする撓み部１３，１３が撓んで当該撓み部１３，１３に形成されているゲージ抵抗Ｒｘ１〜Ｒｘ４の抵抗値が変化することになる。この場合、ゲージ抵抗Ｒｘ１，Ｒｘ３は引張応力を受け、ゲージ抵抗Ｒｘ２，Ｒｘ４は圧縮応力を受ける。一般的にゲージ抵抗は引張応力を受けると抵抗値（抵抗率）が増大し、圧縮応力を受けると抵抗値（抵抗率）が減少する特性を有しているので、ゲージ抵抗Ｒｘ１，Ｒｘ３は抵抗値が増大し、ゲージ抵抗Ｒｘ２，Ｒｘ４は抵抗値が減少することになる。したがって、図３に示した一対の入力端子ＶＤＤ，ＧＮＤ間に外部電源から一定の直流電圧を印加しておけば、図３に示した左側のブリッジ回路Ｂｘの出力端子Ｘ１，Ｘ２間の電位差がｘ軸方向の加速度の大きさに応じて変化する。同様に、ｙ軸方向の加速度がかかった場合には図２に示した中央のブリッジ回路Ｂｙの出力端子Ｙ１，Ｙ２間の電位差がｙ軸方向の加速度の大きさに応じて変化し、ｚ軸方向の加速度がかかった場合には図３に示した右側のブリッジ回路Ｂｚの出力端子Ｚ１，Ｚ２間の電位差がｚ軸方向の加速度の大きさに応じて変化する。しかして、上述の半導体素子１は、各ブリッジ回路Ｂｘ〜Ｂｚそれぞれの出力電圧の変化を検出することにより、当該半導体素子１に作用したｘ軸方向、ｙ軸方向、ｚ軸方向それぞれの加速度を検出することができる。   Now, assuming that acceleration is applied to the semiconductor element 1 in the positive x-axis direction while no acceleration is applied to the semiconductor element 1, the frame portion 11 is caused by the inertial force of the weight 12 acting in the negative x-axis direction. Accordingly, the weight 12 is displaced, and as a result, the bending portions 13 and 13 whose longitudinal direction is the x-axis direction are bent, and the resistance values of the gauge resistors Rx1 to Rx4 formed in the bending portions 13 and 13 change. Will do. In this case, the gauge resistances Rx1 and Rx3 are subjected to tensile stress, and the gauge resistances Rx2 and Rx4 are subjected to compressive stress. In general, gauge resistance has a characteristic that resistance value (resistivity) increases when subjected to tensile stress, and resistance value (resistivity) decreases when subjected to compressive stress. As the value increases, the resistance values of the gauge resistors Rx2 and Rx4 decrease. Therefore, if a constant DC voltage is applied from the external power source between the pair of input terminals VDD and GND shown in FIG. 3, the potential difference between the output terminals X1 and X2 of the left bridge circuit Bx shown in FIG. It changes according to the magnitude of the acceleration in the x-axis direction. Similarly, when acceleration in the y-axis direction is applied, the potential difference between the output terminals Y1 and Y2 of the central bridge circuit By shown in FIG. 2 changes according to the magnitude of the acceleration in the y-axis direction, and the z-axis When acceleration in the direction is applied, the potential difference between the output terminals Z1 and Z2 of the right bridge circuit Bz shown in FIG. 3 changes according to the magnitude of acceleration in the z-axis direction. Therefore, the above-described semiconductor element 1 detects the change in the output voltage of each of the bridge circuits Bx to Bz, thereby accelerating each acceleration acting on the semiconductor element 1 in the x-axis direction, the y-axis direction, and the z-axis direction. Can be detected.

ここにおいて、半導体素子１は、上述の３つのブリッジ回路Ｂｘ，Ｂｙ，Ｂｚに共通の２つの入力端子ＶＤＤ，ＧＮＤと、ブリッジ回路Ｂｘの２つの出力端子Ｘ１，Ｘ２と、ブリッジ回路Ｂｙの２つの出力端子Ｙ１，Ｙ２と、ブリッジ回路Ｂｚの２つの出力端子Ｚ１，Ｚ２とを備えており、これらの各入力端子ＶＤＤ，ＧＮＤおよび各出力端子Ｘ１，Ｘ２，Ｙ１，Ｙ２，Ｚ１，Ｚ２が、上記一表面側にパッド（外部接続用電極）１９として設けられている。すなわち、半導体素子１は、回路を構成するうえで必要なパッド１９を備えているが、本実施形態では、８つのパッド１９以外に回路では必要ない１つのパッド１９をダミー（ダミーのパッド１９は、３つのブリッジ回路Ｂｘ，Ｂｚ，Ｂｙのいずれとも電気的に接続されていない）として備えている。なお、半導体素子１は、上記一表面側において上記シリコン層１０ｃ上にシリコン酸化膜とシリコン窒化膜との積層膜からなる絶縁膜１６が形成されており、パッド１９および上記金属配線は絶縁膜１６上に形成されている。   Here, the semiconductor element 1 includes two input terminals VDD and GND common to the above-described three bridge circuits Bx, By, and Bz, two output terminals X1 and X2 of the bridge circuit Bx, and two bridge circuits By. The output terminals Y1 and Y2 and the two output terminals Z1 and Z2 of the bridge circuit Bz are provided. These input terminals VDD and GND and the output terminals X1, X2, Y1, Y2, Z1 and Z2 A pad (external connection electrode) 19 is provided on one surface side. That is, the semiconductor element 1 includes the pads 19 necessary for configuring the circuit, but in the present embodiment, one pad 19 that is not necessary for the circuit other than the eight pads 19 is dummy (the dummy pad 19 is 3 is not electrically connected to any of the three bridge circuits Bx, Bz, By. In the semiconductor element 1, an insulating film 16 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the silicon layer 10 c on the one surface side, and the pad 19 and the metal wiring are the insulating film 16. Formed on top.

上述の各ゲージ抵抗（ピエゾ抵抗）Ｒｘ１〜Ｒｘ４，Ｒｙ１〜Ｒｙ４，Ｒｚ１〜Ｒｚ４および上記各拡散層配線は、上記シリコン層１０ｃにおけるそれぞれの形成部位に適宜濃度のｐ形不純物をドーピングすることにより形成され、上記金属配線は、絶縁膜１６上にスパッタ法や蒸着法などにより成膜した金属膜（例えば、Ａｌ膜、Ａｌ合金膜など）をリソグラフィ技術およびエッチング技術を利用してパターニングすることにより形成されている。なお、上記金属配線は絶縁膜１６に設けたコンタクトホールを通して拡散層配線と電気的に接続されている。   The gauge resistances (piezoresistors) Rx1 to Rx4, Ry1 to Ry4, Rz1 to Rz4 and the diffusion layer wirings described above are formed by doping p-type impurities with appropriate concentrations at respective formation sites in the silicon layer 10c. The metal wiring is formed by patterning a metal film (for example, an Al film, an Al alloy film, etc.) formed on the insulating film 16 by sputtering or vapor deposition using a lithography technique and an etching technique. Has been. The metal wiring is electrically connected to the diffusion layer wiring through a contact hole provided in the insulating film 16.

ところで、本実施形態の半導体素子１の実装構造では、半導体素子１の外周形状に基づいて規定した仮想三角形の３つの頂点に対応する３箇所で半導体素子１のパッド１９と基板３における半導体素子１の実装面３ａ側の接続用電極３９とが半田バンプからなるバンプ２を介して接合されている。より具体的には、本実施形態の半導体素子１の実装構造では、半導体素子１の外周形状が矩形状であって、上記仮想三角形の３つの頂点に対応する３箇所を半導体素子１の四隅のうちの３箇所に設定してあり、９つのパッド１９が、半導体素子１の四隅のうちの３箇所に分散して各箇所で３つずつ集中して配置されている。要するに、９つのパッド１９は、フレーム部１１の３箇所に３つずつ集中して配置されている。ここで、各パッド１９は、半導体素子１の外周部に位置しており、ＭＥＭＳデバイスの一種である半導体加速度センサチップよりなる半導体素子１の機能部であって各撓み部１３と重り部１２とで構成される可動部から離間して配置されている。しかして、各バンプ２は、半導体素子１の外周部に位置し、半導体素子１の上記可動部から離間して配置されることとなり、半導体素子の上記３箇所のうち複数のバンプ２が配置される箇所（ここでは、３箇所）では当該複数のバンプ２が密集して配置されることとなる。なお、９つのパッド１９は、半導体素子１の外周に沿って配置されている。   By the way, in the mounting structure of the semiconductor element 1 of the present embodiment, the pad 19 of the semiconductor element 1 and the semiconductor element 1 on the substrate 3 at three positions corresponding to the three vertices of the virtual triangle defined based on the outer peripheral shape of the semiconductor element 1. The connection electrode 39 on the mounting surface 3a side is joined via the bumps 2 made of solder bumps. More specifically, in the mounting structure of the semiconductor element 1 according to the present embodiment, the outer peripheral shape of the semiconductor element 1 is rectangular, and three locations corresponding to the three vertices of the virtual triangle are formed at the four corners of the semiconductor element 1. Of these, nine pads 19 are dispersed in three of the four corners of the semiconductor element 1 and three are arranged in a concentrated manner at each location. In short, nine pads 19 are arranged in a concentrated manner in three places on the frame portion 11. Here, each pad 19 is located on the outer periphery of the semiconductor element 1 and is a functional part of the semiconductor element 1 made of a semiconductor acceleration sensor chip, which is a kind of MEMS device. It is arrange | positioned away from the movable part comprised by these. Thus, each bump 2 is located on the outer peripheral portion of the semiconductor element 1 and is disposed away from the movable portion of the semiconductor element 1, and a plurality of bumps 2 are disposed among the three locations of the semiconductor element 1. The plurality of bumps 2 are densely arranged at three locations (here, three locations). The nine pads 19 are arranged along the outer periphery of the semiconductor element 1.

ここで、本実施形態では、基板３としてセラミック基板を用いており、接続用電極３９は、Ｎｉ膜とＡｕ膜との積層膜により構成されている。   Here, in the present embodiment, a ceramic substrate is used as the substrate 3, and the connection electrode 39 is configured by a laminated film of a Ni film and an Au film.

以下、半導体素子１を基板３に実装する際の半導体素子１および基板３の状態変化について図４に基づいて説明する。   Hereinafter, the state change of the semiconductor element 1 and the substrate 3 when the semiconductor element 1 is mounted on the substrate 3 will be described with reference to FIG.

半導体素子１を基板３に実装するにあたっては、図４（ａ）に示すように半導体素子１の各パッド１９（図１および図２参照）に半田バンプからなるバンプ２を形成した後、半導体素子１の各パッド１９に形成されたバンプ２と基板３における半導体素子１の実装面３ａ側の接続用電極３９（図１および図２参照）とを位置合わせして、所定温度に加熱すると図４（ｂ）に示すように基板３が熱変形し、その後、常温になると図４（ｃ）に示すように基板３が熱変形のない状態に戻ろうとする。ここで、半導体素子１は基板３が熱変形した状態で固定されていたが、基板３に対して上述の３箇所のみでしかバンプ２により固着されていないので、常温に戻ったときに温度変化による基板３側の変形が半導体素子１には当該半導体素子１の傾きとして伝わり、半導体素子１の表面を上述の３箇所で決定でき、半導体素子１が変形して応力が発生するのを防止することができる。基板３が常温に戻ったときに半導体素子１は図４（ｃ）に示すように若干傾くが、高低差がナノメータレベルの傾きであり、特に問題ない。なお、本実施形態では、半導体素子１のチップサイズが１．５ｍｍ□〜３．０ｍｍ□となっており、バンプ２の直径を０．１〜０．３ｍｍ程度に設定してあるが、これらの数値は特に限定するものではない。ただし、上述の３箇所それぞれで密集するバンプ２間の間隔は、半田ブリッジが形成されるのを防止するために、０．１ｍｍ以上であることが望ましい。   In mounting the semiconductor element 1 on the substrate 3, as shown in FIG. 4A, after forming bumps 2 made of solder bumps on the pads 19 of the semiconductor element 1 (see FIGS. 1 and 2), the semiconductor element 1 When the bump 2 formed on each pad 19 and the connection electrode 39 (see FIGS. 1 and 2) on the mounting surface 3a side of the semiconductor element 1 on the substrate 3 are aligned and heated to a predetermined temperature, FIG. As shown in FIG. 4B, the substrate 3 is thermally deformed, and thereafter, when the temperature reaches room temperature, the substrate 3 tries to return to a state without thermal deformation as shown in FIG. Here, the semiconductor element 1 is fixed in a state where the substrate 3 is thermally deformed. However, since the semiconductor element 1 is fixed to the substrate 3 by the bumps 2 only at the above-described three locations, the temperature change occurs when the temperature returns to room temperature. The deformation on the substrate 3 side due to the above is transmitted to the semiconductor element 1 as the inclination of the semiconductor element 1, and the surface of the semiconductor element 1 can be determined at the above-mentioned three locations, and the semiconductor element 1 is prevented from being deformed and generating stress. be able to. When the substrate 3 returns to room temperature, the semiconductor element 1 is slightly tilted as shown in FIG. 4C, but the height difference is a tilt at the nanometer level, which is not a problem. In this embodiment, the chip size of the semiconductor element 1 is 1.5 mm □ to 3.0 mm □, and the diameter of the bump 2 is set to about 0.1 to 0.3 mm. The numerical value is not particularly limited. However, it is desirable that the distance between the bumps 2 densely packed at each of the three locations described above is 0.1 mm or more in order to prevent the formation of a solder bridge.

以上説明した本実施形態の半導体素子１の実装構造では、半導体素子１の外周形状に基づいて規定した仮想三角形の３つの頂点に対応する３箇所で半導体素子１のパッド１９と基板３の接続用電極３９とがバンプ２を介して接合されているので、基板３への実装時などの温度変化に起因した基板３側の変形が半導体素子１に当該半導体素子１の傾きとして伝わるから、半導体素子１が変形するのを抑制することができ、半導体素子１に生じる応力を低減することが可能となる。ここで、半導体素子１が上述のような半導体加速度センサチップであれば、フレーム部１１の４つの角部それぞれに１ないし複数のバンプ２を形成して基板３に実装した場合やフレーム部１１の各辺それぞれに沿って複数のバンプ２を形成して基板３に実装した場合に比べて、基板３から半導体素子１への応力が、半導体素子１の機能部であって各撓み部１３と重り部１２とで構成される可動部に作用しにくく安定した精度の高い加速度測定が可能となる。要するに、本実施形態の半導体素子１の実装構造では、半導体素子１がＭＥＭＳデバイスの一種である半導体加速度センサチップであり、各パッド２が、当該ＭＥＭＳデバイスにおける可動部から離間して配置されているので、基板１への実装時などの温度変化に起因した可動部の変形を抑制することができ、特性変動（本実施形態では、センサ特性の変動）を抑制することができる。なお、本実施形態の半導体素子１の実装構造では、バンプ２の高さにより重り部１２の基板３側への許容変位量が決まることになるが、基板３における実装面３ａに、重り部１２の変位可能空間を拡張するための凹所を予め形成しておいてもよい。   In the mounting structure of the semiconductor element 1 of the present embodiment described above, the pads 19 of the semiconductor element 1 and the substrate 3 are connected at three positions corresponding to the three vertices of the virtual triangle defined based on the outer peripheral shape of the semiconductor element 1. Since the electrode 39 is joined via the bump 2, the deformation on the substrate 3 side caused by the temperature change during mounting on the substrate 3 is transmitted to the semiconductor element 1 as the inclination of the semiconductor element 1. 1 can be prevented from being deformed, and the stress generated in the semiconductor element 1 can be reduced. Here, when the semiconductor element 1 is a semiconductor acceleration sensor chip as described above, when one or a plurality of bumps 2 are formed on each of the four corners of the frame portion 11 and mounted on the substrate 3, Compared with the case where a plurality of bumps 2 are formed along each side and mounted on the substrate 3, the stress from the substrate 3 to the semiconductor element 1 is a functional part of the semiconductor element 1 and is weighted with each bending part 13. Therefore, it is possible to perform stable and highly accurate acceleration measurement that does not easily act on the movable part constituted by the part 12. In short, in the mounting structure of the semiconductor element 1 of the present embodiment, the semiconductor element 1 is a semiconductor acceleration sensor chip that is a kind of MEMS device, and each pad 2 is arranged apart from the movable part in the MEMS device. Therefore, it is possible to suppress deformation of the movable part due to temperature changes such as when mounted on the substrate 1, and to suppress characteristic fluctuations (sensor characteristic fluctuations in the present embodiment). In the mounting structure of the semiconductor element 1 of the present embodiment, the allowable displacement amount of the weight portion 12 toward the substrate 3 is determined by the height of the bump 2, but the weight portion 12 is disposed on the mounting surface 3 a of the substrate 3. A recess for expanding the displaceable space may be formed in advance.

また、本実施形態の半導体素子１の実装構造によれば、各バンプ２が半導体素子１の外周部に位置しているので、各バンプ２が半導体素子１の外周部よりも内側に位置している場合に比べて、半導体素子１を安定して固定することができる。   Further, according to the mounting structure of the semiconductor element 1 of the present embodiment, each bump 2 is located on the outer peripheral portion of the semiconductor element 1, so that each bump 2 is located on the inner side of the outer peripheral portion of the semiconductor element 1. The semiconductor element 1 can be stably fixed as compared with the case where it is present.

また、本実施形態の半導体素子１の実装構造では、各バンプ２が半田バンプにより構成されているので、各バンプ２をＡｕバンプにより構成する場合に比べて、各バンプ２が柔らかくて応力緩和性が大きく、基板３への実装時などの温度変化に起因して半導体素子１に生じる応力をより低減することができるとともに、接合信頼性を向上させることができる。   Further, in the mounting structure of the semiconductor element 1 according to the present embodiment, each bump 2 is constituted by a solder bump, so that each bump 2 is softer and less stress-releasing than when each bump 2 is constituted by an Au bump. Therefore, the stress generated in the semiconductor element 1 due to a temperature change at the time of mounting on the substrate 3 can be further reduced, and the bonding reliability can be improved.

また、本実施形態の半導体素子１の実装構造によれば、上述の３箇所のうち複数のバンプ２が配置される箇所（ここでは、３箇所）では当該複数のバンプ２が密集して配置されているので、半導体素子１の局所的な変形を抑制することができる。   Further, according to the mounting structure of the semiconductor element 1 of the present embodiment, the plurality of bumps 2 are densely arranged at the locations (here, three locations) where the plurality of bumps 2 are arranged among the three locations described above. Therefore, local deformation of the semiconductor element 1 can be suppressed.

（実施形態２）
本実施形態の半導体素子１の実装構造は実施形態１と略同じであって、図５に示すように、半導体素子１と基板３との間で各バンプ２を封止する樹脂（例えば、エポキシ樹脂など）からなる封止部（アンダーフィル部）４が設けられている点が相違する。ここにおいて、本実施形態では、各バンプ２を大径部の直径が０．０５ｍｍ〜０．１５ｍｍのＡｕスタッドバンプからなるＡｕバンプにより構成してあり、密集して配置された３つのバンプ２を封止部４により封止してある。なお、実施形態１と同様の構成要素には同一の符号を付して説明を省略する。 (Embodiment 2)
The mounting structure of the semiconductor element 1 of the present embodiment is substantially the same as that of the first embodiment, and as shown in FIG. The difference is that a sealing portion (underfill portion) 4 made of a resin or the like is provided. Here, in this embodiment, each bump 2 is constituted by an Au bump made of an Au stud bump having a large diameter portion of 0.05 mm to 0.15 mm, and three bumps 2 arranged in a dense manner are provided. Sealed by the sealing part 4. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

ところで、Ａｕバンプは半田バンプに比べて硬いので、バンプ２を形成した後の工程の熱履歴での基板３の熱収縮によりバンプ２と接続用電極２９との接合部位において接合不良が発生する恐れがある。   By the way, since the Au bump is harder than the solder bump, a bonding failure may occur at the bonding portion between the bump 2 and the connection electrode 29 due to the thermal contraction of the substrate 3 in the thermal history of the process after the bump 2 is formed. There is.

しかしながら、本実施形態の半導体素子１の実装構造では、各バンプ２が樹脂からなる封止部４により封止されているので、半導体素子１と基板３とのバンプ２による接合信頼性を向上させることができる。また、本実施形態では、封止部４が、バンプ２と同様、半導体素子１の外周形状に基づいて規定した仮想三角形の３つの頂点に対応する３箇所で半導体素子１と基板３とを接合しているので、基板３への実装時などの温度変化に起因した基板３側の変形が半導体素子１に当該半導体素子１の傾きとして伝わるから、半導体素子１が変形するのを抑制することができ、半導体素子１に生じる応力を低減することが可能となる。なお、本実施形態では、各バンプ２をＡｕバンプにより構成してあるが、Ａｕバンプに限らず、半田バンプにより構成してもよい。また、Ａｕバンプはスタッドバンプに限らず、めっきバンプでもよい。   However, in the mounting structure of the semiconductor element 1 of the present embodiment, since each bump 2 is sealed by the sealing portion 4 made of resin, the bonding reliability of the semiconductor element 1 and the substrate 3 by the bump 2 is improved. be able to. Further, in the present embodiment, the sealing portion 4 joins the semiconductor element 1 and the substrate 3 at three locations corresponding to the three vertices of the virtual triangle defined based on the outer peripheral shape of the semiconductor element 1, as with the bump 2. Therefore, the deformation on the substrate 3 side caused by the temperature change at the time of mounting on the substrate 3 is transmitted to the semiconductor element 1 as the inclination of the semiconductor element 1, so that the deformation of the semiconductor element 1 can be suppressed. It is possible to reduce the stress generated in the semiconductor element 1. In the present embodiment, each bump 2 is composed of an Au bump, but is not limited to an Au bump, and may be composed of a solder bump. The Au bump is not limited to a stud bump, and may be a plating bump.

ところで、上述の各実施形態では、平面視における外周形状が正方形状の半導体素子１を３箇所でバンプ２により基板３に固着しているが、バンプ２の位置は各実施形態の位置に限定するものではなく、半導体素子１をバランス良く支持できる位置であればよく、図６の（ａ）〜（ｌ）の位置でもよい。ここで、図６（ａ）は実施形態１，２における各バンプ２の配置と同じであり、半導体素子１の四隅のうちの３箇所それぞれにバンプ２が位置する例、同図（ｂ）は半導体素子１の四隅のうちの隣り合う２箇所と当該２箇所近傍の角を結ぶ辺に平行な辺の中央近傍とにバンプ２が位置する例、同図（ｃ），（ｄ）は半導体素子１の四隅のうちの隣り合う２箇所と当該２箇所近傍の角を結ぶ辺に隣り合う１辺の中間近傍とにバンプ２が位置する例、同図（ｅ）〜（ｊ）は半導体素子１の四隅のうちの１箇所と４辺のうちの２辺の中間近傍とにバンプ２が位置する例、同図（ｋ），（ｌ）は半導体素子１の４辺のうちの３辺の中間近傍にバンプ２が位置する例を示している。ここにおいて、３箇所のバンプ２は、仮想三角形の頂点に対応するように位置しているが、当該仮想三角形の面積が大きく、且つ、当該仮想三角形内に半導体素子１の中心が内包されることが望ましく、３箇所のバンプ２の配置は、同図（ａ），（ｂ）の配置が最良の配置となる。   By the way, in each of the above-described embodiments, the semiconductor element 1 having a square outer peripheral shape in plan view is fixed to the substrate 3 by the bumps 2 at three positions. However, the positions of the bumps 2 are limited to the positions of the respective embodiments. It may be a position that can support the semiconductor element 1 in a balanced manner, and may be the positions (a) to (l) in FIG. Here, FIG. 6A is the same as the arrangement of the bumps 2 in the first and second embodiments, and an example in which the bumps 2 are located at three of the four corners of the semiconductor element 1, FIG. An example in which the bumps 2 are located in two adjacent corners of the semiconductor element 1 and in the vicinity of the center of the side parallel to the side connecting the corners in the vicinity of the two parts, FIGS. FIG. 4E to FIG. 6J show an example in which the bumps 2 are located in the vicinity of two of the four corners of one and the middle of one side adjacent to the side connecting the corners in the vicinity of the two. The bumps 2 are located in one of the four corners and in the vicinity of the middle of two of the four sides. FIGS. 4 (k) and 1 (l) show the middle of three of the four sides of the semiconductor element 1. An example in which the bump 2 is located in the vicinity is shown. Here, the three bumps 2 are positioned so as to correspond to the vertices of the virtual triangle, but the area of the virtual triangle is large, and the center of the semiconductor element 1 is included in the virtual triangle. Desirably, the arrangement of the bumps 2 at the three locations is the best arrangement shown in FIGS.

また、上述の各実施形態では、バンプ２として、半田バンプやＡｕバンプなどを採用しているが、バンプ２は、半田やＡｕなどの金属に限らず、シリコーン系樹脂（例えば、弾性率が１０ＭＰａ以下のシリコーン樹脂などのシリコーン系樹脂）の導電性ペーストにより形成してもよく、この場合には、各バンプ２を金属やエポキシ樹脂系の導電性ペーストなどにより構成する場合に比べて、各バンプ２の弾性率が小さくて応力緩和性が大きいので、基板３への実装時などの温度変化に起因して半導体素子１に生じる応力をより低減することができるとともに、接合信頼性を向上させることができる。   In each of the above-described embodiments, solder bumps or Au bumps are used as the bumps 2. However, the bumps 2 are not limited to metals such as solder and Au, but may be silicone resins (for example, elastic modulus is 10 MPa). It may be formed by a conductive paste of a silicone resin such as the following silicone resin. In this case, each bump 2 is compared with a case where each bump 2 is made of a conductive paste of metal or epoxy resin. 2 has a small elastic modulus and a large stress relaxation property, so that the stress generated in the semiconductor element 1 due to a temperature change during mounting on the substrate 3 can be further reduced and the bonding reliability can be improved. Can do.

また、上述の各実施形態では、９つのパッド１９を設けた半導体素子１について例示したが、パッド１９の数は特に限定するものではなく３つ以上であればよく、４つ以上の場合には、上述の３箇所のうち少なくとも１箇所で複数のバンプ２を密集して配置することで、複数のバンプ２が配置される箇所での半導体素子１の局所的な変形を抑制することができる。   Further, in each of the above-described embodiments, the semiconductor element 1 provided with the nine pads 19 is illustrated, but the number of the pads 19 is not particularly limited and may be three or more, and in the case of four or more. By arranging the plurality of bumps 2 densely in at least one of the three locations described above, local deformation of the semiconductor element 1 at the location where the plurality of bumps 2 are disposed can be suppressed.

また、上述の各実施形態では、半導体素子１として、ＭＥＭＳデバイスの一例としてピエゾ抵抗形の半導体加速度センサチップを例示したが、半導体素子１は、半導体加速度センサチップに限らず、例えば、容量形の加速度センサチップやジャイロセンサ、圧力センサ、マイクロアクチュエータ、マイクロリレー、マイクロバルブ、赤外線センサなどのＭＥＭＳデバイスや、ＩＣチップ、半導体スイッチ（例えば、ＭＯＳＦＥＴなど）などにも適用できる。また、半導体素子１の外周形状は正方形状に限らず、矩形状であればよい。   In each of the above-described embodiments, a piezoresistive semiconductor acceleration sensor chip is illustrated as an example of the MEMS device as the semiconductor element 1. However, the semiconductor element 1 is not limited to the semiconductor acceleration sensor chip, and may be, for example, a capacitive type. It can also be applied to MEMS devices such as acceleration sensor chips, gyro sensors, pressure sensors, microactuators, microrelays, microvalves, infrared sensors, IC chips, semiconductor switches (eg, MOSFETs), and the like. Further, the outer peripheral shape of the semiconductor element 1 is not limited to a square shape, but may be a rectangular shape.

実施形態１の半導体素子の実装構造を示し、（ａ）は要部概略平面図、（ｂ）は要部概略断面図である。1A and 1B show a mounting structure of a semiconductor element according to Embodiment 1, wherein FIG. 3A is a schematic plan view of a main part, and FIG. 同上における半導体素子の概略平面図、（ｂ）は概略断面図である。The schematic plan view of the semiconductor element in the same as the above, (b) is a schematic sectional view. 同上の半導体素子である半導体加速度センサチップの回路図である。It is a circuit diagram of the semiconductor acceleration sensor chip which is a semiconductor element same as the above. 同上における基板への半導体素子の実装工程の説明図である。It is explanatory drawing of the mounting process of the semiconductor element to the board | substrate in the same as the above. 実施形態２の半導体素子の実装構造を示し、（ａ）は要部概略平面図、（ｂ）は要部概略断面図である。The mounting structure of the semiconductor element of Embodiment 2 is shown, (a) is a principal part schematic plan view, (b) is a principal part schematic sectional drawing. 同上における各バンプの配置例の説明図である。It is explanatory drawing of the example of arrangement | positioning of each bump in the same as the above. 従来例における半導体素子の実装構造を示し、（ａ）は要部概略平面図、（ｂ）は（ａ）のＡ−Ａ’概略断面図である。The mounting structure of the semiconductor element in a prior art example is shown, (a) is a principal part schematic plan view, (b) is A-A 'schematic sectional drawing of (a). 他の従来例における半導体素子の実装構造を示す概略平面図である。It is a schematic plan view which shows the mounting structure of the semiconductor element in another prior art example. 同上における基板への半導体素子の実装工程の説明図である。It is explanatory drawing of the mounting process of the semiconductor element to the board | substrate in the same as the above.

符号の説明Explanation of symbols

１ 半導体素子
２ バンプ
３ 基板
４ 封止部
１１ フレーム部
１２ 重り部
１３ 撓み部
１９ パッド
３９ 接続用電極 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Bump 3 Substrate 4 Sealing part 11 Frame part 12 Weight part 13 Deflection part 19 Pad 39 Connection electrode

Claims (7)

半導体素子を基板に実装した半導体素子の実装構造であって、半導体素子の外周形状に基づいて規定した仮想三角形の３つの頂点に対応する３箇所で半導体素子のパッドと基板の接続用電極とがバンプを介して接合されてなることを特徴とする半導体素子の実装構造。   A semiconductor element mounting structure in which a semiconductor element is mounted on a substrate, wherein pads of the semiconductor element and connection electrodes on the substrate are provided at three locations corresponding to the three vertices of a virtual triangle defined based on the outer peripheral shape of the semiconductor element. A semiconductor device mounting structure characterized by being bonded via a bump. 前記３箇所のうち少なくとも１箇所では複数のバンプが密集して配置されてなることを特徴とする請求項１記載の半導体素子の実装構造。   2. The semiconductor element mounting structure according to claim 1, wherein a plurality of bumps are densely arranged in at least one of the three locations. 各バンプは、半導体素子の外周部に位置していることを特徴とする請求項１または請求項２記載の半導体素子の実装構造。   3. The semiconductor element mounting structure according to claim 1, wherein each bump is located on an outer peripheral portion of the semiconductor element. 半導体素子がＭＥＭＳデバイスであり、各パッドは、当該ＭＥＭＳデバイスにおける可動部から離間して配置されてなることを特徴とする請求項１ないし請求項３のいずれか１項に記載の半導体素子の実装構造。   4. The semiconductor element mounting according to claim 1, wherein the semiconductor element is a MEMS device, and each pad is disposed apart from a movable portion in the MEMS device. 5. Construction. 各バンプは、半田バンプからなることを特徴とする請求項１ないし請求項４のいずれか１項に記載の半導体素子の実装構造。   5. The semiconductor element mounting structure according to claim 1, wherein each bump is made of a solder bump. 各バンプは、シリコーン系樹脂の導電性ペーストにより形成されてなることを特徴とする請求項１ないし請求項４のいずれか１項に記載の半導体素子の実装構造。   5. The semiconductor element mounting structure according to claim 1, wherein each bump is formed of a conductive paste of a silicone-based resin. 半導体素子と基板との間で各バンプを封止する樹脂からなる封止部が設けられてなることを特徴とする請求項１ないし請求項６のいずれか１項に記載の半導体素子の実装構造。   The semiconductor element mounting structure according to claim 1, wherein a sealing portion made of a resin for sealing each bump is provided between the semiconductor element and the substrate. .
JP2008111701A 2008-04-22 2008-04-22 Semiconductor element mounting structure Expired - Fee Related JP5033045B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008111701A JP5033045B2 (en) 2008-04-22 2008-04-22 Semiconductor element mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008111701A JP5033045B2 (en) 2008-04-22 2008-04-22 Semiconductor element mounting structure

Publications (2)

Publication Number Publication Date
JP2009266898A true JP2009266898A (en) 2009-11-12
JP5033045B2 JP5033045B2 (en) 2012-09-26

Family

ID=41392404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008111701A Expired - Fee Related JP5033045B2 (en) 2008-04-22 2008-04-22 Semiconductor element mounting structure

Country Status (1)

Country Link
JP (1) JP5033045B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832179A (en) * 2012-08-31 2012-12-19 江苏宏微科技股份有限公司 Metal base plate used for welding power module
WO2022163195A1 (en) * 2021-01-27 2022-08-04 ソニーグループ株式会社 Force sensor module

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745620A (en) * 1993-07-26 1995-02-14 Hitachi Ltd Semiconductor device, its manufacture, and its mounting structure
JPH10189653A (en) * 1996-12-26 1998-07-21 Toshiba Corp Semiconductor element and circuit module having this semiconductor element
JP2001250840A (en) * 2000-03-08 2001-09-14 Seiko Instruments Inc Semiconductor device
JP2004349390A (en) * 2003-05-21 2004-12-09 Olympus Corp Semiconductor device and its manufacturing method
JP2005203465A (en) * 2004-01-14 2005-07-28 Seiko Epson Corp Bump arrangement method in flip chip connection, semiconductor chip and optical module
JP2007266555A (en) * 2006-03-30 2007-10-11 Denso Corp Manufacturing method for bump bonding laminate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745620A (en) * 1993-07-26 1995-02-14 Hitachi Ltd Semiconductor device, its manufacture, and its mounting structure
JPH10189653A (en) * 1996-12-26 1998-07-21 Toshiba Corp Semiconductor element and circuit module having this semiconductor element
JP2001250840A (en) * 2000-03-08 2001-09-14 Seiko Instruments Inc Semiconductor device
JP2004349390A (en) * 2003-05-21 2004-12-09 Olympus Corp Semiconductor device and its manufacturing method
JP2005203465A (en) * 2004-01-14 2005-07-28 Seiko Epson Corp Bump arrangement method in flip chip connection, semiconductor chip and optical module
JP2007266555A (en) * 2006-03-30 2007-10-11 Denso Corp Manufacturing method for bump bonding laminate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832179A (en) * 2012-08-31 2012-12-19 江苏宏微科技股份有限公司 Metal base plate used for welding power module
WO2022163195A1 (en) * 2021-01-27 2022-08-04 ソニーグループ株式会社 Force sensor module

Also Published As

Publication number Publication date
JP5033045B2 (en) 2012-09-26

Similar Documents

Publication Publication Date Title
JP4925275B2 (en) Semiconductor device
JP4925272B2 (en) Semiconductor device
JP4839826B2 (en) Sensor module
JP3938198B1 (en) Wafer level package structure and sensor element
JP2008008672A (en) Acceleration sensor
JP5033045B2 (en) Semiconductor element mounting structure
JP4715503B2 (en) Manufacturing method of sensor module
JP3938204B1 (en) Wafer level package structure and sensor element
JP3938199B1 (en) Wafer level package structure and sensor device
JP5475946B2 (en) Sensor module
JP5221940B2 (en) Semiconductor element mounting structure
JP5395412B2 (en) Interposer
JP2008241482A (en) Sensor device
JP2010008172A (en) Semiconductor device
JP2007173757A (en) Sensor element
JP2010008123A (en) Sensor module
JP4665733B2 (en) Sensor element
JP5069410B2 (en) Sensor element
JP4925274B2 (en) Semiconductor device
JP4816065B2 (en) Manufacturing method of sensor module
JP4925273B2 (en) Semiconductor device
JP2006300904A (en) Physical quantity sensor
JP3938203B1 (en) Sensor element and wafer level package structure
JP2008157825A (en) Sensor device
JP2007171153A (en) Sensor element

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20100811

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101222

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20120112

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120313

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120321

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120521

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120605

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120629

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150706

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees