JP2009238957A - Via forming method on board - Google Patents

Via forming method on board Download PDF

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JP2009238957A
JP2009238957A JP2008082102A JP2008082102A JP2009238957A JP 2009238957 A JP2009238957 A JP 2009238957A JP 2008082102 A JP2008082102 A JP 2008082102A JP 2008082102 A JP2008082102 A JP 2008082102A JP 2009238957 A JP2009238957 A JP 2009238957A
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substrate
surface side
forming
hole
thin film
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Kaoru Tone
薫 戸根
Takumi Taura
巧 田浦
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Panasonic Electric Works Co Ltd
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Panasonic Electric Works Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

<P>PROBLEM TO BE SOLVED: To provide a via forming method of a board can reduce warpage of the board. <P>SOLUTION: After forming a metal thin film 26 on one surface side of a board 20a after a through-hole formation process to prevent the respective through-holes 22 from being closed, a resist layer 61 having a plurality of openings 61a exposing the respective through-holes 22 and the metal thin film 26 in circumferential parts of the respective through-holes 22 are formed on the one surface side of the board 20a; thereafter a plurality of island-like conductor parts 27 closing the respective through-holes 22 are formed on the one surface side of the board 20a by electric plating; thereafter a current is carried between positive electrodes oppositely arranged on the other surface side of the board 20a and negative electrodes composed of the conductor parts 27 closing the respective through-holes 22 on the one surface side of the board 20a to deposit a plurality of metal parts respectively used as vias 24 along the thickness direction of the board 20a from exposed surfaces of the through-hole 22 sides in the respective conductor parts 27; and thereafter the resist layer 61 and the metal thin film 26 under the resist layer 61 are removed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、基板へのビアの形成方法に関するものである。   The present invention relates to a method for forming a via in a substrate.

従来から、ビアを有するデバイスやパッケージの応用分野として、例えば、ＬＥＤチップを用いた発光装置、物理量センサ（加速度センサ、圧力センサ、ジャイロセンサなど）、赤外線センサ、高周波デバイス（ＲＦ−ＭＥＭＳ、マイクロリレーなど）、マイクロバルブ、音響センサ、化学センサ、半導体装置（例えば、集積回路装置など）などが知られており、半導体基板や絶縁性基板（例えば、ガラス基板）などの基板へのビアの形成方法が各所で研究開発されている（例えば、特許文献１〜３照）。   Conventionally, as application fields of devices and packages having vias, for example, light emitting devices using LED chips, physical quantity sensors (acceleration sensors, pressure sensors, gyro sensors, etc.), infrared sensors, high frequency devices (RF-MEMS, micro relays) Etc.), microvalves, acoustic sensors, chemical sensors, semiconductor devices (eg, integrated circuit devices), etc., and methods for forming vias on substrates such as semiconductor substrates and insulating substrates (eg, glass substrates) Are being researched and developed in various places (for example, see Patent Documents 1 to 3).

ここにおいて、上記特許文献１には、基板に形成した複数の貫通孔内へビア（貫通孔配線）となる導電性材料を充填する方法として、溶融金属埋め戻し法を採用することが記載され、上記特許文献３，４には、電気めっき法が記載されている。   Here, Patent Document 1 describes that a molten metal backfill method is employed as a method of filling a conductive material to be a via (through hole wiring) into a plurality of through holes formed in a substrate. Patent Documents 3 and 4 describe an electroplating method.

ここで、上記特許文献２に記載された基板へのビア（貫通孔配線）の形成方法の一例について図１１に基づいて説明する。   Here, an example of a method of forming a via (through-hole wiring) in the substrate described in Patent Document 2 will be described with reference to FIG.

まず、半導体基板からなる基板２４０の一表面（図１１（ａ）の上面）における貫通孔形成予定部位にエッチング加工などによって貫通孔用の凹部２４０ａを形成することにより、図１１（ａ）に示す構造を得る。   First, a through-hole recess 240a is formed by etching or the like at a through-hole formation scheduled portion on one surface of the substrate 240 made of a semiconductor substrate (the upper surface of FIG. 11 (a)). Get the structure.

その後、ＣＶＤ法や熱酸化法などによって基板２４０の上記一表面および凹部２４０ａの内面に絶縁層２４３ａを形成するとともに基板２４０の他表面（図１１（ａ）の下面）に絶縁層２４３ｂを形成し、続いて、基板２４０の上記一表面および凹部２４０ａの内面に形成されている絶縁層２４３ａに金属材料（例えば、銅、ニッケルなど）からなる金属薄膜２４４をＣＶＤ法やスパッタ法などによって積層することによって、図１１（ｂ）に示す構造を得る。   Thereafter, an insulating layer 243a is formed on the one surface of the substrate 240 and the inner surface of the recess 240a by CVD or thermal oxidation, and an insulating layer 243b is formed on the other surface of the substrate 240 (the lower surface in FIG. 11A). Subsequently, a metal thin film 244 made of a metal material (for example, copper, nickel, etc.) is laminated on the insulating layer 243a formed on the one surface of the substrate 240 and the inner surface of the recess 240a by a CVD method, a sputtering method, or the like. Thus, the structure shown in FIG.

その後、金属薄膜２４４をシード層として電気めっき法などによって金属材料（例えば、銅、ニッケルなど）からなる金属部２４５を析出（堆積）させることにより、図１１（ｃ）に示す構造を得る。   Thereafter, a metal portion 245 made of a metal material (for example, copper, nickel, etc.) is deposited (deposited) by electroplating using the metal thin film 244 as a seed layer, thereby obtaining the structure shown in FIG.

その後、基板２４０の上記他表面側をＣＭＰ技術などによって研磨して貫通孔２４２を完成させ、続いて、金属部２４５のうち基板２４０の上記一表面側における不要部分を除去することによって、図１１（ｄ）に示す構造を得る。ここに、図１１（ｄ）では、金属部２４５のうち貫通孔２４２に埋め込まれている部分が貫通配線２４６を構成している。   Thereafter, the other surface side of the substrate 240 is polished by a CMP technique or the like to complete the through hole 242, and then unnecessary portions on the one surface side of the substrate 240 of the metal portion 245 are removed, whereby FIG. The structure shown in (d) is obtained. Here, in FIG. 11D, the portion embedded in the through hole 242 in the metal portion 245 constitutes the through wiring 246.

次に、上記特許文献３に記載された基板へのビア（貫通孔配線）の形成方法の一例について図１２に基づいて説明する。   Next, an example of a method for forming a via (through-hole wiring) in the substrate described in Patent Document 3 will be described with reference to FIG.

まず、絶縁性基板からなる基板３４０にエッチング加工などによって厚み方向に貫通する複数の貫通孔３４２を形成することにより、図１２（ａ）に示す構造を得る。   First, the structure shown in FIG. 12A is obtained by forming a plurality of through holes 342 penetrating in the thickness direction by etching or the like on a substrate 340 made of an insulating substrate.

その後、基板３４０の一表面側に金属薄膜３４４をスパッタ法などによって形成することにより、図１２（ｂ）に示す構造を得る。続いて、金属薄膜３４４をシード層として電気めっき法によって金属を析出させることで基板３４０の上記一表面側において各貫通孔３４２を閉塞する導体部３４５を形成することにより、図１２（ｃ）に示す構造を得る。   Thereafter, a metal thin film 344 is formed on one surface side of the substrate 340 by a sputtering method or the like, thereby obtaining the structure shown in FIG. Subsequently, a metal portion is deposited by electroplating using the metal thin film 344 as a seed layer to form a conductor portion 345 that closes each through-hole 342 on the one surface side of the substrate 340, whereby FIG. Get the structure shown.

その後、基板３４０の他表面側に対向配置した陽極（図示せず）と基板３４０の上記一表面側において各貫通孔３４２を閉塞している導体部３４５からなる陰極との間に通電して金属部３４６を各導体部３４５における貫通孔３４２側の露出表面から基板３４０の厚み方向に沿って析出させ、続いて、各金属部３４６のうち基板３４０の上記他表面側に突出した不要部分を除去するＣＭＰを行うことによって、図１２（ｄ）に示す構造を得る。   Thereafter, a current is applied between an anode (not shown) disposed opposite to the other surface side of the substrate 340 and a cathode formed of a conductor portion 345 blocking each through-hole 342 on the one surface side of the substrate 340. The portion 346 is deposited along the thickness direction of the substrate 340 from the exposed surface of each conductor portion 345 on the through hole 342 side, and then, unnecessary portions protruding from the other surface side of the substrate 340 are removed from each metal portion 346. By performing CMP, the structure shown in FIG. 12D is obtained.

その後、基板３４０の上記一表面側の導体部３４５を除去するＣＭＰを行うことによって、金属部３４６からなるビアが完成した図１２（ｅ）に示す構造を得る。
特開２００２−２３７４６８号公報 特開２００３−３２８１８０号公報 特開２００６−１１１８９６号公報 Thereafter, CMP is performed to remove the conductor portion 345 on the one surface side of the substrate 340, thereby obtaining a structure shown in FIG. 12E in which a via made of the metal portion 346 is completed.
JP 2002-237468 A JP 2003-328180 A JP 2006-111896 A

しかしながら、上記特許文献１に記載された溶融金属埋め戻し法を利用してビアを形成する基板へのビアの形成方法では、減圧雰囲気中で例えば３００℃の溶融金属（溶融すず）に基板を浸漬し、その後、雰囲気を大気圧に戻すようにしているが、溶融金属の硬化時の収縮により応力が生じて基板が反ってしまう。   However, in the method of forming a via on a substrate that forms a via using the molten metal backfill method described in Patent Document 1, the substrate is immersed in a molten metal (molten tin) at 300 ° C. in a reduced pressure atmosphere. After that, the atmosphere is returned to atmospheric pressure, but stress is generated due to shrinkage when the molten metal is cured, and the substrate is warped.

また、上記特許文献２に記載された基板へのビアの形成方法では、金属部２４５を形成する電気めっきを行うことにより、図１１（ｃ）に示すように金属部２４５が基板２４０の上記一表面側の全体に形成されるので、めっき応力により基板２４０が反ってしまい、その後、金属部２４５のうち基板２４０の上記一表面側における不要部分を除去しても、基板２４０の反りが残ってしまう。   Further, in the method for forming a via on the substrate described in Patent Document 2, the metal portion 245 is formed on the substrate 240 as shown in FIG. 11C by performing electroplating to form the metal portion 245. Since it is formed on the entire surface side, the substrate 240 warps due to the plating stress, and the warp of the substrate 240 remains even after the unnecessary portion of the metal portion 245 on the one surface side of the substrate 240 is removed. End up.

また、上記特許文献３に記載された基板へのビアの形成方法では、基板３４０の上記一表面側において各貫通孔３４２を閉塞する導体部３４５を形成することにより、図１２（ｃ）に示すように導体部３４５が基板３４０の上記一表面側の全体に形成されるので、めっき応力によって基板３４０が反ってしまい、その後、導体部３４５の不要部分を除去しても、基板３４０の反りが残ってしまう。   Further, in the method for forming a via in the substrate described in Patent Document 3, a conductor portion 345 that closes each through-hole 342 is formed on the one surface side of the substrate 340, as shown in FIG. Thus, since the conductor portion 345 is formed on the entire surface of the one surface of the substrate 340, the substrate 340 is warped by the plating stress, and after that, even if unnecessary portions of the conductor portion 345 are removed, the warpage of the substrate 340 is caused. It will remain.

ところで、ビアを有する基板を備えたデバイスの製造時に、基板が反ってしまうと、その後の工程において、ロボットアームによる基板の搬送ができなくなったり、加工精度の低下（特に、フォトリソグラフィ技術とエッチング技術を利用したパターニングや、研磨技術を利用した平坦化などの加工精度の低下）や、歩留まりの低下の原因となったり、デバイスの特性低下（例えば、物理量センサのセンサ特性など）の原因となることが考えられる。   By the way, if a substrate is warped during the manufacture of a device having a substrate having vias, the substrate cannot be transported by a robot arm in the subsequent process, or the processing accuracy is lowered (especially photolithography technology and etching technology). Patterning using a metal or reduction in processing accuracy such as flattening using a polishing technique), a decrease in yield, or a decrease in device characteristics (for example, sensor characteristics of a physical quantity sensor). Can be considered.

本発明は上記事由に鑑みて為されたものであり、その目的は、基板の反りを低減できる基板へのビアの形成方法を提供することにある。   The present invention has been made in view of the above-described reasons, and an object thereof is to provide a method for forming a via in a substrate that can reduce the warpage of the substrate.

請求項１の発明は、基板へのビアの形成方法であって、基板に厚み方向に貫通する複数の貫通孔を形成する貫通孔形成工程と、貫通孔形成工程の後で基板の一表面側に各貫通孔が閉塞されないように金属薄膜を形成する金属薄膜形成工程と、金属薄膜形成工程の後で基板の前記一表面側に各貫通孔および各貫通孔の周部の金属薄膜を露出させる複数の開口部を有するレジスト層を形成するレジスト層形成工程と、レジスト層形成工程の後で基板の前記一表面側に各貫通孔を閉塞する複数の島状の導体部を電気めっきにより形成する第１の電気めっき工程と、第１の電気めっき工程の後で基板の他表面側に対向配置した陽極と基板の前記一表面側において各貫通孔を閉塞している導体部からなる陰極との間に通電してそれぞれビアとなる複数の金属部を各導体部における貫通孔側の露出表面から基板の厚み方向に沿って析出させる第２の電気めっき工程と、第２の電気めっき工程の後でレジスト層を除去する不要部除去工程とを備えることを特徴とする。   The invention according to claim 1 is a method for forming a via in a substrate, wherein a through hole forming step of forming a plurality of through holes penetrating in the thickness direction in the substrate, and one surface side of the substrate after the through hole forming step A metal thin film forming step for forming a metal thin film so that each through hole is not blocked at the same time, and after the metal thin film forming step, each through hole and the metal thin film around each through hole are exposed on the one surface side of the substrate A resist layer forming step for forming a resist layer having a plurality of openings, and a plurality of island-shaped conductor portions for closing each through hole on the one surface side of the substrate after the resist layer forming step are formed by electroplating A first electroplating step, an anode disposed opposite to the other surface side of the substrate after the first electroplating step, and a cathode comprising a conductor portion closing each through hole on the one surface side of the substrate Multiple energizing each to become a via A second electroplating step of depositing the genus portion along the thickness direction of the substrate from the exposed surface on the through hole side in each conductor portion; and an unnecessary portion removing step of removing the resist layer after the second electroplating step; It is characterized by providing.

この発明によれば、貫通孔形成工程の後で基板の一表面側に各貫通孔が閉塞されないように金属薄膜を形成した後、基板の前記一表面側に各貫通孔および各貫通孔の周部の金属薄膜を露出させる複数の開口部を有するレジスト層を形成してから、基板の前記一表面側に各貫通孔を閉塞する複数の島状の導体部を電気めっきにより形成し、その後で基板の他表面側に対向配置した陽極と基板の前記一表面側において各貫通孔を閉塞している導体部からなる陰極との間に通電してそれぞれビアとなる複数の金属部を各導体部における貫通孔側の露出表面から基板の厚み方向に沿って析出させ、その後、レジスト層を除去するので、基板の前記一表面側において各貫通孔を閉塞する複数の導体部が島状に形成されており、基板の前記一表面側の全体に連続した導体部が形成されている場合に比べて、めっき応力を低減でき、基板の反りを低減できる。   According to this invention, after forming the metal thin film so that each through hole is not blocked on one surface side of the substrate after the through hole forming step, each through hole and the periphery of each through hole are formed on the one surface side of the substrate. Forming a resist layer having a plurality of openings exposing the metal thin film, and then forming a plurality of island-shaped conductor portions for closing each through hole on the one surface side of the substrate by electroplating, A plurality of metal portions each serving as a via by energizing between an anode arranged opposite to the other surface side of the substrate and a cathode composed of a conductor portion blocking each through hole on the one surface side of the substrate, each conductor portion Since the resist layer is removed from the exposed surface on the through hole side in the substrate, and then the resist layer is removed, a plurality of conductor portions for closing each through hole on the one surface side of the substrate are formed in an island shape. And the whole of the one surface side of the substrate As compared with the case where continuous conductor part is formed, the plating stress can be reduced, thereby reducing the warp of the substrate.

請求項２の発明は、請求項１の発明において、前記基板が半導体基板であり、前記貫通孔形成工程と前記金属薄膜形成工程との間に、前記基板の前記一表面および前記他表面および前記各貫通孔の内周面に絶縁膜を形成する絶縁膜形成工程を備えることを特徴とする。   The invention of claim 2 is the invention of claim 1, wherein the substrate is a semiconductor substrate, and the one surface and the other surface of the substrate and the surface between the through hole forming step and the metal thin film forming step. An insulating film forming step of forming an insulating film on the inner peripheral surface of each through hole is provided.

この発明によれば、前記基板として半導体基板を用いた場合には、前記金属薄膜を形成する前に前記基板の前記一表面および前記他表面および前記各貫通孔の内周面に絶縁膜が形成されているので、前記ビアと前記基板とが電気的に接続されるのを防止することができる。   According to this invention, when a semiconductor substrate is used as the substrate, an insulating film is formed on the one surface and the other surface of the substrate and the inner peripheral surface of each through-hole before forming the metal thin film. Therefore, the via and the substrate can be prevented from being electrically connected.

請求項３の発明は、請求項１または請求項２の発明において、前記各導体部が前記基板の前記一表面側の導体パターンを兼ねるものであり、前記レジスト層形成工程では、前記開口部の開口形状を前記導体パターンに合わせて設定してあることを特徴とする。   According to a third aspect of the present invention, in the first or second aspect of the present invention, each of the conductor portions also serves as a conductor pattern on the one surface side of the substrate. In the resist layer forming step, The opening shape is set according to the conductor pattern.

この発明によれば、前記不要部除去工程の後に残った前記各導体部を導体パターンとして利用することができる。   According to this invention, each said conductor part remaining after the said unnecessary part removal process can be utilized as a conductor pattern.

請求項１の発明では、基板の反りを低減できるという効果がある。   In the invention of claim 1, there is an effect that the warpage of the substrate can be reduced.

以下、本実施形態では、基板へのビアの形成方法を利用して形成されるデバイスの一例としての発光装置について図８〜図１０に基づいて説明してから、基板へのビアの形成方法について図１〜図７に基づいて説明する。   Hereinafter, in the present embodiment, a light emitting device as an example of a device formed using a method for forming a via on a substrate will be described with reference to FIGS. 8 to 10 and then a method for forming a via on a substrate. This will be described with reference to FIGS.

発光装置は、図８および図９に示すように、ＬＥＤチップからなる発光素子１と、発光素子１を収納する収納凹所２ａが一表面に形成された実装基板２と、実装基板２の上記一表面側において収納凹所２ａを閉塞する形で実装基板２に固着された透光性部材３と、実装基板２に設けられ発光素子１から放射された光を検出する光検出素子（受光素子）４と、実装基板２の収納凹所２ａに充填された透光性材料（例えば、シリコーン樹脂、アクリル樹脂、エポキシ樹脂、ポリカーボネート樹脂、ガラスなど）からなり発光素子１および当該発光素子１に電気的に接続されたボンディングワイヤ１４を封止した封止部５と備えている。ここで、実装基板２は、上記一表面側において収納凹所２ａの周部から内方へ突出した庇状の突出部２ｃを有しており、当該突出部２ｃに光検出素子４が設けられている。   As shown in FIGS. 8 and 9, the light-emitting device includes a light-emitting element 1 made of an LED chip, a mounting substrate 2 in which a housing recess 2 a for storing the light-emitting element 1 is formed on one surface, and the above-described mounting board 2. A translucent member 3 fixed to the mounting substrate 2 so as to close the housing recess 2a on one surface side, and a light detecting element (light receiving element) provided on the mounting substrate 2 for detecting light emitted from the light emitting element 1 ) 4 and a light-transmitting material (for example, silicone resin, acrylic resin, epoxy resin, polycarbonate resin, glass, etc.) filled in the housing recess 2a of the mounting substrate 2, the light emitting element 1 and the light emitting element 1 are electrically And the sealing part 5 which sealed the bonding wire 14 connected in general. Here, the mounting substrate 2 has a hook-like protrusion 2c protruding inward from the peripheral portion of the housing recess 2a on the one surface side, and the light detection element 4 is provided on the protrusion 2c. ing.

実装基板２は、発光素子１が一表面側に実装される矩形板状のベース基板２０と、ベース基板２０の上記一表面側に対向配置され円形状の光取出窓４１が形成されるとともに光検出素子４が形成された光検出素子形成基板４０と、ベース基板２０と光検出素子形成基板４０との間に介在し光取出窓４１に連通する矩形状の開口窓３１が形成された中間層基板３０とで構成されており、ベース基板２０と中間層基板３０と光検出素子形成基板４０とで囲まれた空間が上記収納凹所２ａを構成している。ここにおいて、ベース基板２０および中間層基板３０および光検出素子形成基板４０の外周形状は矩形状であり、中間層基板３０および光検出素子形成基板４０はベース基板２０と同じ外形寸法に形成されている。また、光検出素子形成基板４０の厚み寸法はベース基板２０および中間層基板３０の厚み寸法に比べて小さく設定されている。本実施形態では、光検出素子形成基板４０において中間層基板３０の開口窓３１上に張り出した部位が、上述の突出部２ｃを構成している。なお、本実施形態では、実装基板２と透光性部材３とでパッケージを構成しているが、透光性部材３は、必ずしも設けなくてもよく、必要に応じて適宜設ければよい。また、実装基板２における光検出素子形成基板４０も必ずしも設ける必要はない。   The mounting substrate 2 includes a rectangular plate-like base substrate 20 on which the light-emitting element 1 is mounted on one surface side, and a circular light extraction window 41 formed on the one surface side of the base substrate 20 so as to face the light. A light detection element forming substrate 40 on which the detection element 4 is formed, and an intermediate layer in which a rectangular opening window 31 that is interposed between the base substrate 20 and the light detection element formation substrate 40 and communicates with the light extraction window 41 is formed. A space surrounded by the base substrate 20, the intermediate layer substrate 30, and the photodetecting element forming substrate 40 constitutes the housing recess 2a. Here, the outer peripheral shapes of the base substrate 20, the intermediate layer substrate 30, and the light detection element formation substrate 40 are rectangular, and the intermediate layer substrate 30 and the light detection element formation substrate 40 are formed to have the same outer dimensions as the base substrate 20. Yes. Further, the thickness dimension of the light detection element forming substrate 40 is set smaller than the thickness dimension of the base substrate 20 and the intermediate layer substrate 30. In the present embodiment, a portion of the light detection element forming substrate 40 that protrudes over the opening window 31 of the intermediate layer substrate 30 constitutes the above-described protruding portion 2c. In the present embodiment, the package is constituted by the mounting substrate 2 and the translucent member 3, but the translucent member 3 is not necessarily provided, and may be appropriately provided as necessary. Further, the light detection element forming substrate 40 in the mounting substrate 2 is not necessarily provided.

上述のベース基板２０、中間層基板３０、光検出素子形成基板４０は、それぞれ、導電形がｎ形で主表面が（１００）面のシリコン基板（半導体基板）２０ａ，３０ａ，４０ａを用いて形成してある。ここにおいて、中間層基板３０は、開口窓３１の内側面が、アルカリ系溶液（例えば、ＴＭＡＨ溶液、ＫＯＨ溶液など）を用いた異方性エッチングにより形成された（１１１）面により構成されており（つまり、中間層基板３０は、開口窓３１の開口面積がベース基板２０から離れるにつれて徐々に大きくなっており）、発光素子１から放射された光を前方へ反射するミラーを構成している。   The base substrate 20, the intermediate layer substrate 30, and the light detection element formation substrate 40 described above are formed using silicon substrates (semiconductor substrates) 20a, 30a, and 40a having an n-type conductivity and a (100) principal surface, respectively. It is. Here, in the intermediate layer substrate 30, the inner surface of the opening window 31 is constituted by a (111) surface formed by anisotropic etching using an alkaline solution (for example, TMAH solution, KOH solution, etc.). (That is, the intermediate layer substrate 30 gradually increases as the opening area of the opening window 31 increases from the base substrate 20), and constitutes a mirror that reflects light emitted from the light emitting element 1 forward.

ベース基板２０は、シリコン基板２０ａの一表面側（図８における上面側）に、発光素子１の両電極それぞれと電気的に接続される２つの導体パターン２５ａ，２５ａが形成されるとともに、中間層基板３０に形成された後述の２つのビア３４，３４（以下、貫通孔配線３４，３４とも称する）を介して光検出素子４と電気的に接続される２つの導体パターン２５ｂ，２５ｂが形成されており、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂとシリコン基板２０ａの他表面側（図８における右面側）に形成された４つの外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂとがそれぞれ配線用のビア２４（以下、貫通孔配線２４ａとも称する）を介して電気的に接続されている。また、ベース基板２０は、シリコン基板２０ａの上記一表面側に、中間層基板３０と接合するための接合用金属層２９も形成されている。   In the base substrate 20, two conductor patterns 25a and 25a electrically connected to both electrodes of the light emitting element 1 are formed on one surface side (the upper surface side in FIG. 8) of the silicon substrate 20a, and an intermediate layer is formed. Two conductor patterns 25b and 25b are formed which are electrically connected to the photodetecting element 4 through two vias 34 and 34 (hereinafter also referred to as through-hole wirings 34 and 34) formed on the substrate 30. Each of the conductor patterns 25a, 25a, 25b, and 25b and the four external connection electrodes 27a, 27a, 27b, and 27b formed on the other surface side (right side in FIG. 8) of the silicon substrate 20a are used for wiring. The vias 24 (hereinafter also referred to as through-hole wiring 24a) are electrically connected. The base substrate 20 is also formed with a bonding metal layer 29 for bonding to the intermediate layer substrate 30 on the one surface side of the silicon substrate 20a.

本実施形態における発光素子１は、結晶成長用基板として導電性基板を用い厚み方向の両面に電極（図示せず）が形成された可視光ＬＥＤチップである。そこで、ベース基板２０は、発光素子１が電気的に接続される２つの導体パターン２５ａ，２５ａのうちの一方の導体パターン２５ａを、発光素子１がダイボンディングされる矩形状のダイパッド部２５ａａと、ダイパッド部２５ａａに連続一体に形成され貫通孔配線２４ａとの接続部位となる引き出し配線部２５ａｂとで構成してある。要するに、発光素子１は、上記一方の導体パターン２５ａのダイパッド部２５ａａにダイボンディングされており、ダイパッド部２５ａａ側の電極がダイパッド部２５ａａに接合されて電気的に接続され、光取り出し面側の電極がボンディングワイヤ１４を介して他方の導体パターン２５ａと電気的に接続されている。なお、発光素子１としては、光取出し面側に両電極が形成されたものを用いてもよい。   The light-emitting element 1 in this embodiment is a visible light LED chip in which a conductive substrate is used as a crystal growth substrate and electrodes (not shown) are formed on both surfaces in the thickness direction. Therefore, the base substrate 20 has one of the two conductor patterns 25a and 25a to which the light emitting element 1 is electrically connected, a rectangular die pad portion 25aa to which the light emitting element 1 is die-bonded, and The lead-out wiring part 25ab is formed integrally with the die pad part 25aa and is connected to the through-hole wiring 24a. In short, the light emitting element 1 is die-bonded to the die pad portion 25aa of the one conductor pattern 25a, the electrode on the die pad portion 25aa side is joined and electrically connected to the die pad portion 25aa, and the electrode on the light extraction surface side. Is electrically connected to the other conductor pattern 25 a via the bonding wire 14. In addition, as the light emitting element 1, you may use the thing in which both electrodes were formed in the light extraction surface side.

また、ベース基板２０は、シリコン基板２０ａの上記他表面側に、シリコン基板２０ａよりも熱伝導率の高い金属材料からなる矩形状の放熱用パッド部２８が形成されており、ダイパッド部２５ａａと放熱用パッド部２８とがシリコン基板２０ａよりも熱伝導率の高い金属材料（例えば、Ｃｕなど）からなる複数（本実施形態では、９個）の円柱状のビア２４（以下、サーマルビア２４ｂとも称する）を介して熱的に結合されており、発光素子１で発生した熱が各サーマルビア２４ｂおよび放熱用パッド部２８を介して放熱されるようになっている。   The base substrate 20 has a rectangular heat radiation pad portion 28 made of a metal material having a higher thermal conductivity than the silicon substrate 20a on the other surface side of the silicon substrate 20a. A plurality of (in this embodiment, nine) cylindrical vias 24 (hereinafter also referred to as thermal vias 24b) made of a metal material (for example, Cu) having a thermal conductivity higher than that of the silicon substrate 20a. The heat generated in the light emitting element 1 is dissipated through the thermal vias 24b and the heat dissipating pad portion 28.

ところで、ベース基板２０は、シリコン基板２０ａに、上述の各ビア２４それぞれが内側に形成される複数の貫通孔２２が厚み方向に貫設され、シリコン基板２０ａの上記一表面および上記他表面と各貫通孔２２の内面とに跨って熱酸化膜（シリコン酸化膜）からなる絶縁膜２３が形成されており、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９、各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂ、放熱用パッド部２８、各ビア２４がシリコン基板２０ａと電気的に絶縁されている。   By the way, the base substrate 20 has a plurality of through-holes 22 formed in the thickness direction in the silicon substrate 20a, in which each of the above-described vias 24 is formed. An insulating film 23 made of a thermal oxide film (silicon oxide film) is formed across the inner surface of the through hole 22, and each conductor pattern 25 a, 25 a, 25 b, 25 b, the bonding metal layer 29, each external connection electrode 27a, 27a, 27b, 27b, the heat radiation pad portion 28, and each via 24 are electrically insulated from the silicon substrate 20a.

ここにおいて、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９、各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂ、放熱用パッド部２８は、絶縁膜２３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、シリコン基板２０ａの上記一表面側の各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９が同時に形成され、シリコン基板２０ａの上記他表面側の各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂ、放熱用パッド部２８が同時に形成されている。なお、本実施形態では、絶縁膜２３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。また、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜２３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。また、ビア２４の材料としては、Ｃｕを採用しているが、Ｃｕに限らず、例えば、Ｎｉ、Ａｌなどを採用してもよい。   Here, each conductor pattern 25a, 25a, 25b, 25b, bonding metal layer 29, each external connection electrode 27a, 27a, 27b, 27b, and heat radiation pad portion 28 are formed on the insulating film 23. And the Au film formed on the Ti film, the conductor patterns 25a, 25a, 25b, 25b on the one surface side of the silicon substrate 20a and the bonding metal layer 29 are simultaneously formed. The external connection electrodes 27a, 27a, 27b, 27b on the other surface side of the silicon substrate 20a and the heat dissipation pad portion 28 are formed at the same time. In this embodiment, the thickness of the Ti film on the insulating film 23 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Further, the material of each Au film is not limited to pure gold, and may be one added with impurities. In addition, although a Ti film is interposed as an adhesion layer for improving adhesion between each Au film and the insulating film 23, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. Moreover, although Cu is adopted as the material of the via 24, it is not limited to Cu, and for example, Ni, Al, etc. may be adopted.

中間層基板３０は、シリコン基板３０ａの一表面側（図８における下面側）に、ベース基板２０の２つの接続用金属層（以下、第１の接続用金属層と称す）２５ｂ，２５ｂと接合されて電気的に接続される２つの第２の接続用金属層（図示せず））３５，３５が形成されるとともに、ベース基板２０の接合用金属層２９と接合される接合用金属層３６が形成されている。また、中間層基板３０は、シリコン基板３０ａの他表面側（図８における上面側）に、貫通孔配線３４，３４を介して各第２の接続用金属層３５，３５と電気的に接続される２つの第３の接続用金属層３７，３７が形成されるとともに、光検出素子形成基板４０と接合するための接合用金属層３８（図９参照）が形成されている。   The intermediate layer substrate 30 is bonded to two connection metal layers (hereinafter referred to as first connection metal layers) 25b and 25b of the base substrate 20 on one surface side (the lower surface side in FIG. 8) of the silicon substrate 30a. Then, two second connection metal layers (not shown) 35 and 35 that are electrically connected to each other are formed, and the bonding metal layer 36 bonded to the bonding metal layer 29 of the base substrate 20 is formed. Is formed. Further, the intermediate layer substrate 30 is electrically connected to the second connection metal layers 35 and 35 via the through-hole wirings 34 and 34 on the other surface side (the upper surface side in FIG. 8) of the silicon substrate 30a. Two third connection metal layers 37, 37 are formed, and a bonding metal layer 38 (see FIG. 9) for bonding to the photodetecting element forming substrate 40 is formed.

また、中間層基板３０は、上述の２つの貫通孔配線３４それぞれが内側に形成される２つの貫通孔３２がシリコン基板３０ａの厚み方向に貫設され、シリコン基板３０ａの上記一表面および上記他表面と各貫通孔３２の内面とに跨って熱酸化膜（シリコン酸化膜）からなる絶縁膜３３が形成されており、第２の接続用金属層３５，３５、第３の接続用金属層３７，３７および各接合用金属層３６，３８がシリコン基板３０ａと電気的に絶縁されている。ここにおいて、第２の接続用金属層３５，３５、第３の接続用金属層３７，３７および各接合用金属層３６，３８は、絶縁膜３３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、シリコン基板３０ａの上記一表面側の第２の接続用金属層３５，３５と接合用金属層３６とが同時に形成され、シリコン基板３０ａの上記他表面側の第３の接続用金属層３７，３７と接合用金属層３８とが同時に形成されている。なお、本実施形態では、絶縁膜３３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。ここにおいて、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜３３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。また、貫通孔配線３４の材料としては、Ｃｕを採用しているが、Ｃｕに限らず、例えば、Ｎｉ、Ａｌなどを採用してもよい。   Further, the intermediate layer substrate 30 has two through holes 32 formed therein in the thickness direction of the silicon substrate 30a, and the one surface of the silicon substrate 30a and the other. An insulating film 33 made of a thermal oxide film (silicon oxide film) is formed across the surface and the inner surface of each through hole 32, and the second connection metal layers 35, 35 and the third connection metal layer 37 are formed. , 37 and the bonding metal layers 36, 38 are electrically insulated from the silicon substrate 30a. Here, the second connecting metal layers 35, 35, the third connecting metal layers 37, 37, and the joining metal layers 36, 38 are formed on the Ti film formed on the insulating film 33 and the Ti film. The second connecting metal layers 35, 35 and the bonding metal layer 36 on the one surface side of the silicon substrate 30a are formed at the same time to form the silicon substrate 30a. The third connecting metal layers 37 and 37 on the other surface side and the joining metal layer 38 are formed simultaneously. In this embodiment, the thickness of the Ti film on the insulating film 33 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Here, the material of each Au film is not limited to pure gold, and may be added with impurities. Further, although a Ti film is interposed as an adhesion improving layer for adhesion between each Au film and the insulating film 33, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. Further, although Cu is adopted as the material of the through-hole wiring 34, it is not limited to Cu, and for example, Ni, Al or the like may be adopted.

光検出素子形成基板４０は、シリコン基板４０ａの一表面側（図８における下面側）に、中間層基板３０の２つの接続用金属層３７，３７と接合されて電気的に接続される２つの第４の接続用金属層４７，４７が形成されるとともに、中間層基板３０の接合用金属層３８と接合される接合用金属層（図示せず）が形成されている。ここにおいて、光検出素子４は、フォトダイオードにより構成されており、光検出素子形成基板４０に形成された２つの第４の接続用金属層４７，４７の一方の第４の接続用金属層４７が、光検出素子４を構成するフォトダイオードのｐ形領域４ａに電気的に接続され、他方の第４の接続用金属層４７が、上記フォトダイオードのｎ形領域４ｂを構成するシリコン基板４０ａに電気的に接続されている。   The photodetecting element forming substrate 40 is bonded to and electrically connected to two connecting metal layers 37, 37 of the intermediate layer substrate 30 on one surface side (the lower surface side in FIG. 8) of the silicon substrate 40a. The fourth connection metal layers 47 and 47 are formed, and a bonding metal layer (not shown) to be bonded to the bonding metal layer 38 of the intermediate layer substrate 30 is formed. Here, the photodetecting element 4 is constituted by a photodiode, and one of the four fourth connecting metal layers 47, 47 formed on the photodetecting element forming substrate 40 is the fourth connecting metal layer 47. Is electrically connected to the p-type region 4a of the photodiode constituting the photodetecting element 4, and the other fourth connecting metal layer 47 is formed on the silicon substrate 40a constituting the n-type region 4b of the photodiode. Electrically connected.

また、光検出素子形成基板４０は、シリコン基板４０ａの上記一表面側にシリコン酸化膜からなる絶縁膜４３が形成されており、当該絶縁膜４３がフォトダイオードの反射防止膜を兼ねている。また、光検出素子形成基板４０は、上記一方の第４の接続用金属層４７が、絶縁膜４３に形成したコンタクトホール４３ａを通してｐ形領域４ａと電気的に接続され、上記他方の第４の接続用金属層４７が絶縁膜４３に形成したコンタクトホール４３ｂを通してｎ形領域４ｂと電気的に接続されている。ここにおいて、２つの第４の接続用金属層４７，４７および上記接合用金属層は、絶縁膜４３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、同時に形成してある。なお、本実施形態では、絶縁膜４３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。ここにおいて、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜４３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。   Further, in the photodetecting element forming substrate 40, an insulating film 43 made of a silicon oxide film is formed on the one surface side of the silicon substrate 40a, and the insulating film 43 also serves as an antireflection film of the photodiode. In the photodetecting element forming substrate 40, the one fourth connecting metal layer 47 is electrically connected to the p-type region 4a through a contact hole 43a formed in the insulating film 43, and the other fourth connecting metal layer 47 is connected. The connecting metal layer 47 is electrically connected to the n-type region 4 b through a contact hole 43 b formed in the insulating film 43. Here, the two fourth connecting metal layers 47, 47 and the bonding metal layer are constituted by a laminated film of a Ti film formed on the insulating film 43 and an Au film formed on the Ti film. Are formed at the same time. In this embodiment, the thickness of the Ti film on the insulating film 43 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Here, the material of each Au film is not limited to pure gold, and may be added with impurities. Further, although a Ti film is interposed as an adhesion improving layer for adhesion between each Au film and the insulating film 43, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used.

上述の実装基板２の形成にあたっては、例えば、光検出素子４、絶縁膜４３、各第４の接続用金属層４７，４７、および上記接合用金属層が形成されたシリコン基板４０ａと中間層基板３０とを接合する第１の接合工程を行った後、シリコン基板４０ａを所望の厚みまで研磨する研磨工程を行い、その後、ＩＣＰ型のドライエッチング装置などを用いてシリコン基板４０ａに光取出窓４１を形成する光取出窓形成工程を行うことで光検出素子形成基板４０を完成させてから、発光素子１が実装されたベース基板２０（発光素子１が搭載されボンディングワイヤ１４の結線が行われたベース基板２０）と中間層基板３０とを接合する第２の接合工程を行うようにすればよい。ここにおいて、第１の接合工程、第２の接合工程では、接合前に互いの接合表面へアルゴンのプラズマ若しくはイオンビーム若しくは原子ビームを真空中で照射して各接合表面の清浄化・活性化を行ってから、接合表面同士を接触させ、常温下で直接接合する常温接合法を採用しているが、常温接合法に限らず、上述の各接合表面の正常化・活性化を行ってから、接合表面を接触させ常温よりも高い規定温度（例えば、８０℃）で直接接合するようにしてもよい。   In forming the mounting substrate 2 described above, for example, the photodetector 4, the insulating film 43, the fourth connection metal layers 47 and 47, and the silicon substrate 40 a and the intermediate layer substrate on which the bonding metal layer is formed. After performing the first bonding step for bonding to the substrate 30, a polishing step for polishing the silicon substrate 40a to a desired thickness is performed, and then a light extraction window 41 is formed on the silicon substrate 40a using an ICP type dry etching apparatus or the like. The light detection element forming substrate 40 is completed by performing the light extraction window forming step of forming the base substrate 20 on which the light emitting element 1 is mounted (the light emitting element 1 is mounted and the bonding wire 14 is connected). A second bonding step for bonding the base substrate 20) and the intermediate layer substrate 30 may be performed. Here, in the first bonding step and the second bonding step, each bonding surface is cleaned and activated by irradiating each bonding surface with argon plasma, ion beam or atomic beam in vacuum before bonding. After performing the normal temperature bonding method of contacting the bonding surfaces together and directly bonding at normal temperature, but not limited to the normal temperature bonding method, after normalizing and activating each of the above-mentioned bonding surfaces, The bonding surfaces may be brought into contact and directly bonded at a specified temperature higher than room temperature (for example, 80 ° C.).

上述の第１の接合工程では、シリコン基板４０ａの上記一表面側の上記接合用金属層と中間層基板３０の接合用金属層３８とが接合されるとともに、シリコン基板４０ａの上記一表面側の第４の接続用金属層４７，４７と中間層基板３０の第３の接続用金属層３７，３７とが接合され電気的に接続される。ここで、第４の接続用金属層４７，４７と第３の接続用金属層３７，３７との接合部位が、貫通孔配線３４に重なる領域からずれるようにパターン設計しておけば、第４の接続用金属層４７，４７と第３の接続用金属層３７，３７との互いの接合面の平坦度を高めることができ、特に常温接合法により接合する際の接合歩留まりを高めることができるとともに接合信頼性を高めることができる。また、第２の接合工程では、ベース基板２０の接合用金属層２９と中間層基板３０の接合用金属層３６とが接合されるとともに、ベース基板２０の第１の接続用金属層２５ｂ，２５ｂと中間層基板３０の第２の接続用金属層３５，３５とが接合され電気的に接続される。ここで、本実施形態では、第１の接続用金属層２５ｂ，２５ｂと第２の接続用金属層３５，３５との接合部位を、貫通孔配線２４ａに重なる領域および貫通孔配線３４に重なる領域からずらしてあるので、第１の接続用金属層２５ｂ，２５ｂと第２の接続用金属層３５，３５との互いの接合面の平坦度を高めることができ、特に常温接合法により接合する際の接合歩留まりを高めることができるとともに接合信頼性を高めることができる。   In the first bonding step, the bonding metal layer on the one surface side of the silicon substrate 40a and the bonding metal layer 38 of the intermediate layer substrate 30 are bonded, and the one surface side of the silicon substrate 40a is bonded. The fourth connection metal layers 47 and 47 and the third connection metal layers 37 and 37 of the intermediate layer substrate 30 are joined and electrically connected. Here, if the pattern design is made so that the joint portion between the fourth connection metal layers 47 and 47 and the third connection metal layers 37 and 37 is shifted from the region overlapping the through-hole wiring 34, The flatness of the bonding surfaces of the connecting metal layers 47 and 47 and the third connecting metal layers 37 and 37 can be increased, and in particular, the bonding yield when bonded by the room temperature bonding method can be increased. At the same time, the bonding reliability can be improved. Further, in the second bonding step, the bonding metal layer 29 of the base substrate 20 and the bonding metal layer 36 of the intermediate layer substrate 30 are bonded, and the first connection metal layers 25b and 25b of the base substrate 20 are bonded. And the second connecting metal layers 35 of the intermediate layer substrate 30 are joined and electrically connected. Here, in the present embodiment, the joint portions of the first connection metal layers 25b and 25b and the second connection metal layers 35 and 35 are regions overlapping the through-hole wiring 24a and regions overlapping the through-hole wiring 34. Therefore, the flatness of the joint surfaces of the first connection metal layers 25b and 25b and the second connection metal layers 35 and 35 can be increased. The bonding yield can be increased and the bonding reliability can be increased.

また、上述の透光性部材３は、透光性材料（例えば、シリコーン樹脂、アクリル樹脂、エポキシ樹脂、ポリカーボネート樹脂、ガラスなど）からなる透光性基板を用いて形成してある。ここで、透光性部材３は、実装基板２と同じ外周形状の矩形板状に形成されており、実装基板２側とは反対の光取り出し面に、発光素子１から放射された光の全反射を抑制する微細凹凸構造が形成されている。ここにおいて、透光性部材３の光取り出し面に形成する微細凹凸構造は、多数の微細な凹部が２次元周期構造を有するように形成されている。なお、上述の微細凹凸構造は、例えば、レーザ加工技術やエッチング技術やインプリントリソグラフィ技術などを利用して形成すればよい。また、微細凹凸構造の周期は、発光素子１の発光ピーク波長の１／４〜１００倍程度の範囲で適宜設定すればよい。   Further, the above-described translucent member 3 is formed using a translucent substrate made of a translucent material (for example, silicone resin, acrylic resin, epoxy resin, polycarbonate resin, glass, or the like). Here, the translucent member 3 is formed in a rectangular plate shape having the same outer peripheral shape as the mounting substrate 2, and all of the light emitted from the light emitting element 1 is formed on the light extraction surface opposite to the mounting substrate 2 side. A fine concavo-convex structure that suppresses reflection is formed. Here, the fine concavo-convex structure formed on the light extraction surface of the translucent member 3 is formed such that many fine concave portions have a two-dimensional periodic structure. The fine concavo-convex structure described above may be formed using, for example, a laser processing technique, an etching technique, an imprint lithography technique, or the like. Further, the period of the fine concavo-convex structure may be appropriately set within a range of about ¼ to 100 times the emission peak wavelength of the light emitting element 1.

本実施形態の発光装置の製造にあたっては、上述の各シリコン基板２０ａ，３０ａ，４０ａとして、それぞれベース基板２０、中間層基板３０、光検出素子形成基板４０を多数形成可能なシリコンウェハを用いるとともに、上述の透光性基板として透光性部材３を多数形成可能なウェハ状のもの（透光性ウェハ）を用い、上述の第１の接合工程、研磨工程、光取出窓形成工程、第２の接合工程、実装基板２の収納凹所２ａに透光性材料を充填して封止部５を形成する封止部形成工程、封止部形成工程の後で実装基板２と透光性部材３とを接合する第３の接合工程などの各工程をウェハレベルで行うことでウェハレベルパッケージ構造体を形成してから、ダイシング工程により実装基板２のサイズに分割されている。したがって、ベース基板２０と中間層基板３０と光検出素子形成基板４０と透光性部材３とが同じ外形サイズとなり、小型のパッケージを実現できるとともに、製造が容易になる。また、中間層基板３０におけるミラーと光検出素子形成基板４０における光検出素子４との相対的な位置精度を高めることができ、発光素子１から側方へ放射された光がミラーにより反射されて光検出素子４へ導かれる。   In manufacturing the light emitting device of the present embodiment, as each of the silicon substrates 20a, 30a, and 40a described above, a silicon wafer capable of forming a large number of the base substrate 20, the intermediate layer substrate 30, and the light detection element forming substrate 40 is used. A wafer-like one (translucent wafer) capable of forming a large number of translucent members 3 is used as the above-described translucent substrate, and the above-described first bonding step, polishing step, light extraction window forming step, second step The mounting substrate 2 and the translucent member 3 after the joining step, the sealing portion forming step of forming the sealing portion 5 by filling the housing recess 2a of the mounting substrate 2 with the translucent material, and the sealing portion forming step. The wafer level package structure is formed by performing each process such as a third bonding process for bonding the two at the wafer level, and then divided into the size of the mounting substrate 2 by the dicing process. Therefore, the base substrate 20, the intermediate layer substrate 30, the light detection element formation substrate 40, and the translucent member 3 have the same outer size, so that a small package can be realized and manufacturing is facilitated. Further, the relative positional accuracy between the mirror in the intermediate layer substrate 30 and the light detection element 4 in the light detection element formation substrate 40 can be improved, and the light emitted from the light emitting element 1 to the side is reflected by the mirror. It is guided to the light detection element 4.

上述の発光装置では、発光素子１として可視光ＬＥＤチップを用いているが、発光素子１は、可視光ＬＥＤチップに限らず、紫外光ＬＥＤチップや、ＬＥＤチップと当該ＬＥＤチップに積層され少なくとも当該ＬＥＤチップから放射された光によって励起されて当該ＬＥＤチップよりも長波長の光を放射する蛍光体により形成された蛍光体層とで構成されたものや、有機ＥＬ素子でもよい。また、発光素子１としては、例えば、結晶成長用基板の主表面側に発光部などをエピタキシャル成長した後に発光部を支持する導電性基板（例えば、Ｓｉ基板など）を発光部に固着してから、結晶成長用基板などを除去したものを用いてもよい。また、発光素子１の数は、１個に限らず、発光色が同じ或いは異なる複数の発光素子を用いてもよい
また、光検出素子４は、フォトダイオードに限らず、例えば、フォトダイオードとカラーフィルタとを組み合わせたカラーセンサや、フォトダイオードと波長選択フィルタとを組み合わせたものなどでもよい。また、光検出素子４は、必ずしも設ける必要はない。 In the light emitting device described above, a visible light LED chip is used as the light emitting element 1, but the light emitting element 1 is not limited to the visible light LED chip, but is stacked on the ultraviolet light LED chip or the LED chip and the LED chip. It may be composed of a phosphor layer formed of a phosphor that is excited by light emitted from the LED chip and emits light having a longer wavelength than the LED chip, or may be an organic EL element. In addition, as the light emitting element 1, for example, after a light emitting portion or the like is epitaxially grown on the main surface side of the crystal growth substrate, a conductive substrate (for example, a Si substrate) that supports the light emitting portion is fixed to the light emitting portion. You may use what removed the board | substrate for crystal growth. The number of the light emitting elements 1 is not limited to one, and a plurality of light emitting elements having the same or different emission colors may be used. The light detecting element 4 is not limited to a photodiode, and may be, for example, a photodiode and a color. A color sensor combined with a filter, or a combination of a photodiode and a wavelength selection filter may be used. Further, the light detection element 4 is not necessarily provided.

以下、上述のシリコン基板２０ａ（以下、基板２０ａという）へのビア２４の形成方法について図１〜図７に基づいて説明する。   Hereinafter, a method for forming the via 24 in the above-described silicon substrate 20a (hereinafter referred to as the substrate 20a) will be described with reference to FIGS.

まず、基板２０ａの一表面側（ここでは、シリコン基板２０ａの上記他表面側）および他表面側（ここでは、シリコン基板２０ａの上記一表面側）に熱酸化法によってシリコン酸化膜を形成する酸化膜形成工程を行い、その後、基板２０ａにビア２４形成用の貫通孔２２を形成する際のマスクを形成するために、フォトリソグラフィ技術およびエッチング技術を利用して基板２０ａの上記他表面側のシリコン酸化膜をパターニングし、当該パターニングされたシリコン酸化膜をマスクとして、例えば誘導結合プラズマ（ＩＣＰ）型のエッチング装置により基板２０ａを上記一表面側から上記他表面側のシリコン酸化膜に達するまでドライエッチングすることで基板２０ａの厚み方向に貫通する複数の貫通孔２２を形成する貫通孔形成工程を行い、続いて、各シリコン酸化膜をエッチング除去する酸化膜除去工程を行ってから、基板２０ａの上記一表面側および上記他表面側および各貫通孔２２の内面（内周面）に熱酸化法によってシリコン酸化膜からなる絶縁膜２３を形成する絶縁膜形成工程を行い、更にその後、基板２０ａの上記一表面側に各貫通孔２２が閉塞されないように金属材料からなる金属薄膜２６をスパッタ法などにより形成する金属薄膜形成工程を行うことによって、図１（ａ）に示す構造を得る。なお、金属薄膜形成工程にて形成される金属薄膜２６の一部は、基板２０ａの上記一表面側において各貫通孔２２の内側にも形成される。なお、本実施形態では、金属薄膜２６を絶縁膜２３上に形成されたＣｒ膜と当該Ｃｒ膜上に形成されたＣｕ膜との積層膜により構成してある。なお、本実施形態では、基板２０ａとして厚さが３００μｍのシリコンウェハ（シリコン基板）を用いており、貫通孔２２の内径を２０μｍに設定し、絶縁膜２３上のＣｒ膜の膜厚を０．０３μｍ、Ｃｒ膜上のＣｕ膜の膜厚を０．４μｍに設定してあるが、これらの数値は一例であって特に限定するものではない。ただし、貫通孔２２の内径については、デバイスの小型化の観点から、５μｍ〜５０μｍの範囲で設定することが好ましい。また、Ｃｕ膜の膜厚については、後述のレジスト層形成工程において表面が酸化されることを考慮して０．２μｍ以上とすることが好ましい。   First, an oxidation for forming a silicon oxide film on one surface side of the substrate 20a (here, the other surface side of the silicon substrate 20a) and the other surface side (here, the one surface side of the silicon substrate 20a) by thermal oxidation. In order to form a mask for forming the through hole 22 for forming the via 24 in the substrate 20a after performing the film forming step, silicon on the other surface side of the substrate 20a is used by using a photolithography technique and an etching technique. Patterning the oxide film, and using the patterned silicon oxide film as a mask, the substrate 20a is dry etched by the inductively coupled plasma (ICP) type etching apparatus until it reaches the silicon oxide film on the other surface side from the one surface side. As a result, a through hole forming step for forming a plurality of through holes 22 penetrating in the thickness direction of the substrate 20a is performed. Subsequently, after performing an oxide film removing step for removing each silicon oxide film by etching, the one surface side and the other surface side of the substrate 20a and the inner surface (inner peripheral surface) of each through hole 22 are thermally oxidized. An insulating film forming step of forming an insulating film 23 made of a silicon oxide film is performed, and then a metal thin film 26 made of a metal material is formed by sputtering or the like so that each through hole 22 is not blocked on the one surface side of the substrate 20a. The structure shown in FIG. 1A is obtained by performing the metal thin film forming step to be formed. A part of the metal thin film 26 formed in the metal thin film forming step is also formed inside each through hole 22 on the one surface side of the substrate 20a. In the present embodiment, the metal thin film 26 is composed of a laminated film of a Cr film formed on the insulating film 23 and a Cu film formed on the Cr film. In this embodiment, a silicon wafer (silicon substrate) having a thickness of 300 μm is used as the substrate 20 a, the inner diameter of the through hole 22 is set to 20 μm, and the film thickness of the Cr film on the insulating film 23 is set to 0. Although the film thickness of the Cu film on the Cr film is set to 03 μm and 0.4 μm, these numerical values are merely examples and are not particularly limited. However, the inner diameter of the through hole 22 is preferably set in the range of 5 μm to 50 μm from the viewpoint of device miniaturization. The film thickness of the Cu film is preferably set to 0.2 μm or more in consideration of the oxidation of the surface in the resist layer forming step described later.

上述の金属薄膜形成工程の後、基板２０ａの上記一表面側に各貫通孔２２および各貫通孔２２の周部の金属薄膜２６を露出させる複数の開口部６１ａを有するレジスト層６１を形成するレジスト層形成工程を行うことによって、図１（ｂ）に示す構造を得る。レジスト層６１の形成にあたっては、感光性のフォトレジストをスピンコート法などにより塗布してから、露光、現像すればよい。   After the above-described metal thin film forming step, a resist for forming a resist layer 61 having a plurality of openings 61a that expose each through hole 22 and the metal thin film 26 around the through hole 22 on the one surface side of the substrate 20a. By performing the layer forming step, the structure shown in FIG. 1B is obtained. In forming the resist layer 61, a photosensitive photoresist may be applied by spin coating or the like, and then exposed and developed.

上述のレジスト層形成工程の後、基板２０ａの上記一表面側に各貫通孔２２を閉塞する複数の島状の導体部２７を電気めっきにより形成する第１の電気めっき工程を行うことによって、図１（ｃ）に示す構造を得る。第１の電気めっき工程では、めっき液として硫酸銅めっき液を用い、基板２０ａの上記一表面側にめっき液を介して対向配置した銅板からなる陽極（図示せず）と基板２０ａの上記一表面側の金属薄膜２６からなる陰極との間に通電することで導体部２７を形成する。   By performing a first electroplating step of forming a plurality of island-like conductor portions 27 for closing each through-hole 22 on the one surface side of the substrate 20a by the electroplating after the resist layer forming step described above, FIG. The structure shown in 1 (c) is obtained. In the first electroplating step, a copper sulfate plating solution is used as a plating solution, and an anode (not shown) made of a copper plate disposed opposite to the one surface side of the substrate 20a via the plating solution and the one surface of the substrate 20a. The conductor portion 27 is formed by energizing the cathode made of the metal thin film 26 on the side.

上述の第１の電気めっき工程の後、めっき液として硫酸銅めっき液を用い、基板２０ａの上記他表面側に対向配置した銅板からなる陽極（図示せず）と基板２０ａの上記一表面側において各貫通孔２２を閉塞している導体部２７からなる陰極との間に通電してそれぞれビア２４となる金属材料（ここでは、Ｃｕ）からなる複数の金属部を各導体部２７における貫通孔２２側の露出表面から基板２０ａの厚み方向に沿って析出させる第２の電気めっき工程を行い（つまり、第２の電気めっき工程では、ビア２４となる金属部をボトムアップ成長させている）、その後、金属部のうちシリコン基板２０ａの上記他表面側に形成された不要部分をＣＭＰなどによって除去する研磨工程を行うことによって、図１（ｄ）に示す構造を得る。なお、上記金属材料は、Ｃｕに限らず、例えば、Ｎｉなどでもよい。   After the first electroplating step, a copper sulfate plating solution is used as a plating solution, and an anode (not shown) made of a copper plate disposed opposite to the other surface side of the substrate 20a and the one surface side of the substrate 20a A plurality of metal parts made of a metal material (here, Cu) that becomes the vias 24 when energized between the cathodes made of the conductor parts 27 closing the through-holes 22 are connected to the through-holes 22 in the conductor parts 27. A second electroplating step for depositing along the thickness direction of the substrate 20a from the exposed surface on the side (that is, in the second electroplating step, the metal portion to be the via 24 is grown bottom-up), and then Then, by performing a polishing process for removing unnecessary portions formed on the other surface side of the silicon substrate 20a in the metal portion by CMP or the like, the structure shown in FIG. 1D is obtained. The metal material is not limited to Cu, and may be Ni, for example.

上述の研磨工程の後でレジスト層６１および当該レジスト層６１下の金属薄膜２６を除去する不要部除去工程を行うことによって、図１（ｅ）に示す構造を得る。ここにおいて、不要部除去工程では、レジスト層６１を有機溶剤などを用いて除去し、その後、金属薄膜２６をエッチング液を用いて除去している。なお、本実施形態では、基板２０ａの上記一表面側の各導体部２７を残して、外部接続用電極２７ａ，２７ｂや放熱用パッド部２８を構成するようにしいているが、各導体部２７をＣＭＰなどによって除去してから、外部接続用電極２７ａ，２７ｂおよび放熱用パッド部２８を形成するようにしてもよい（この場合には、各導体部２７をＣＭＰなどにより除去する際に金属薄膜２６もＣＭＰなどにより除去するようにしてもよい）。なお、上述のベース基板２０を完成させるには、不要部除去工程の後で、基板２０ａの上記他表面側に、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９を、薄膜形成技術、フォトリソグラフィ技術およびエッチング技術を利用して同時に形成すればよい。   A structure shown in FIG. 1E is obtained by performing an unnecessary portion removing step of removing the resist layer 61 and the metal thin film 26 under the resist layer 61 after the above-described polishing step. Here, in the unnecessary portion removing step, the resist layer 61 is removed using an organic solvent or the like, and then the metal thin film 26 is removed using an etching solution. In the present embodiment, the external connection electrodes 27a and 27b and the heat dissipating pad portion 28 are configured by leaving the conductor portions 27 on the one surface side of the substrate 20a. The external connection electrodes 27a and 27b and the heat radiation pad portion 28 may be formed after removal by CMP or the like (in this case, the metal thin film 26 is removed when each conductor portion 27 is removed by CMP or the like). May also be removed by CMP or the like). In order to complete the above-described base substrate 20, the conductive patterns 25a, 25a, 25b, and 25b and the bonding metal layer 29 are formed on the other surface side of the substrate 20a after the unnecessary portion removing step. It may be formed simultaneously using a technique, a photolithography technique, and an etching technique.

ところで、本実施形態の基板２０ａのビア２４の形成方法においては、上述の第１の電気めっき工程において、めっき液（硫酸銅めっき液）に、めっき促進剤７１およびめっき抑制剤７２を添加しており、ここにおいて、めっき促進剤７１は、図２（ａ）に示すように、貫通孔２２の内側の金属薄膜２６の表面に多く付着してめっきを促進させる機能を有し、めっき抑制剤７２は、基板２０ａの上記一表面側で金属薄膜２６の表面に多く付着してめっきを抑制する機能を有している。したがって、めっき液中にめっき促進剤７１およびめっき抑制剤７２を添加剤として添加しておくことにより、これら添加剤の作用により貫通孔２２を閉塞しやすくなり、めっき促進剤７１およびめっき抑制剤７２を添加していないめっき液を用いた場合に形成される導体部２７（図３参照）に比べて、図２（ｂ）に示すように導体部２７の厚みを薄くすることができる。なお、めっき促進剤７１として、例えば、ビス（３−スルホプロピル）ジスルフィド（ＳＰＳ）を用い、めっき抑制剤７２として、分子量が３０００〜８０００のポリエチレングリコール（ＰＥＧ）を用いているが、これらの材料は特に限定するものではない。   By the way, in the formation method of the via | veer 24 of the board | substrate 20a of this embodiment, the plating accelerator 71 and the plating inhibitor 72 are added to a plating solution (copper sulfate plating solution) in the above-mentioned 1st electroplating process. Here, as shown in FIG. 2A, the plating accelerator 71 has a function of adhering to the surface of the metal thin film 26 inside the through hole 22 to promote plating, and a plating inhibitor 72. Has a function of suppressing the plating by adhering to the surface of the metal thin film 26 on the one surface side of the substrate 20a. Therefore, by adding the plating accelerator 71 and the plating inhibitor 72 as additives in the plating solution, the through holes 22 can be easily blocked by the action of these additives, so that the plating accelerator 71 and the plating inhibitor 72 are added. As shown in FIG. 2B, the thickness of the conductor 27 can be reduced as compared with the conductor 27 (see FIG. 3) formed when a plating solution to which no is added is used. As the plating accelerator 71, for example, bis (3-sulfopropyl) disulfide (SPS) is used, and as the plating inhibitor 72, polyethylene glycol (PEG) having a molecular weight of 3000 to 8000 is used. Is not particularly limited.

また、第２の電気めっき工程では、一定電流あるいは一定電圧の条件で電気めっきを行えばよく、貫通孔２２内側のめっきが終わって更にめっきを続けることにより図４に示すように金属部２４がマッシュルーム状に形成されるから、一定電流の条件で電気めっきを行った場合には、めっき電圧がめっき時間の経過とともに図５に示すように変化するので、めっき電圧の変化率が第１の規定値よりも大きくなった時点をめっき終了時点（充填完了時点）として通電を終了するようにすればめっきを過不足なく行うことができる。また、一定電圧の条件で電気めっきを行った場合には、めっき電流がめっき時間の経過とともに図６に示すように変化するので、めっき電流の変化率が第２の規定値よりも大きくなった時点をめっき終了時点（充填完了時点）として通電を終了するようにすればめっきを過不足なく行うことができる。ただし、めっき電圧やめっき電流の変化率によりめっき終了時点を判断する場合には、基板２０ａの上記一表面側の導体部２７へめっき電流の回り込みあると、めっき電圧やめっき電流の変化率が小さく、適宜のプログラムを搭載したコンピュータなどからなる制御装置によるめっき終了時点の判断が難しくなるので、導体部２７の裏面側にはめっきされないようにマスキングすることが好ましい。   Further, in the second electroplating step, electroplating may be performed under a constant current or constant voltage condition, and the plating inside the through hole 22 is finished and the plating is further continued, so that the metal portion 24 is formed as shown in FIG. Since it is formed in a mushroom shape, when electroplating is performed under the condition of a constant current, the plating voltage changes as shown in FIG. 5 as the plating time elapses. If the energization is terminated with the time when the value becomes larger than the value as the time when the plating is completed (the time when filling is completed), the plating can be performed without excess or deficiency. In addition, when electroplating was performed under the condition of a constant voltage, the plating current changed as shown in FIG. 6 with the lapse of the plating time, so the rate of change of the plating current was larger than the second specified value. If energization is terminated with the point in time as the end of plating (the point of completion of filling), plating can be performed without excess or deficiency. However, when judging the end point of plating from the rate of change of the plating voltage or plating current, if the plating current wraps around the conductor portion 27 on the one surface side of the substrate 20a, the rate of change of the plating voltage or plating current is small. Since it is difficult to determine the end point of plating by a control device including a computer equipped with an appropriate program, it is preferable to perform masking so that the back side of the conductor portion 27 is not plated.

以上説明した本実施形態の基板２０ａへのビアの形成方法によれば、貫通孔形成工程の後で基板２０ａの上記一表面側に各貫通孔２２が閉塞されないように金属薄膜２６を形成した後、基板２０ａの上記一表面側に各貫通孔２２および各貫通孔２２の周部の金属薄膜２６を露出させる複数の開口部６１ａを有するレジスト層６１を形成してから、基板２０ａの上記一表面側に各貫通孔２２を閉塞する複数の島状の導体部２７を電気めっきにより形成し、その後で基板２０ａの上記他表面側に対向配置した上記陽極と基板２０ａの上記一表面側において各貫通孔２２を閉塞している導体部２７からなる陰極との間に通電してそれぞれビア２４となる複数の金属部を各導体部２７における貫通孔２２側の露出表面から基板２０ａの厚み方向に沿って析出させ、その後、レジスト層６１および当該レジスト層６１下の金属薄膜２６を除去するので、基板２０ａの上記一表面側において各貫通孔２２を閉塞する複数の導体部２７が島状に形成されており、基板２０ａの上記一表面側の全体に連続した導体部が形成されている場合に比べて、めっき応力を低減でき、基板２０ａの反りを低減できる。   According to the method of forming a via on the substrate 20a of the present embodiment described above, after the metal thin film 26 is formed so that each through hole 22 is not blocked on the one surface side of the substrate 20a after the through hole forming step. The resist layer 61 having a plurality of openings 61a exposing the through holes 22 and the metal thin film 26 around the through holes 22 is formed on the one surface side of the substrate 20a, and then the one surface of the substrate 20a is formed. A plurality of island-shaped conductor portions 27 for closing each through-hole 22 on the side are formed by electroplating, and then each through-hole is formed on the one surface side of the substrate 20a and the anode disposed opposite to the other surface side of the substrate 20a. A plurality of metal portions each serving as a via 24 are energized between the cathode made of the conductor portion 27 closing the hole 22 and are exposed from the exposed surface of each conductor portion 27 on the through hole 22 side along the thickness direction of the substrate 20a. Then, since the resist layer 61 and the metal thin film 26 under the resist layer 61 are removed, a plurality of conductor portions 27 that close the through holes 22 are formed in an island shape on the one surface side of the substrate 20a. And compared with the case where the continuous conductor part is formed in the whole said one surface side of the board | substrate 20a, a plating stress can be reduced and the curvature of the board | substrate 20a can be reduced.

ここにおいて、一般的にウェハの一表面全面にめっき膜を形成した場合のウェハの反りｈ〔μｍ〕は、ウェハの厚さをＴ〔μｍ〕、ウェハのヤング率をＥ〔Ｐａ〕、ウェハのポアソン比をν、めっき膜厚をｔ〔μｍ〕、めっき径（ウェハの直径）をＤ〔μｍ〕、めっき応力をσ〔Ｐａ〕とすると、下記数１で表される。   Here, in general, when the plating film is formed on the entire surface of the wafer, the wafer warp h [μm] is the wafer thickness T [μm], the wafer Young's modulus E [Pa], When the Poisson's ratio is ν, the plating film thickness is t [μm], the plating diameter (wafer diameter) is D [μm], and the plating stress is σ [Pa], it is expressed by the following equation (1).

Figure 2009238957
Figure 2009238957

上記数１から分かるようにウェハの反りｈは、めっき応力σが同一であれば、めっき面積（≒πＤ２／４）に比例して大きくなるのに対して、本実施形態の基板２０ａへのビア２４の形成方法によれば、第１の電気めっき工程よりも前にレジスト層６１を形成することで基板２０ａの上記一表面に平行な面内において導体部２７が形成される領域の面積を小さくすることができ、基板２０ａの反りを小さくすることができる。また、本実施形態の基板２０ａへのビア２４の形成方法によれば、上述の第１の電気めっき工程で用いるめっき液にめっき促進剤７１およびめっき抑制剤７２を添加しているので、基板２０ａの上記一表面側の導体部２７の厚みを薄くすることができるので、基板２０ａの反りをより小さくすることができる。 Warp h of the wafer as can be seen from Equation 1, if the plating stress σ are the same, whereas increases in proportion to the plating area (≒ πD 2/4), to the substrate 20a of the present embodiment According to the method for forming the via 24, the area of the region in which the conductor portion 27 is formed in the plane parallel to the one surface of the substrate 20a is formed by forming the resist layer 61 before the first electroplating step. The warpage of the substrate 20a can be reduced. In addition, according to the method for forming the via 24 on the substrate 20a of the present embodiment, the plating accelerator 71 and the plating inhibitor 72 are added to the plating solution used in the first electroplating step described above. Since the thickness of the conductor portion 27 on the one surface side can be reduced, the warp of the substrate 20a can be further reduced.

しかして、ビア２４を有する基板２０ａを備えたデバイスの製造時に、ビア２４形成後の工程において、ロボットアームによる基板２０ａの搬送を安定して行うことができるとともに、加工精度の低下（特に、フォトリソグラフィ技術とエッチング技術を利用したパターニングや、研磨技術を利用した平坦化などの加工精度の低下）や、歩留まりの低下を防止することができ、デバイスの特性低下を防止することができる。   Thus, when manufacturing a device including the substrate 20a having the vias 24, the substrate 20a can be stably transported by the robot arm in the process after the vias 24 are formed, and the processing accuracy is lowered (particularly, photo processing). It is possible to prevent a reduction in processing accuracy such as patterning using a lithography technique and an etching technique and flattening using a polishing technique) and a reduction in yield, and a deterioration in device characteristics can be prevented.

ここにおいて、本実施形態の基板２０ａへのビア２４の形成方法を上述のベース基板２０の形成方法に適用し、中間層基板３０の形成方法に準用すれば、ベース基板２０および中間層基板３０の反りを低減できるので、上述の第１の接合工程および第２の接合工程の歩留まりを向上でき、発光装置の低コスト化を図れる。   Here, if the method for forming the via 24 in the substrate 20a of the present embodiment is applied to the method for forming the base substrate 20 described above and applied to the method for forming the intermediate layer substrate 30, the base substrate 20 and the intermediate layer substrate 30 can be formed. Since warpage can be reduced, the yield of the first bonding step and the second bonding step described above can be improved, and the cost of the light-emitting device can be reduced.

また、上述の基板２０ａへのビア２４の形成方法においては、基板２０ａとしてシリコン基板のような半導体基板を用いているが、貫通孔形成工程と金属薄膜形成工程との間に、基板２０ａの上記一表面および上記他表面および各貫通孔２２の内周面に絶縁膜２３を形成する絶縁膜形成工程を行うので、金属薄膜２６を形成する前に基板２０ａの上記一表面および上記他表面および各貫通孔２２の内周面に絶縁膜２３が形成されており、ビア２４と基板２０ａとが電気的に接続されるのを防止することができる。なお、本実施形態では、基板２０ａとして半導体基板を用いた例を説明したが、基板２０ａは、半導体基板に限らず、金属板や絶縁性基板（例えば、ガラス基板など）でもよく、絶縁性基板を用いる場合には、上述の絶縁膜形成工程は不要である。   Further, in the above-described method for forming the via 24 on the substrate 20a, a semiconductor substrate such as a silicon substrate is used as the substrate 20a. However, the above-described method of forming the via 20 between the through hole forming step and the metal thin film forming step. Since the insulating film forming step of forming the insulating film 23 on the one surface, the other surface, and the inner peripheral surface of each through hole 22 is performed, the one surface, the other surface, and each of the substrate 20a are formed before the metal thin film 26 is formed. An insulating film 23 is formed on the inner peripheral surface of the through hole 22, and it is possible to prevent the via 24 and the substrate 20 a from being electrically connected. In this embodiment, an example in which a semiconductor substrate is used as the substrate 20a has been described. However, the substrate 20a is not limited to a semiconductor substrate, and may be a metal plate or an insulating substrate (for example, a glass substrate). When using, the above-described insulating film forming step is not necessary.

また、本実施形態の基板２０ａへのビア２４の形成方法において、各導体部２７が基板２０ａの上記一表面側の導体パターン（図７では、導体パターンとして外部接続用電極２７ａ，２７ａ、放熱用パッド部２８を図示してある）を兼ねるようにし、レジスト層形成工程で、開口部６１ａの開口形状をこれら導体パターンに合わせて設定するようにすれば、上記不要部除去工程の後に残った各導体部２７を導体パターンとして利用することができる。なお、上記不要部除去工程では、レジスト層６１下の金属薄膜２６も除去しているが、必ずしもレジスト層６１下の金属薄膜２６の全部を除去する必要はなく、例えば、ビア２４のうち上述の貫通孔配線２４ａを構成するビア２４周辺の金属薄膜２６を除去し、ビア２４のうち上述のサーマルビア２４ｂを構成するビア２４周辺の金属薄膜２６を残すようにしてもよい。   Further, in the method of forming the via 24 on the substrate 20a of the present embodiment, each conductor portion 27 is a conductor pattern on the one surface side of the substrate 20a (in FIG. 7, the external connection electrodes 27a and 27a are used as the conductor pattern, and for heat dissipation. If the opening portion 61a is set in accordance with these conductor patterns in the resist layer forming step, each remaining after the unnecessary portion removing step is also provided. The conductor part 27 can be used as a conductor pattern. In the unnecessary portion removing step, the metal thin film 26 under the resist layer 61 is also removed. However, the entire metal thin film 26 under the resist layer 61 is not necessarily removed. The metal thin film 26 around the via 24 constituting the through-hole wiring 24 a may be removed, and the metal thin film 26 around the via 24 constituting the thermal via 24 b of the via 24 may be left.

また、上述の基板２０ａのビア２４の形成方法によれば、上述の金属薄膜２６を形成する金属薄膜形成工程において、金属薄膜２６をスパッタ法により形成しているので、金属薄膜２６を蒸着法やＣＶＤ法により形成する場合に比べて、貫通孔２２の内側への金属薄膜２３の堆積が起こりにくくなり、結果的に、ビア２４の埋め込み性が良くなる。   Further, according to the method for forming the via 24 of the substrate 20a, the metal thin film 26 is formed by the sputtering method in the metal thin film forming step of forming the metal thin film 26. Compared with the case of forming by the CVD method, the metal thin film 23 is less likely to be deposited inside the through hole 22, and as a result, the embedding property of the via 24 is improved.

ところで、上述の実施形態では、ビア２４を有するデバイスとして発光装置を例示したが、ビア２４を有するデバイスは、発光装置に限らず、物理量センサ、赤外線センサ、高周波デバイス、マイクロバルブ、音響センサ、化学センサ、半導体装置などでもよい。   By the way, in the above-mentioned embodiment, although the light-emitting device was illustrated as a device which has the via 24, the device which has the via 24 is not restricted to a light-emitting device, A physical quantity sensor, an infrared sensor, a high frequency device, a microvalve, an acoustic sensor, chemical A sensor, a semiconductor device, etc. may be sufficient.

実施形態における基板へのビアの形成方法を説明するための主要工程断面図である。It is main process sectional drawing for demonstrating the formation method of the via | veer to the board | substrate in embodiment. 同上の基板へのビアの形成方法の説明図である。It is explanatory drawing of the formation method of the via to a board | substrate same as the above. 同上の基板へのビアの形成方法の説明図である。It is explanatory drawing of the formation method of the via to a board | substrate same as the above. 同上の基板へのビアの形成方法の説明図である。It is explanatory drawing of the formation method of the via to a board | substrate same as the above. 同上の基板へのビアの形成方法の説明図である。It is explanatory drawing of the formation method of the via to a board | substrate same as the above. 同上の基板へのビアの形成方法の説明図である。It is explanatory drawing of the formation method of the via to a board | substrate same as the above. 同上の基板へのビアの形成方法の説明図である。It is explanatory drawing of the formation method of the via to a board | substrate same as the above. 同上における発光装置の概略断面図である。It is a schematic sectional drawing of the light-emitting device in the same as the above. 同上における発光装置の概略分解斜視図である。It is a general | schematic disassembled perspective view of the light-emitting device same as the above. 同上におけるベース基板を示し、（ａ）は概略平面図、（ｂ）は（ａ）のＡ−Ａ’概略断面図、（ｃ）は（ａ）のＢ−Ｂ’概略断面図である。The base board | substrate in the same as the above is shown, (a) is a schematic plan view, (b) is an A-A 'schematic sectional view of (a), and (c) is a B-B' schematic sectional view of (a). 従来例を示す基板へのビアの形成方法を説明するための主要工程断面図である。It is main process sectional drawing for demonstrating the formation method of the via | veer to the board | substrate which shows a prior art example. 他の従来例を示す基板へのビアの形成方法を説明するための主要工程断面図である。It is main process sectional drawing for demonstrating the formation method of the via to the board | substrate which shows another prior art example.

符号の説明Explanation of symbols

２０ａ 基板
２２ 貫通孔
２３ 絶縁膜
２４ ビア（金属部）
２６ 金属薄膜
２７ 導体部（導体パターン）
６１ レジスト層
６１ａ 開口部 20a Substrate 22 Through-hole 23 Insulating film 24 Via (metal part)
26 Metal thin film 27 Conductor (conductor pattern)
61 resist layer 61a opening

Claims (3)

基板へのビアの形成方法であって、基板に厚み方向に貫通する複数の貫通孔を形成する貫通孔形成工程と、貫通孔形成工程の後で基板の一表面側に各貫通孔が閉塞されないように金属薄膜を形成する金属薄膜形成工程と、金属薄膜形成工程の後で基板の前記一表面側に各貫通孔および各貫通孔の周部の金属薄膜を露出させる複数の開口部を有するレジスト層を形成するレジスト層形成工程と、レジスト層形成工程の後で基板の前記一表面側に各貫通孔を閉塞する複数の島状の導体部を電気めっきにより形成する第１の電気めっき工程と、第１の電気めっき工程の後で基板の他表面側に対向配置した陽極と基板の前記一表面側において各貫通孔を閉塞している導体部からなる陰極との間に通電してそれぞれビアとなる複数の金属部を各導体部における貫通孔側の露出表面から基板の厚み方向に沿って析出させる第２の電気めっき工程と、第２の電気めっき工程の後でレジスト層を除去する不要部除去工程とを備えることを特徴とする基板へのビアの形成方法。   A method of forming a via in a substrate, wherein a through hole forming step for forming a plurality of through holes penetrating in the thickness direction in the substrate and each through hole is not blocked on one surface side of the substrate after the through hole forming step A metal thin film forming step of forming a metal thin film, and a resist having a plurality of openings exposing the through holes and the metal thin film around the through holes on the one surface side of the substrate after the metal thin film forming step A resist layer forming step of forming a layer, and a first electroplating step of forming, by electroplating, a plurality of island-shaped conductor portions that close each through hole on the one surface side of the substrate after the resist layer forming step Via each of the vias between the anode disposed opposite to the other surface side of the substrate after the first electroplating step and the cathode formed of a conductor portion closing each through hole on the one surface side of the substrate. Multiple metal parts to each conductor part And a second electroplating step of depositing along the thickness direction of the substrate from the exposed surface on the through hole side, and an unnecessary portion removing step of removing the resist layer after the second electroplating step. A method of forming a via on a substrate. 前記基板が半導体基板であり、前記貫通孔形成工程と前記金属薄膜形成工程との間に、前記基板の前記一表面および前記他表面および前記各貫通孔の内周面に絶縁膜を形成する絶縁膜形成工程を備えることを特徴とする請求項１記載の基板へのビアの形成方法。   The substrate is a semiconductor substrate, and an insulating film is formed on the one surface and the other surface of the substrate and an inner peripheral surface of each through hole between the through hole forming step and the metal thin film forming step. The method for forming a via in a substrate according to claim 1, further comprising a film forming step. 前記各導体部が前記基板の前記一表面側の導体パターンを兼ねるものであり、前記レジスト層形成工程では、前記開口部の開口形状を前記導体パターンに合わせて設定してあることを特徴とする請求項１または請求項２記載の基板へのビアの形成方法。   Each of the conductor portions also serves as a conductor pattern on the one surface side of the substrate, and in the resist layer forming step, an opening shape of the opening portion is set in accordance with the conductor pattern. A method for forming a via in a substrate according to claim 1.
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JP2013008940A (en) * 2011-05-26 2013-01-10 Napura:Kk Substrate for electronic apparatus and electronic apparatus
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JP2013518433A (en) * 2010-01-29 2013-05-20 日本テキサス・インスツルメンツ株式会社 Protruding TSV for enhanced heat dissipation of IC devices
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JP2011258664A (en) * 2010-06-07 2011-12-22 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing wiring board
JP2011258663A (en) * 2010-06-07 2011-12-22 Shinko Electric Ind Co Ltd Wiring board and method for manufacturing wiring board
US20110297426A1 (en) * 2010-06-07 2011-12-08 Shinko Electric Industries Co., Ltd. Wiring substrate and manufacturing method thereof
US8664536B2 (en) * 2010-06-07 2014-03-04 Shinko Electric Industries Co., Ltd. Wiring substrate and manufacturing method thereof
US8895868B2 (en) 2010-06-07 2014-11-25 Shinko Electric Industries Co., Ltd. Wiring substrate
US9704793B2 (en) 2011-01-04 2017-07-11 Napra Co., Ltd. Substrate for electronic device and electronic device
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