JP2009176931A - Semiconductor device and electronic apparatus - Google Patents

Semiconductor device and electronic apparatus Download PDF

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Publication number
JP2009176931A
JP2009176931A JP2008013727A JP2008013727A JP2009176931A JP 2009176931 A JP2009176931 A JP 2009176931A JP 2008013727 A JP2008013727 A JP 2008013727A JP 2008013727 A JP2008013727 A JP 2008013727A JP 2009176931 A JP2009176931 A JP 2009176931A
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semiconductor chip
reinforcing plate
mounting terminal
semiconductor device
electronic component
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Yoshiaki Takeoka
嘉昭 竹岡
Akira Saito
彰 齊藤
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the mounting density of components on a substrate can be enhanced. <P>SOLUTION: The semiconductor device comprises a substrate 5, in which a mounting terminal 6A is provided on one surface 5a in the thickness direction, while a connection terminal 11 for external connection is provided on the other surface 5b; a semiconductor chip 7 which is mounted on one surface 5a of the substrate 5 by connecting a pad 12, which faces the mounting terminal 6A to the mounting terminal 6A, and a reinforcing plate 8A fixed to the surface of the semiconductor chip 7, which is on the opposite side of the substrate 5. The reinforcing plate 8A is accommodated on the semiconductor chip 7. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、半導体装置およびそれを用いた電子機器に関する。   The present invention relates to a semiconductor device and an electronic apparatus using the same.

各種電子機器のマザー基板上に実装される半導体装置は、図７に示すように、基板１と、この基板１上に実装された半導体チップ２と、基板１との間に半導体チップ２を挟む補強板３とを備えている（例えば、特許文献１参照）。半導体チップ２は、基板１の一方面（図７では上面）に設けられた実装端子１ａと対向するパッド２ａを有しており、このパッド２ａが実装端子１ａとバンプで接続されることにより基板１の一方面上に実装されている。また、基板１の他方面（図７では下面）には、外部接続用の接続端子１ｂが設けられていて、この接続端子１ｂがはんだなどでマザー基板の実装端子に接続されることにより、半導体装置がマザー基板上に実装される。   As shown in FIG. 7, the semiconductor device mounted on the mother substrate of various electronic devices has the semiconductor chip 2 sandwiched between the substrate 1, the semiconductor chip 2 mounted on the substrate 1, and the substrate 1. And a reinforcing plate 3 (see, for example, Patent Document 1). The semiconductor chip 2 has a pad 2a opposed to the mounting terminal 1a provided on one surface (upper surface in FIG. 7) of the substrate 1, and the pad 2a is connected to the mounting terminal 1a by a bump, thereby causing the substrate 1 is mounted on one side. Further, a connection terminal 1b for external connection is provided on the other surface (the lower surface in FIG. 7) of the substrate 1, and the connection terminal 1b is connected to the mounting terminal of the mother substrate by solder or the like, thereby providing a semiconductor. The device is mounted on the mother board.

補強板３は、マザー基板上に半導体装置を実装する際の熱的環境（例えばはんだ付け）により半導体チップ２が湾曲し、それによってパッド２ａと実装端子１ａとの電気的接続状態が不安定となるのを抑制するためのものであり、半導体チップ２の基板１と反対側の面に固定されている。また、補強板３の大きさは、半導体チップ２よりも十分に大きく設定されており、半導体チップ２から張り出す周縁部が外枠４などを介して基板１に固定されている。
特開２００１−１３５７４９号公報 In the reinforcing plate 3, the semiconductor chip 2 is bent by a thermal environment (for example, soldering) when the semiconductor device is mounted on the mother substrate, and thereby the electrical connection state between the pad 2a and the mounting terminal 1a is unstable. In other words, the semiconductor chip 2 is fixed to the surface opposite to the substrate 1. Further, the size of the reinforcing plate 3 is set to be sufficiently larger than that of the semiconductor chip 2, and the peripheral edge protruding from the semiconductor chip 2 is fixed to the substrate 1 via the outer frame 4 or the like.
JP 2001-135749 A

ところで、従来の半導体装置では、基板１に他の電子部品を実装する場合、補強板３が半導体チップ２から大きく張り出しているために、半導体チップ２の周囲のスペースを他の電子部品の実装のために使用することができず、その結果、基板１上における部品実装密度をあまり高くすることができなかった。   By the way, in the conventional semiconductor device, when other electronic components are mounted on the substrate 1, the reinforcing plate 3 protrudes greatly from the semiconductor chip 2, so that the space around the semiconductor chip 2 is used for mounting other electronic components. Therefore, the component mounting density on the substrate 1 could not be increased so much.

本発明は、このような事情に鑑み、基板上における部品実装密度を高めることが可能な半導体装置を提供することを目的とする。   In view of such circumstances, an object of the present invention is to provide a semiconductor device capable of increasing a component mounting density on a substrate.

前記目的を達成するために、本発明は、厚み方向の一方面に実装端子が設けられ、他方面に外部接続用の接続端子が設けられた基板と、前記実装端子に対向するパッドが前記実装端子に接続されることにより前記基板の一方面上に実装された半導体チップと、前記半導体チップの前記基板と反対側の面に固定された補強板と、を備え、前記補強板は、前記半導体チップ上に納まっている、半導体装置を提供する。   In order to achieve the above object, the present invention provides a substrate in which a mounting terminal is provided on one surface in the thickness direction and a connection terminal for external connection is provided on the other surface, and a pad facing the mounting terminal is mounted on the mounting surface. A semiconductor chip mounted on one surface of the substrate by being connected to a terminal; and a reinforcing plate fixed to a surface of the semiconductor chip opposite to the substrate, the reinforcing plate comprising the semiconductor Provided is a semiconductor device housed on a chip.

ここで、「補強板が半導体チップ上に納まっている」とは、補強板が完全に半導体チップ上に納まっていることだけでなく、補強板が実質的に半導体チップ上に納まっていることを含む概念であり、補強板が半導体チップから僅かに（例えば、１００μｍ程度）張り出していてもよい。   Here, “the reinforcing plate is accommodated on the semiconductor chip” means not only that the reinforcing plate is completely accommodated on the semiconductor chip but also that the reinforcing plate is substantially accommodated on the semiconductor chip. The reinforcing plate may slightly protrude (for example, about 100 μm) from the semiconductor chip.

また、本発明は、別の側面から、厚み方向の一方面に実装端子が設けられ、他方面に外部接続用の接続端子が設けられた基板と、前記実装端子に対向するパッドが前記実装端子に接続されることにより前記基板の一方面上に実装された半導体チップと、前記半導体チップの前記基板と反対側の面に固定された補強板と、前記補強板を挟んで前記半導体チップと反対側に配置された電子部品と、を備え、前記実装端子は、前記半導体チップのパッドと電気的に接続される第１実装端子と、この第１実装端子で構成される端子群の外側に配置された第２実装端子とを含み、前記電子部品の電極は、前記第２実装端子と電気的に接続されている、半導体装置を提供する。   Further, according to another aspect of the present invention, the mounting terminal is provided on one surface in the thickness direction and the connection terminal for external connection is provided on the other surface, and the pad facing the mounting terminal is the mounting terminal. A semiconductor chip mounted on one surface of the substrate by being connected to the substrate, a reinforcing plate fixed to the surface of the semiconductor chip opposite to the substrate, and opposite to the semiconductor chip across the reinforcing plate An electronic component disposed on the side, wherein the mounting terminal is disposed outside a first mounting terminal electrically connected to a pad of the semiconductor chip and a terminal group constituted by the first mounting terminal. And a second mounting terminal, wherein the electrode of the electronic component is electrically connected to the second mounting terminal.

さらに、本発明は、これらの半導体装置のどちらか一方と、この半導体装置が実装されたマザー基板と、を備える、電子機器を提供する。   Furthermore, the present invention provides an electronic apparatus including any one of these semiconductor devices and a mother board on which the semiconductor device is mounted.

上記の第１の構成によれば、補強板が半導体チップ上に納まっているので、半導体チップの周囲のスペースを利用して基板に他の電子部品を実装することができる。また、上記の第２の構成によれば、基板上に半導体チップと電子部品とが重なり合うように配置されているので、基板上におけるそれらの占有面積を小さくすることができる。   According to said 1st structure, since the reinforcement board is stored on the semiconductor chip, another electronic component can be mounted in a board | substrate using the space around a semiconductor chip. Moreover, according to said 2nd structure, since it arrange | positions so that a semiconductor chip and an electronic component may overlap on a board | substrate, those occupation areas on a board | substrate can be made small.

従って、本発明によれば、どちらの構成であっても、基板上における部品実装密度を高めることが可能である。   Therefore, according to the present invention, it is possible to increase the component mounting density on the board in any configuration.

以下、本発明の一実施形態について、図面を用いて説明する。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

図１に示すように、本発明の一実施形態に係る半導体装置は、基板５と、基板５上に実装された第１の半導体チップ７と、第１の半導体チップ７を補強する補強板８Ａと、補強板８Ａを挟んで第１の半導体チップ７と反対側に配置された第２の半導体チップ（本発明の電子部品の一例）９とを備えている。なお、本明細書では、説明の便宜のために、基板１の厚み方向のうち図１の上側を上方、下側を下方という。   As shown in FIG. 1, a semiconductor device according to an embodiment of the present invention includes a substrate 5, a first semiconductor chip 7 mounted on the substrate 5, and a reinforcing plate 8 </ b> A that reinforces the first semiconductor chip 7. And a second semiconductor chip (an example of an electronic component of the present invention) 9 disposed on the opposite side of the first semiconductor chip 7 across the reinforcing plate 8A. In the present specification, for convenience of explanation, in the thickness direction of the substrate 1, the upper side in FIG.

基板５は、平面視で矩形状の形状を有している（図３参照）。基板５の上面（厚み方向の一方面）５ａには、第１の半導体チップ７用の第１端子群を構成する複数の第１実装端子６Ａと、第２の半導体チップ９用の第２端子群を構成する複数の第２実装端子６Ｂとが設けられている。第１実装端子６Ａは、枠状に配置されており、第２実装端子６Ｂは、第１端子群を所定間隔を隔てて取り囲むように、第１端子群の周囲に、第１実装端子６Ａよりも一回り大きな枠状に配置されている。   The substrate 5 has a rectangular shape in plan view (see FIG. 3). On the upper surface (one surface in the thickness direction) 5 a of the substrate 5, a plurality of first mounting terminals 6 A constituting a first terminal group for the first semiconductor chip 7 and a second terminal for the second semiconductor chip 9. A plurality of second mounting terminals 6B constituting the group are provided. The first mounting terminals 6A are arranged in a frame shape, and the second mounting terminals 6B are arranged around the first terminal group from the first mounting terminals 6A so as to surround the first terminal group at a predetermined interval. Is also arranged in a larger frame shape.

また、基板１の下面（厚み方向の他方面）５ｂには、外部接続用の複数の接続端子１１が適所に設けられている。接続端子１１のそれぞれには、半導体装置を電子機器のマザー基板（図示せず）に実装するためのバンプ１０が設けられており、接続端子１１がバンプ１０によってマザー基板の実装端子に接続されることにより、半導体装置がマザー基板上に実装される。   A plurality of connection terminals 11 for external connection are provided at appropriate positions on the lower surface (the other surface in the thickness direction) 5b of the substrate 1. Each of the connection terminals 11 is provided with bumps 10 for mounting the semiconductor device on a mother board (not shown) of the electronic device, and the connection terminals 11 are connected to the mounting terminals of the mother board by the bumps 10. Thus, the semiconductor device is mounted on the mother substrate.

第１の半導体チップ７は、平面視で矩形状の形状を有している（図３参照）。この第１の半導体チップ７は、下面７ｂに、各々が第１実装端子６Ａのそれぞれと対向する複数のパッド（電極）１２を有している。そして、第１の半導体チップ７は、それぞれのパッド１２が対応する第１実装端子６Ａとバンプ１３で接続されることにより、パッド１２と第１実装端子６Ａとがバンプ１３を介して電気的に接続された状態で基板５の上面５ａ上に実装されている。なお、第１の半導体チップ７の下面７ｂは、パッド１２を除く部分を表面保護層２０で覆われている。また、第１の半導体チップ７と基板５との間の隙間は、補強用の樹脂１４で埋められており、この樹脂１４によっても基板５への第１の半導体チップ７の固定が図られている。   The first semiconductor chip 7 has a rectangular shape in plan view (see FIG. 3). The first semiconductor chip 7 has a plurality of pads (electrodes) 12 on the lower surface 7b, each facing the first mounting terminal 6A. In the first semiconductor chip 7, each pad 12 is connected to the corresponding first mounting terminal 6 </ b> A and the bump 13, so that the pad 12 and the first mounting terminal 6 </ b> A are electrically connected via the bump 13. It is mounted on the upper surface 5a of the substrate 5 in a connected state. The lower surface 7 b of the first semiconductor chip 7 is covered with the surface protective layer 20 except for the pads 12. The gap between the first semiconductor chip 7 and the substrate 5 is filled with a reinforcing resin 14, and the first semiconductor chip 7 is fixed to the substrate 5 by this resin 14. Yes.

補強板８Ａは、本実施形態では平面視で第１の半導体チップ７と同一の矩形状の形状を有している（図３参照）。そして、補強板８Ａは、第１の半導体チップ７の上面７ａに接着剤１５によって固定されることにより、第１の半導体チップ７上に納まっている。なお、本発明の補強板は平面視で第１の半導体チップ７と同一の形状を有している必要はなく、補強板の大きさが第１の半導体チップ７の大きさと略同じであるかそれよりも小さければよい。   In this embodiment, the reinforcing plate 8A has the same rectangular shape as that of the first semiconductor chip 7 in plan view (see FIG. 3). The reinforcing plate 8 </ b> A is housed on the first semiconductor chip 7 by being fixed to the upper surface 7 a of the first semiconductor chip 7 with the adhesive 15. The reinforcing plate of the present invention does not need to have the same shape as the first semiconductor chip 7 in plan view, and is the size of the reinforcing plate substantially the same as the size of the first semiconductor chip 7? Smaller than that.

第２の半導体チップ９は、平面視で第１の半導体チップ７よりも一回り大きな矩形状の形状を有している。この第２の半導体チップ９は、周縁部が全周に亘って補強板８Ａから張り出す状態で配置されている。   The second semiconductor chip 9 has a rectangular shape that is slightly larger than the first semiconductor chip 7 in plan view. The second semiconductor chip 9 is arranged in a state in which the peripheral edge protrudes from the reinforcing plate 8A over the entire circumference.

より詳しくは、第２の半導体チップ９は、補強板８Ａから張り出す周縁部の下面９１に、各々が第２実装端子６Ｂのそれぞれと対向する複数のパッド（電極）１８を有している。一方、第２実装端子６Ｂのそれぞれには、当該第２実装端子６Ｂから対応するパッド１８に向って延びる、すなわち第１の半導体チップ７および補強板８Ａの側方でこれらの厚み方向（上下方向）に延びる柱状バンプ１６が立設されている。そして、第２の半導体チップ９は、それぞれのパッド１８が対応する柱状バンプ１６とバンプ１７で接続されることにより、パッド１８と第２実装端子６Ｂとが柱状バンプ１６およびバンプ１７を介して電気的に接続された状態で基板５の上面５ａ上に実装されている。なお、第２の半導体チップ９の下面は、パッド１８を除く部分を表面保護層２１で覆われている。また、第２の半導体チップ９と補強板８Ａとの間には接着剤１９が介在しており、この接着剤１９によって第２の半導体チップ９が補強板８Ａの上面に固着されている。   More specifically, the second semiconductor chip 9 has a plurality of pads (electrodes) 18 each facing the second mounting terminal 6B on the lower surface 91 of the peripheral edge protruding from the reinforcing plate 8A. On the other hand, each of the second mounting terminals 6B extends from the second mounting terminal 6B toward the corresponding pad 18, that is, in the thickness direction (vertical direction) on the side of the first semiconductor chip 7 and the reinforcing plate 8A. The columnar bumps 16 extending in the vertical direction are erected. In the second semiconductor chip 9, the pads 18 and the second mounting terminals 6 </ b> B are electrically connected via the columnar bumps 16 and the bumps 17 by connecting the respective pads 18 with the corresponding columnar bumps 16 and bumps 17. It is mounted on the upper surface 5a of the substrate 5 in a connected state. The lower surface of the second semiconductor chip 9 is covered with a surface protective layer 21 except for the pads 18. An adhesive 19 is interposed between the second semiconductor chip 9 and the reinforcing plate 8A, and the second semiconductor chip 9 is fixed to the upper surface of the reinforcing plate 8A by the adhesive 19.

このように、本実施形態の半導体装置では、補強板８Ａが第１の半導体チップ７上に納まっているので、基板５上の第１の半導体チップ７の周囲には、上方に開放されたスペースが存在している。そして、本実施形態では、このスペースを利用して基板５と第１の半導体チップ７の上に配置した第２の半導体チップ９とを電気的に接続するようにしている。すなわち、本実施形態では、基板５の第２実装端子６Ｂと第２の半導体チップ９のパッド１８との導通を図る柱状バンプ１６を第１の半導体チップ９の近傍に配置することができ、これにより、基板５上における部品実装密度が高くなっている。   Thus, in the semiconductor device of the present embodiment, the reinforcing plate 8A is accommodated on the first semiconductor chip 7, so that the space opened upward is formed around the first semiconductor chip 7 on the substrate 5. Is present. In this embodiment, the space 5 is used to electrically connect the substrate 5 and the second semiconductor chip 9 disposed on the first semiconductor chip 7. That is, in the present embodiment, the columnar bumps 16 for conducting the second mounting terminals 6B of the substrate 5 and the pads 18 of the second semiconductor chip 9 can be arranged in the vicinity of the first semiconductor chip 9, and this Thus, the component mounting density on the substrate 5 is increased.

ここで、基板５上への第１の半導体チップ７の実装について説明する。この実装の前に、第１の半導体チップ７のパッド１２に例えば金またははんだなどでバンプ１３を形成する。また、第１の半導体チップ７の上面７ａには、補強板８Ａをそれらの輪郭を合致させた状態で接着剤１５で接着して固定する。   Here, mounting of the first semiconductor chip 7 on the substrate 5 will be described. Prior to this mounting, bumps 13 are formed on the pads 12 of the first semiconductor chip 7 with, for example, gold or solder. Further, the reinforcing plate 8A is bonded and fixed to the upper surface 7a of the first semiconductor chip 7 with an adhesive 15 in a state in which the contours thereof are matched.

まず、基板５の上面５ａ上に、樹脂１４を例えば第１実装端子６Ａで囲まれる領域を満たすように塗布する（盛る）。次に、基板５上に第１の半導体チップ７を第１実装端子６Ａの位置とパッド１２の位置とが一致するように配置する。その後、補強板８Ａの上から熱と圧力をかけることにより、樹脂１４を第１の半導体チップ７で押し広げながら、基板５上に第１の半導体チップ７を実装する。勿論、このときの第１の半導体チップ７の押し下げにより、そのパッド１２はバンプ１３を介して基板５上の第１実装端子６Ａに当接し、これにより両者は電気的に接続される。   First, on the upper surface 5a of the substrate 5, the resin 14 is applied (filled) so as to fill the region surrounded by the first mounting terminals 6A, for example. Next, the first semiconductor chip 7 is arranged on the substrate 5 so that the position of the first mounting terminal 6A and the position of the pad 12 coincide. Thereafter, by applying heat and pressure from above the reinforcing plate 8A, the first semiconductor chip 7 is mounted on the substrate 5 while the resin 14 is spread by the first semiconductor chip 7. Of course, when the first semiconductor chip 7 is pushed down at this time, the pad 12 comes into contact with the first mounting terminal 6A on the substrate 5 through the bumps 13, and thereby both are electrically connected.

このような熱と圧力をかけての補強板８Ａの押し下げのためにも、補強板８ＡはＡｌ、Ｃｕ、Ｎｉなどの熱伝導性の良好な金属で構成されていることが好ましい。また、この補強板８Ａと第１の半導体チップ７とを接着する接着剤１５も熱伝導率の高い熱伝導物質（例えばセラミックフィラや金属粒）を含んだものとすることが好ましい。   In order to push down the reinforcing plate 8A by applying such heat and pressure, the reinforcing plate 8A is preferably made of a metal having good thermal conductivity such as Al, Cu, Ni. Moreover, it is preferable that the adhesive 15 for bonding the reinforcing plate 8A and the first semiconductor chip 7 also includes a heat conductive material (for example, ceramic filler or metal particles) having high heat conductivity.

そして補強板８Ａの押し下げにより、樹脂１４は押し広げられ、最終的には図３のごとく一部が第２実装端子６Ｂ上にかかるまで広がる場合もある。   Then, the resin 14 is expanded by being pushed down by the reinforcing plate 8A, and finally spreads until a part of the resin 14 is placed on the second mounting terminal 6B as shown in FIG.

図２は、補強板８Ａが固定されていない第１の半導体チップ７の上から熱と圧力をかけて当該第１の半導体チップ７を基板５側に押し下げて基板５上に実装し、その後補強板８Ａを第１の半導体チップ７の上面７ａに接着剤１５で接着して固定する例を示している。   In FIG. 2, heat and pressure are applied from above the first semiconductor chip 7 to which the reinforcing plate 8A is not fixed, and the first semiconductor chip 7 is pushed down to the substrate 5 side to be mounted on the substrate 5 and then reinforced. An example is shown in which the plate 8A is bonded and fixed to the upper surface 7a of the first semiconductor chip 7 with an adhesive 15.

図１の場合も、図２の場合も、図３のごとく樹脂１４は押し広げられ、最終的には図３のごとく一部が第２実装端子６Ｂ上にかかるまで広がる場合があるが、第２実装端子６Ｂの一部分だけを覆う状態なので、この第２実装端子６Ｂへの柱状バンプ１６の電気的な接続が不良となることは極めて少ない。   In both the case of FIG. 1 and FIG. 2, the resin 14 is pushed and spread as shown in FIG. 3 and eventually spread until a part of the resin 14 is placed on the second mounting terminal 6B as shown in FIG. Since only a part of the two mounting terminals 6B is covered, the electrical connection of the columnar bumps 16 to the second mounting terminals 6B is very rare.

ただし、使用する樹脂１４の種類などにより第２実装端子６Ｂ上に大きく広がるおそれがあるときには、図４および図６に示すように、補強板を、平面視で第１の半導体チップ７の輪郭から各辺の中央部分を内側に控えさせた形状、換言すれば第１の半導体チップ７の頂点と対応する４つの頂点の間に内向きに窪む４つの逃がし部８１を有した形状とすることが好ましい。   However, when there is a possibility that the second mounting terminal 6B may be greatly spread depending on the type of the resin 14 to be used, the reinforcing plate is removed from the outline of the first semiconductor chip 7 in plan view as shown in FIGS. A shape in which the central portion of each side is kept inward, in other words, a shape having four relief portions 81 recessed inwardly between four vertices corresponding to the vertices of the first semiconductor chip 7. Is preferred.

図４に示す例では、第１の半導体チップ７が平面視で正方形状をなしており、補強板８Ｂは、平面視で第１の半導体チップ７の対角を結ぶ略十字状をなしている。すなわち、補強板８Ｂの各逃がし部８１は、平面視で第１の半導体チップ７の頂点と対応する４つの頂点を結ぶ線の中央部分が直角二等辺三角形状に窪む形状となっている。   In the example shown in FIG. 4, the first semiconductor chip 7 has a square shape in plan view, and the reinforcing plate 8B has a substantially cross shape that connects the diagonals of the first semiconductor chip 7 in plan view. . That is, each relief portion 81 of the reinforcing plate 8B has a shape in which a central portion of a line connecting four vertices corresponding to the vertices of the first semiconductor chip 7 is recessed in a right isosceles triangle shape in plan view.

このように正方形状の第１の半導体チップ７の対角を結ぶ略十字状に形成された補強板８Ｂを用いると、補強板８Ｂの上からの加熱時に、熱が補強板８Ｂを通じて第１の半導体チップ７に対角線に沿って重点的に伝達されるようになる。その結果、図３では広がりにくかった第１の半導体チップ７の対角線方向にも樹脂１４が広がりやすくなり、それにより樹脂１４は、図５のごとく第１の半導体チップ７の外周に均一的に広がるようになる。これにより、図３とは異なり、樹脂１４が第２実装端子６Ｂ上に大きく広がることが効果的に抑制され、第２実装端子６Ｂと柱状バンプ１６の電気的接続不良を防ぐことができる。   When the reinforcing plate 8B formed in a substantially cross shape connecting the diagonals of the square first semiconductor chips 7 is used, heat is applied through the reinforcing plate 8B during the heating from above the reinforcing plate 8B. It is transmitted to the semiconductor chip 7 along the diagonal line. As a result, the resin 14 is likely to spread in the diagonal direction of the first semiconductor chip 7 which is difficult to spread in FIG. 3, so that the resin 14 spreads uniformly on the outer periphery of the first semiconductor chip 7 as shown in FIG. It becomes like this. Thereby, unlike FIG. 3, it is possible to effectively suppress the resin 14 from spreading greatly on the second mounting terminal 6B, and to prevent poor electrical connection between the second mounting terminal 6B and the columnar bump 16.

図６に示す例では、第１の半導体チップ７が平面視で正方形状をなしており、補強板８Ｃは、第１の半導体チップ７の対角を結ぶ略十字形の星状をなしている。すなわち、補強板８Ｃの各逃がし部８１は、平面視で第１の半導体チップ７の頂点と対応する４つの頂点から緩やかな角度で直線状に窪む形状となっている。そして、この場合も、図５と同じように樹脂１４が第２実装端子６Ｂ上に大きく広がることが効果的に抑制され、第２実装端子６Ｂと柱状バンプ１６の電気的接続不良を防ぐことができる。   In the example shown in FIG. 6, the first semiconductor chip 7 has a square shape in plan view, and the reinforcing plate 8 </ b> C has a substantially cross-shaped star shape that connects the diagonals of the first semiconductor chip 7. . That is, each relief portion 81 of the reinforcing plate 8C has a shape that is linearly depressed at a gentle angle from four vertices corresponding to the vertices of the first semiconductor chip 7 in plan view. Also in this case, as in FIG. 5, the resin 14 is effectively suppressed from spreading widely on the second mounting terminal 6 </ b> B, and poor electrical connection between the second mounting terminal 6 </ b> B and the columnar bump 16 can be prevented. it can.

なお、図４および図６に示す例では、補強板８Ｂ，８Ｃの各逃がし部８１が平面視で２本の直線を呈するようになっているが、補強板８Ｂ，８Ｃの各逃がし部８１は、例えば平面視で曲線を呈するような形状になっていてもよい。また、第１の半導体チップ７の形状は、平面視で正方形状である必要はなく、長方形状であってもよい。   In the example shown in FIGS. 4 and 6, the relief portions 81 of the reinforcing plates 8B and 8C are configured to form two straight lines in a plan view, but the relief portions 81 of the reinforcing plates 8B and 8C are For example, it may have a shape that exhibits a curve in plan view. Further, the shape of the first semiconductor chip 7 does not have to be a square shape in plan view, and may be a rectangular shape.

第２の半導体チップ９の基板５への実装については、まず基板５の第２実装端子６Ｂ上に例えばはんだなどで柱状バンプ１６を形成する。ついで、第１の半導体チップ７と同様に、パッド１８に例えば金またははんだなどでバンプ１７が形成された第２の半導体チップ９を、接着剤１９を塗布した補強板８Ａの上面上に重ね、第２の半導体チップ９の上から熱と圧力をかけてパッド１８と柱状バンプ１６とをバンプ１７によって接続する。   For mounting the second semiconductor chip 9 on the substrate 5, first, columnar bumps 16 are formed on the second mounting terminals 6 </ b> B of the substrate 5 with, for example, solder. Next, like the first semiconductor chip 7, the second semiconductor chip 9 in which the bumps 17 are formed on the pads 18 with, for example, gold or solder, is overlaid on the upper surface of the reinforcing plate 8 </ b> A coated with the adhesive 19. The pad 18 and the columnar bump 16 are connected by the bump 17 by applying heat and pressure from above the second semiconductor chip 9.

なお、前記実施形態では、第２の半導体チップ９を第１の半導体チップ７の上に配置した形態を示したが、本発明は、第２の半導体チップ９を第１の半導体チップ７の横に配置する場合にも適用可能である。この場合でも、補強板８Ａ（または８Ｂ，８Ｃ）が第１の半導体チップ７上に納まっているので、第２の半導体チップ９を第１の半導体チップ７の近傍に配置することができ、部品実装密度を高めることができる。   In the above-described embodiment, the second semiconductor chip 9 is disposed on the first semiconductor chip 7. However, in the present invention, the second semiconductor chip 9 is placed beside the first semiconductor chip 7. The present invention can also be applied to the case of arranging in the above. Even in this case, since the reinforcing plate 8A (or 8B, 8C) is housed on the first semiconductor chip 7, the second semiconductor chip 9 can be disposed in the vicinity of the first semiconductor chip 7, and the component Mounting density can be increased.

また、基板５には第１の半導体チップ７のみを実装するようにしてもよいが、前記実施形態のように第１の半導体チップ７の上に第２の半導体チップ９を配置すれば、基板５上におけるそれらの占有面積を小さくすることができ、基板５上における部品実装密度を高めることができる。この場合、補強板８Ａの大きさを第１の半導体チップ７よりも十分に大きくして、第１の半導体チップ７を取り囲む外枠などで補強板８Ａの周縁部を基板５に固定し、その外側で第２の半導体チップ９と基板５とを電気的に接続することも可能である。   Further, only the first semiconductor chip 7 may be mounted on the substrate 5, but if the second semiconductor chip 9 is arranged on the first semiconductor chip 7 as in the above-described embodiment, the substrate Their occupied area on the board 5 can be reduced, and the component mounting density on the board 5 can be increased. In this case, the size of the reinforcing plate 8A is made sufficiently larger than that of the first semiconductor chip 7, and the peripheral portion of the reinforcing plate 8A is fixed to the substrate 5 with an outer frame or the like surrounding the first semiconductor chip 7. It is also possible to electrically connect the second semiconductor chip 9 and the substrate 5 on the outside.

さらに、第２の半導体チップ９に代えて、例えば抵抗、コンデンサー、ダイオードなどの受動部品を実装したプリント配線板などの他の電子部品を基板５上に実装してもよい。   Furthermore, instead of the second semiconductor chip 9, other electronic components such as a printed wiring board on which passive components such as resistors, capacitors, and diodes are mounted may be mounted on the substrate 5.

さらに、第１の半導体チップ７の上に配置する電子部品（第２の半導体チップ９または他の電子部品）は、第１の半導体チップ７よりも大きなものである必要はない。例えば、第１の半導体チップ７よりも小さく、下面にパッドを有する電子部品を第１の半導体チップ７の上に配置する場合は、電子部品を第１の半導体チップ７に対してずらして配置することによってパッドを第２実装端子６Ｂに対向させるようにしてもよい。また、第１の半導体チップ７の上に配置する電子部品の電極は、下面に設けられたパッドである必要はなく、例えば、上面または側面に設けられたパッドであってもよいし、リード電極であってもよい。そして、その電子部品の電極と第２実装端子６Ｂとをワイヤボンディングで電気的に接続してもよい。   Furthermore, the electronic component (second semiconductor chip 9 or other electronic component) disposed on the first semiconductor chip 7 does not need to be larger than the first semiconductor chip 7. For example, when an electronic component that is smaller than the first semiconductor chip 7 and has a pad on the lower surface is arranged on the first semiconductor chip 7, the electronic component is arranged so as to be shifted with respect to the first semiconductor chip 7. Thus, the pad may be opposed to the second mounting terminal 6B. Further, the electrode of the electronic component disposed on the first semiconductor chip 7 does not need to be a pad provided on the lower surface, and may be a pad provided on the upper surface or the side surface, for example, It may be. Then, the electrode of the electronic component and the second mounting terminal 6B may be electrically connected by wire bonding.

また、第２実装端子６Ｂは、第１端子群の周囲に配置されている必要はなく、第１端子群の外側に配置されていればよく、例えば、第１端子群を一方向から挟み込むように配置されていてもよいし、第１端子群の横の一箇所にまとめて配置されていてもよい。   Further, the second mounting terminal 6B does not have to be disposed around the first terminal group, and may be disposed outside the first terminal group. For example, the first terminal group is sandwiched from one direction. It may be arranged in one place, or may be arranged together in one place beside the first terminal group.

以上のごとく本発明は、基板上における部品実装密度を高めることが可能な半導体装置を提供するものであるので、この半導体装置を搭載する各種電子機器の小型化に貢献できる。   As described above, the present invention provides a semiconductor device capable of increasing the component mounting density on the substrate, and thus can contribute to miniaturization of various electronic devices on which the semiconductor device is mounted.

本発明の一実施形態に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on one Embodiment of this invention. 図１の半導体装置の製造方法を説明する説明図である。It is explanatory drawing explaining the manufacturing method of the semiconductor device of FIG. 補強板が固定された第１の半導体チップを実装した基板を示す平面図である。It is a top view which shows the board | substrate which mounted the 1st semiconductor chip to which the reinforcement board was fixed. 変形例の補強板が固定された第１の半導体チップを示す平面図である。It is a top view which shows the 1st semiconductor chip to which the reinforcement board of the modification was fixed. 図４の第１の半導体チップを実装した基板を示す平面図である。FIG. 5 is a plan view showing a substrate on which the first semiconductor chip of FIG. 4 is mounted. 他の変形例の補強板が固定された第１の半導体チップを示す平面図である。It is a top view which shows the 1st semiconductor chip to which the reinforcement board of the other modification was fixed. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device.

符号の説明Explanation of symbols

５ 基板
５ａ 上面（一方面）
５ｂ 下面（他方面）
６Ａ 第１実装端子
６Ｂ 第２実装端子
７ 第１の半導体チップ
８Ａ〜８Ｃ 補強板
９ 第２の半導体チップ（本発明の電子部品の一例）
１０，１３，１７ バンプ
１１ 接続端子
１２，１８ パッド
１４ 樹脂
１５，１９ 接着剤
１６ 柱状バンプ
２０，２１ 表面保護層 5 Substrate 5a Upper surface (one surface)
5b Lower surface (the other surface)
6A 1st mounting terminal 6B 2nd mounting terminal 7 1st semiconductor chip 8A-8C Reinforcement board 9 2nd semiconductor chip (an example of electronic component of this invention)
10, 13, 17 Bump 11 Connection terminal 12, 18 Pad 14 Resin 15, 19 Adhesive 16 Columnar bump 20, 21 Surface protective layer

Claims (13)

厚み方向の一方面に実装端子が設けられ、他方面に外部接続用の接続端子が設けられた基板と、前記実装端子に対向するパッドが前記実装端子に接続されることにより前記基板の一方面上に実装された半導体チップと、前記半導体チップの前記基板と反対側の面に固定された補強板と、を備え、
前記補強板は、前記半導体チップ上に納まっている、半導体装置。 A board having a mounting terminal provided on one surface in the thickness direction and a connection terminal for external connection provided on the other surface, and a pad facing the mounting terminal connected to the mounting terminal, thereby providing one surface of the board. A semiconductor chip mounted thereon, and a reinforcing plate fixed to a surface of the semiconductor chip opposite to the substrate,
The reinforcing plate is a semiconductor device housed on the semiconductor chip. 前記補強板を挟んで前記半導体チップと反対側に配置された電子部品をさらに備え、
前記実装端子は、前記半導体チップのパッドと電気的に接続される第１実装端子と、この第１実装端子で構成される端子群の外側に配置された第２実装端子とを含み、
前記電子部品の電極は、前記第２実装端子と電気的に接続されている、請求項１に記載の半導体装置。 The electronic component further disposed on the opposite side of the semiconductor chip across the reinforcing plate,
The mounting terminal includes a first mounting terminal electrically connected to the pad of the semiconductor chip, and a second mounting terminal disposed outside a terminal group configured by the first mounting terminal,
The semiconductor device according to claim 1, wherein the electrode of the electronic component is electrically connected to the second mounting terminal. 厚み方向の一方面に実装端子が設けられ、他方面に外部接続用の接続端子が設けられた基板と、前記実装端子に対向するパッドが前記実装端子に接続されることにより前記基板の一方面上に実装された半導体チップと、前記半導体チップの前記基板と反対側の面に固定された補強板と、前記補強板を挟んで前記半導体チップと反対側に配置された電子部品と、を備え、
前記実装端子は、前記半導体チップのパッドと電気的に接続される第１実装端子と、この第１実装端子で構成される端子群の外側に配置された第２実装端子とを含み、
前記電子部品の電極は、前記第２実装端子と電気的に接続されている、半導体装置。 A board having a mounting terminal provided on one surface in the thickness direction and a connection terminal for external connection provided on the other surface, and a pad facing the mounting terminal connected to the mounting terminal, thereby providing one surface of the board. A semiconductor chip mounted thereon, a reinforcing plate fixed to a surface of the semiconductor chip opposite to the substrate, and an electronic component disposed on the opposite side of the semiconductor chip across the reinforcing plate. ,
The mounting terminal includes a first mounting terminal electrically connected to the pad of the semiconductor chip, and a second mounting terminal disposed outside a terminal group constituted by the first mounting terminal,
The electrode of the said electronic component is a semiconductor device electrically connected with the said 2nd mounting terminal. 前記補強板は、前記半導体チップ上に納まっている、請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein the reinforcing plate is housed on the semiconductor chip. 前記第２実装端子は、前記端子群を取り囲むように当該端子群の周囲に配置されており、
前記電子部品は前記半導体チップよりも大きなものであり、前記電子部品の周縁部は全周に亘って前記補強板から張り出しており、前記電子部品の電極は、当該電子部品の周縁部に設けられた、前記第２実装端子と対向するパッドで構成されており、
前記第２実装端子と前記電子部品のパッドとは、前記半導体チップおよび前記補強板の側方でこれらの厚み方向に延びる柱状バンプを介して電気的に接続されている、請求項２または４に記載の半導体装置。 The second mounting terminal is arranged around the terminal group so as to surround the terminal group,
The electronic component is larger than the semiconductor chip, and a peripheral portion of the electronic component protrudes from the reinforcing plate over the entire periphery, and an electrode of the electronic component is provided on the peripheral portion of the electronic component. Further, it is composed of a pad facing the second mounting terminal,
The said 2nd mounting terminal and the pad of the said electronic component are electrically connected through the columnar bump extended in these thickness directions on the side of the said semiconductor chip and the said reinforcement board, The Claim 2 or 4 The semiconductor device described. 前記電子部品は、前記補強板の前記半導体チップと反対側の面に固着されている、請求項２、４または５に記載の半導体装置。   The semiconductor device according to claim 2, 4 or 5, wherein the electronic component is fixed to a surface of the reinforcing plate opposite to the semiconductor chip. 前記電子部品は、第２の半導体チップである、請求項２、４、５または６に記載の半導体装置。   The semiconductor device according to claim 2, 4, 5, or 6, wherein the electronic component is a second semiconductor chip. 前記半導体チップおよび前記補強板は、平面視で矩形状の形状を有している、請求項１、２、４、５、６または７に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip and the reinforcing plate have a rectangular shape in plan view. 前記半導体チップは、平面視で矩形状の形状を有しており、前記補強板は、平面視で前記半導体チップの輪郭から各辺の中央部分を内側に控えさせた形状を有している、請求項１、２、４、５、６または７に記載の半導体装置。   The semiconductor chip has a rectangular shape in a plan view, and the reinforcing plate has a shape in which a central portion of each side is kept inward from the outline of the semiconductor chip in a plan view. The semiconductor device according to claim 1, 2, 4, 5, 6 or 7. 前記半導体チップは、平面視で正方形状をなしており、前記補強板は、平面視で前記半導体チップの対角を結ぶ略十字状をなしている、請求項９に記載の半導体装置。   The semiconductor device according to claim 9, wherein the semiconductor chip has a square shape in a plan view, and the reinforcing plate has a substantially cross shape that connects diagonals of the semiconductor chip in a plan view. 前記半導体チップは、平面視で正方形状をなしており、前記補強板は、平面視で前記半導体チップの対角を結ぶ略十字形の星状をなしている、請求項９に記載の半導体装置。   10. The semiconductor device according to claim 9, wherein the semiconductor chip has a square shape in a plan view, and the reinforcing plate has a substantially cross-shaped star shape connecting the diagonals of the semiconductor chip in a plan view. . 前記補強板は、金属板である、請求項１〜１１のいずれか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the reinforcing plate is a metal plate. 請求項１〜１２のいずれか一項に記載の半導体装置と、この半導体装置が実装されたマザー基板と、を備える、電子機器。   An electronic apparatus comprising the semiconductor device according to claim 1 and a mother board on which the semiconductor device is mounted.
JP2008013727A 2008-01-24 2008-01-24 Semiconductor device and electronic apparatus Pending JP2009176931A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020080398A (en) * 2018-11-13 2020-05-28 サムソン エレクトロ−メカニックス カンパニーリミテッド． Package structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020080398A (en) * 2018-11-13 2020-05-28 サムソン エレクトロ−メカニックス カンパニーリミテッド． Package structure
JP7200460B2 (en) 2018-11-13 2023-01-10 サムソン エレクトロ－メカニックス カンパニーリミテッド． package structure

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