JP2009129982A - 半導体装置及びその製造方法 - Google Patents
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Abstract
【解決手段】複数の半導体チップ形成領域A、及び前記複数の半導体チップ形成領域の間に配置され、基板切断位置を含むスクライブ領域Bを有する半導体基板31の、前記複数の半導体チップ形成領域に、電極パッド23を有する半導体チップ11を形成する半導体チップ形成工程と、前記半導体チップ上に、第1の絶縁層13を形成する第1の絶縁層形成工程と、前記第1の絶縁層上に、開口部を有する第2の絶縁層16を形成する第2の絶縁層形成工程と、前記基板切断位置Cに対応する部分の前記半導体基板を切断する切断工程と、を有する半導体装置の製造方法であって、前記開口部は、前記基板切断位置を露出するように形成されることを特徴とする。
【選択図】図25
Description
図11は、本発明の第1の実施の形態に係る半導体装置の断面図である。図11を参照するに、第1の実施の形態の半導体装置10は、半導体チップ11と、内部接続端子12と、絶縁層13(第1の絶縁層)と、金属層26及び第2の金属層27からなる配線パターン14と、ソルダーレジスト16(第2の絶縁層)と、外部接続端子17とを有する。又、D部は、従来の半導体装置において、剥離が問題となっていた部分を示している。
図29は、本発明の第2の実施の形態に係る半導体装置の断面図である。図29において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。図29を参照するに、第2の実施の形態の半導体装置40は、第1の実施の形態の半導体装置10に設けられた金属層26と第2の金属層27とからなる配線パターン14の代わりに、金属層26からなる配線パターン41を設けた以外は半導体装置10と同様に構成される。
絶縁層上に金属層を形成し、次いで、金属層の上面にレジストを塗布し、レジストを露光、現像することで、配線形成領域を露出する開口部を有したレジスト膜を形成し、次いで、金属層を給電層として、電解めっき法等により、開口部に金属膜を形成し、次いで、レジスト膜を除去し、次いで、金属膜が形成されていない領域の金属層をエッチングによって除去することで、金属層と金属膜とからなる配線パターンを形成する方法(セミアディティブ)等を用いても構わない。
11,101 半導体チップ
12,102 内部接続端子
12A,13A,25A,26A,27A,103A 上部
13,103 絶縁層
14,41,104 配線パターン
14A,41A,104A 外部接続端子配設領域
16,106 ソルダーレジスト
17,107 外部接続端子
21,31,109,110 半導体基板
22,111 半導体集積回路
23,112 電極パッド
24,113 保護膜
25 金属箔
25B 下部
26 金属層
27 第2の金属層
28 レジスト膜
A 半導体装置形成領域
B スクライブ領域
C 基板切断位置
L1 距離
T1〜T7 厚さ
H1 高さ
W1 幅
Claims (10)
- 複数の半導体チップ形成領域、及び前記複数の半導体チップ形成領域の間に配置され、基板切断位置を含むスクライブ領域を有する半導体基板の、前記複数の半導体チップ形成領域に、電極パッドを有する半導体チップを形成する半導体チップ形成工程と、前記半導体チップ上に、第1の絶縁層を形成する第1の絶縁層形成工程と、前記第1の絶縁層上に、開口部を有する第2の絶縁層を形成する第2の絶縁層形成工程と、前記基板切断位置に対応する部分の前記半導体基板を切断する切断工程と、を有する半導体装置の製造方法であって、
前記開口部は、前記基板切断位置を露出するように形成されることを特徴とする半導体装置の製造方法。 - 更に、前記半導体チップ形成工程の後に、前記電極パッド上に、内部接続端子を形成する内部接続端子形成工程と、
前記第1の絶縁層形成工程の後に、前記第1の絶縁層上に、前記内部接続端子と電気的に接続される金属層を形成する金属層形成工程と、
前記金属層をエッチングして配線パターンを形成する配線パターン形成工程と、
前記配線パターンの所定の領域に前記配線パターンと電気的に接続される外部接続端子を形成する外部接続端子形成工程と、を有することを特徴とする請求項1記載の半導体装置の製造方法。 - 前記第1の絶縁層は、前記スクライブ領域に対応する前記半導体チップを露出しないように形成されることを特徴とする請求項1又は2記載の半導体装置の製造方法。
- 前記第1の絶縁層は、非感光性の絶縁材料によって形成されることを特徴とする請求項1乃至3の何れか一項記載の半導体装置の製造方法。
- 前記開口部は、エッチング処理工程を含むフォトリソグラフィ法によって形成されることを特徴とする請求項1乃至4の何れか一項記載の半導体装置の製造方法。
- 複数の半導体チップ形成領域、及び前記複数の半導体チップ形成領域の間に配置され、基板切断位置を含むスクライブ領域を有する半導体基板の、前記複数の半導体チップ形成領域に形成された、電極パッドを有する半導体チップと、前記半導体チップ上に形成された、第1の絶縁層と、前記第1の絶縁層上に形成された、開口部を有する第2の絶縁層と、を有する半導体装置であって、
前記開口部は、前記基板切断位置を露出していることを特徴とする半導体装置。 - 更に、前記電極パッド上に形成された、内部接続端子と、
前記第1の絶縁層上に形成され、前記内部接続端子と電気的に接続される金属層からなる配線パターンと、
前記配線パターンと電気的に接続される外部接続端子と、を有することを特徴とする請求項6記載の半導体装置。 - 前記第1の絶縁層は、前記スクライブ領域に対応する前記半導体チップを露出していないことを特徴とする請求項6又は7記載の半導体装置。
- 前記第1の絶縁層は、非感光性の絶縁材料によって形成されていることを特徴とする請求項6乃至8の何れか一項記載の半導体装置。
- 前記開口部は、エッチング処理工程を含むフォトリソグラフィ法によって形成されていることを特徴とする請求項6乃至9の何れか一項記載の半導体装置。
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JP2007300790A JP5139039B2 (ja) | 2007-11-20 | 2007-11-20 | 半導体装置及びその製造方法 |
KR1020080114951A KR20090052282A (ko) | 2007-11-20 | 2008-11-19 | 반도체 장치 및 그 제조 방법 |
US12/273,901 US7906833B2 (en) | 2007-11-20 | 2008-11-19 | Semiconductor device and manufacturing method thereof |
TW097144823A TW200931595A (en) | 2007-11-20 | 2008-11-20 | Semiconductor device and manufacturing method thereof |
EP08169571A EP2065928A3 (en) | 2007-11-20 | 2008-11-20 | Semiconductor device and manufacturing method thereof |
CNA2008101809569A CN101441992A (zh) | 2007-11-20 | 2008-11-20 | 半导体器件及其制造方法 |
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JP4121542B1 (ja) * | 2007-06-18 | 2008-07-23 | 新光電気工業株式会社 | 電子装置の製造方法 |
JP2012134270A (ja) * | 2010-12-21 | 2012-07-12 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US20130183823A1 (en) * | 2012-01-18 | 2013-07-18 | Chipbond Technology Corporation | Bumping process |
JP2019054172A (ja) * | 2017-09-15 | 2019-04-04 | 東芝メモリ株式会社 | 半導体装置 |
KR102543996B1 (ko) * | 2019-09-20 | 2023-06-16 | 주식회사 네패스 | 반도체 패키지 및 이의 제조방법 |
CN112885793A (zh) * | 2021-03-12 | 2021-06-01 | 苏州晶方半导体科技股份有限公司 | 芯片封装结构及其制造方法 |
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JP2002057252A (ja) * | 2000-08-07 | 2002-02-22 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP5070661B2 (ja) | 2001-04-27 | 2012-11-14 | パナソニック株式会社 | 半導体装置およびその製造方法 |
US6818475B2 (en) * | 2001-10-22 | 2004-11-16 | Wen-Kun Yang | Wafer level package and the process of the same |
JP3614828B2 (ja) | 2002-04-05 | 2005-01-26 | 沖電気工業株式会社 | チップサイズパッケージの製造方法 |
JP2004134709A (ja) * | 2002-10-15 | 2004-04-30 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004193497A (ja) * | 2002-12-13 | 2004-07-08 | Nec Electronics Corp | チップサイズパッケージおよびその製造方法 |
JP4322181B2 (ja) * | 2004-07-29 | 2009-08-26 | 三洋電機株式会社 | 半導体装置の製造方法 |
KR100660868B1 (ko) * | 2005-07-06 | 2006-12-26 | 삼성전자주식회사 | 칩의 배면이 몰딩된 반도체 패키지 및 그의 제조방법 |
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TW200931595A (en) | 2009-07-16 |
EP2065928A3 (en) | 2011-01-26 |
KR20090052282A (ko) | 2009-05-25 |
JP5139039B2 (ja) | 2013-02-06 |
CN101441992A (zh) | 2009-05-27 |
US7906833B2 (en) | 2011-03-15 |
US20090127665A1 (en) | 2009-05-21 |
EP2065928A2 (en) | 2009-06-03 |
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