JP2009099774A - Hetero-junction field effect transistor - Google Patents

Hetero-junction field effect transistor Download PDF

Info

Publication number
JP2009099774A
JP2009099774A JP2007270042A JP2007270042A JP2009099774A JP 2009099774 A JP2009099774 A JP 2009099774A JP 2007270042 A JP2007270042 A JP 2007270042A JP 2007270042 A JP2007270042 A JP 2007270042A JP 2009099774 A JP2009099774 A JP 2009099774A
Authority
JP
Japan
Prior art keywords
plane
compound semiconductor
hfet
parallel
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007270042A
Other languages
Japanese (ja)
Inventor
Masaharu Yamashita
雅治 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2007270042A priority Critical patent/JP2009099774A/en
Publication of JP2009099774A publication Critical patent/JP2009099774A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a normally-off type heterostructure field effect transistor of small contact resistance and less gate leakage current. <P>SOLUTION: In the hetero-junction field effect transistor produced using a polarizable compound semiconductor, a hetero-junction interface included in the transistor includes first and second regions 100a parallel to the polar face of the compound semiconductor and a step region 100b between them, a pair of source and drain electrodes 2a and 2b are provided on a compound semiconductor surface 101a parallel to the first and second regions, a gate electrode 1 is provided on a compound semiconductor surface 101b parallel to the step region between the source and drain electrodes, and the step region 100b includes a nonpolar face or a semipolar face having an angle to the polar face. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、分極性を有する化合物半導体を利用したヘテロ接合電界効果型トランジスタ（ＨＦＥＴ）に関し、特にノーマリオフ型ＨＦＥＴの改善に関するものである。   The present invention relates to a heterojunction field effect transistor (HFET) using a compound semiconductor having polarizability, and more particularly to improvement of a normally-off type HFET.

従来において、窒化物系III−Ｖ族化合物半導体を利用したＡｌＧａＮ／ＧａＮへテロ接合電界効果型トランジスタ（ＨＦＥＴ）では、ウルツ鉱型結晶構造（六方晶構造）を有するＡｌＧａＮ層とＧａＮ層の（０００１）面が基板表面と並行になるように形成されている。したがって、ＡｌＧａＮ層とＧａＮ層のピエゾ効果や自発分極によって電子が誘起され、ＡｌＧａＮ／ＧａＮ界面に２次元電子ガス（２ＤＥＧ）が形成される。   Conventionally, in an AlGaN / GaN heterojunction field effect transistor (HFET) using a nitride III-V compound semiconductor, an AlGaN layer having a wurtzite crystal structure (hexagonal structure) and (0001) ) Surface is parallel to the substrate surface. Therefore, electrons are induced by the piezoelectric effect and spontaneous polarization of the AlGaN layer and the GaN layer, and a two-dimensional electron gas (2DEG) is formed at the AlGaN / GaN interface.

図４の模式的な断面図は、そのような２ＤＥＧが形成される様子を視覚的に図解している。なお、本願の図面において、長さ、幅、厚さなどの寸法関係は図面の明瞭化と簡略化のために適宜に変更されており、実際の寸法関係を表してはいない。特に、厚さは相対的に拡大されて示されている。また、図面における同一の参照符号は同一部分または相当部分を表している。   The schematic cross-sectional view of FIG. 4 visually illustrates how such 2DEG is formed. In the drawings of the present application, dimensional relationships such as length, width, and thickness are appropriately changed for clarity and simplification of the drawings, and do not represent actual dimensional relationships. In particular, the thickness is shown relatively enlarged. The same reference numerals in the drawings represent the same or corresponding parts.

図４（Ａ）に示されているように、ＧａＮ層１１に比べてＡｌＧａＮ層１２は小さな結晶格子定数を有している。したがって、ＧａＮ層１１上にＡｌＧａＮ層１２をエピタキシャル結晶成長させた場合、図４（Ａ）中の矢印で示されているように、ＧａＮ層１１はＡｌＧａＮ層１２から圧縮応力を受け、逆にＡｌＧａＮ層１２はＧａＮ層１１から引張応力を受けることになる。そして、これらの応力が、ピエゾ効果を生じる原因となり得る。   As shown in FIG. 4A, the AlGaN layer 12 has a smaller crystal lattice constant than the GaN layer 11. Therefore, when the AlGaN layer 12 is epitaxially grown on the GaN layer 11, the GaN layer 11 receives compressive stress from the AlGaN layer 12 as shown by the arrows in FIG. The layer 12 receives a tensile stress from the GaN layer 11. These stresses can cause a piezo effect.

また、図４（Ｂ）中の矢印で示されているように、ＡｌＧａＮ／ＧａＮ界面はｃ軸（［０００１］方向軸）に対して垂直な関係にある。ＧａＮ層１１のｃ軸方向においては、Ｎ原子面とＧａ原子面とが交互に積層されている。そして、Ｇａ原子面とＮ原子面との電気陰性度の相違に起因して、ＧａＮ層１１内においてｃ軸方向に自発分極が生じ得る。   Further, as indicated by an arrow in FIG. 4B, the AlGaN / GaN interface is in a relationship perpendicular to the c-axis ([0001] direction axis). In the c-axis direction of the GaN layer 11, N atomic planes and Ga atomic planes are alternately stacked. Then, spontaneous polarization can occur in the c-axis direction in the GaN layer 11 due to the difference in electronegativity between the Ga atom plane and the N atom plane.

以上のようなピエゾ効果や自発分極で生じた電子は、ＡｌＧａＮに比べてＧａＮが小さなエネルギバンドギャップを有するので、ＡｌＧａＮ／ＧａＮ界面においてＧａＮ層１１側に蓄積されて２ＤＥＧを形成する。   The electrons generated by the piezo effect and spontaneous polarization as described above are accumulated on the GaN layer 11 side at the AlGaN / GaN interface to form 2DEG because GaN has a smaller energy band gap than AlGaN.

図５は、従来のＡｌＧａＮ／ＧａＮへテロ接合ＦＥＴの一例を模式的断面図で図解している。このヘテロ接合ＦＥＴにおいては、ＧａＮ層１３０の（０００１）表面上にＡｌＧａＮ層１３１がエピタキシャルに積層されている。ＡｌＧａＮ層１３１上においては、一対のソース・ドレイン電極２ａ、２ｂが形成されている。また、それらのソース・ドレイン電極２ａ、２ｂ間において、ゲート電極３０が形成されている。このゲート電極３０はショットキ電極であり、その下のＡｌＧａＮ層１３１内には空乏層４００が生成している。   FIG. 5 is a schematic cross-sectional view illustrating an example of a conventional AlGaN / GaN heterojunction FET. In this heterojunction FET, an AlGaN layer 131 is epitaxially stacked on the (0001) surface of the GaN layer 130. On the AlGaN layer 131, a pair of source / drain electrodes 2a, 2b is formed. A gate electrode 30 is formed between the source / drain electrodes 2a and 2b. The gate electrode 30 is a Schottky electrode, and a depletion layer 400 is generated in the AlGaN layer 131 therebelow.

このように構成されている図５のへテロ接合ＦＥＴにおいては、ＡｌＧａＮ／ＧａＮ界面に２次元電子ガス２６０が存在するので、ソース・ドレイン電極２ａ、２ｂ間に電圧を印加すれば、ゲート電圧がゼロの場合でもドレイン電流が流れる。したがって、このようなＨＦＥＴは、ノーマリオン型のＨＦＥＴと呼ばれている。   In the heterojunction FET of FIG. 5 configured as described above, since the two-dimensional electron gas 260 exists at the AlGaN / GaN interface, if a voltage is applied between the source / drain electrodes 2a and 2b, the gate voltage is reduced. Even when zero, drain current flows. Therefore, such an HFET is called a normally-on type HFET.

ところで、一般的な回路へＨＦＥＴを応用する場合、ゲート電圧がゼロの時にドレイン電流が流れることのないノーマリオフ型のＨＦＥＴが望ましい。したがって、先行技術においては、種々のノーマリオフ型ＨＦＥＴの作製が試みられている。   By the way, when applying an HFET to a general circuit, a normally-off type HFET in which a drain current does not flow when the gate voltage is zero is desirable. Therefore, in the prior art, production of various normally-off HFETs has been attempted.

図６では、先行技術によるノーマリオフ型のＨＦＥＴの一例が模式的断面図で図解されている。図５に比べて、図６のＨＦＥＴは、ＡｌＧａＮ層１３１の表面に凹部１３１ａが形成され、その凹部にショットキゲート電極４０が形成されていることにおいて異なっている。この図６のＨＦＥＴにおいては、ショットキゲート電極４０がＡｌＧａＮ層１３１の表面の凹部１３１ａ内に形成されているので、その下の空乏層４１０が深い位置まで到達し得る。そして、その空乏層４１０の底面がＡｌＧａＮ／ＧａＮ界面に至れば、そこにおいて２次元電子ガス２６０ａが途切れることになる。すなわち、ゲート電極４０下には２次元電子ガス２６０ａが存在しておらず、図６のＨＦＥＴのノーマリオフ動作が可能となる。   In FIG. 6, an example of a normally-off type HFET according to the prior art is illustrated in a schematic cross-sectional view. Compared to FIG. 5, the HFET of FIG. 6 differs in that a recess 131 a is formed on the surface of the AlGaN layer 131 and a Schottky gate electrode 40 is formed in the recess. In the HFET of FIG. 6, since the Schottky gate electrode 40 is formed in the recess 131a on the surface of the AlGaN layer 131, the depletion layer 410 below can reach a deep position. When the bottom surface of the depletion layer 410 reaches the AlGaN / GaN interface, the two-dimensional electron gas 260a is interrupted there. That is, the two-dimensional electron gas 260a does not exist under the gate electrode 40, and the normally-off operation of the HFET of FIG. 6 is possible.

他方、非特許文献１の信学技報、ＥＤ２００５−２０５、ｐｐ．３５−３９においては、ウルツ鉱型結晶構造においてピエゾ効果や自発分極によって深さ方向に分極電界を生じない無極性面を利用してノーマリオフ型ＨＦＥＴを作製する方法が開示されている。より具体的には、非特許文献１のノーマリオフ型ＨＦＥＴにおいては、ＧａＮ層の無極性面である（１１−２０）表面上にＡｌＧａＮ層をエピタキシャルに積層し、そのＡｌＧａＮ層の（１１−２０）表面上に一対のソース・ドレイン電極とそれらの間のショットキゲート電極が形成される。
信学技報、ＥＤ２００５−２０５、ｐｐ．３５−３９ On the other hand, the non-patent literature 1 of IEICE Technical Report, ED2005-205, pp. 35-39 discloses a method for producing a normally-off type HFET using a nonpolar surface that does not generate a polarization electric field in the depth direction due to the piezoelectric effect or spontaneous polarization in the wurtzite crystal structure. More specifically, in the normally-off HFET of Non-Patent Document 1, an AlGaN layer is epitaxially stacked on the (11-20) surface, which is a nonpolar surface of the GaN layer, and the (11-20) of the AlGaN layer is epitaxially stacked. A pair of source / drain electrodes and a Schottky gate electrode between them are formed on the surface.
IEICE Technical Report, ED2005-205, pp. 35-39

図６のＨＦＥＴを作製する場合、ＡｌＧａＮ層１３１の表面における凹部１３１ａは、ドライエッチングによって形成される。その場合、凹部１３１ａの底面近傍において半導体がダメージを受ける恐れがある。凹部１３１ａの底面近傍で半導体がダメージを受けることは、ゲート電極４０下のチャネル領域がダメージを受けることを意味し、ＨＦＥＴの特性に悪影響を及ぼすことが明らかである。   When the HFET of FIG. 6 is manufactured, the recess 131a on the surface of the AlGaN layer 131 is formed by dry etching. In that case, the semiconductor may be damaged near the bottom surface of the recess 131a. It is clear that the damage to the semiconductor near the bottom surface of the recess 131a means that the channel region under the gate electrode 40 is damaged, and adversely affects the characteristics of the HFET.

また、ショットキゲート電極４０下の空乏層４１０の深さをヘテロ接合界面近傍に至るように、凹部１３１ａの深さをドライエッチングによって高い精度で制御することは困難である。その結果、図６のＨＦＥＴにおいては、その安定した良好な特性と高い生産歩留まりを達成することが困難である。   In addition, it is difficult to control the depth of the recess 131a with high accuracy by dry etching so that the depth of the depletion layer 410 under the Schottky gate electrode 40 reaches the vicinity of the heterojunction interface. As a result, in the HFET of FIG. 6, it is difficult to achieve stable and good characteristics and a high production yield.

他方、非特許文献１におけるように無極性の（１１−２０）表面上にソース・ドレイン電極を形成する場合、極性面（０００１）に平行なＡｌＧａＮ／ＧａＮ界面を利用する場合と同様にソース・ドレイン電極下にキャリアを生じさせるためには、ＡｌＧａＮ層にドーピングを行なう必要がある。なぜならば、無極性（１１−２０）表面に平行なＡｌＧａＮ／ＧａＮ界面には２次元電子ガスが生成していないからである。したがって、ソース・ドレイン電極のコンタクト抵抗を低減させるためには、ＡｌＧａＮ層のドーピング濃度を増やさなければならない。   On the other hand, when the source / drain electrodes are formed on the nonpolar (11-20) surface as in Non-Patent Document 1, the source / drain electrodes are formed in the same manner as in the case of using the AlGaN / GaN interface parallel to the polar plane (0001). In order to generate carriers under the drain electrode, it is necessary to dope the AlGaN layer. This is because no two-dimensional electron gas is generated at the AlGaN / GaN interface parallel to the nonpolar (11-20) surface. Therefore, in order to reduce the contact resistance of the source / drain electrodes, the doping concentration of the AlGaN layer must be increased.

しかし、そのドーピング濃度を増やし過ぎれば、ショットキゲート電極のリーク電流が増大するという問題がある。すなわち、ウルツ鉱型結晶構造の無極性面上にソース・ドレイン電極形成して得られるＨＦＥＴにおいては、ゲートリーク電流を増大させることなく、ソース・ドレイン電極のコンタクト抵抗を低減させることが困難である。   However, if the doping concentration is increased too much, there is a problem that the leakage current of the Schottky gate electrode increases. That is, in the HFET obtained by forming the source / drain electrodes on the nonpolar surface of the wurtzite crystal structure, it is difficult to reduce the contact resistance of the source / drain electrodes without increasing the gate leakage current. .

以上のような先行技術における状況に鑑み、本発明は、コンタクト抵抗が小さくかつゲートリーク電流が少なくて安定した特性を有するノーマリオフ型ＨＦＥＴを高い歩留まりで提供することを目的とする。   In view of the situation in the prior art as described above, an object of the present invention is to provide a normally-off HFET having a stable characteristic with a small contact resistance and a small gate leakage current at a high yield.

本発明によれば、分極性を有する化合物半導体を用いて作製されたヘテロ接合電界効果型トランジスタにおいて、そのトランジスタに含まれるヘテロ接合界面は化合物半導体の極性面に平行な第１と第２の領域とそれらの間の段差領域とを含み、それらの第１と第２の領域に平行な化合物半導体表面上に一対のソース・ドレイン電極が設けられ、それらのソース・ドレイン電極間において段差領域に平行な化合物半導体表面上にゲート電極が設けられており、段差領域は極性面に対して角度を有する無極性面または半極性面を含んでいることを特徴としている。   According to the present invention, in a heterojunction field effect transistor fabricated using a polarizable compound semiconductor, the heterojunction interface included in the transistor is first and second regions parallel to the polar plane of the compound semiconductor. And a step region between them, a pair of source / drain electrodes are provided on the surface of the compound semiconductor parallel to the first and second regions, and parallel to the step region between the source / drain electrodes A gate electrode is provided on the surface of the compound semiconductor, and the step region includes a nonpolar surface or a semipolar surface having an angle with respect to the polar surface.

なお、そのゲート電極は、ショトキ電極であり得る。また、化合物半導体は、ウルツ鉱型結晶構造を有する窒化物系III‐Ｖ族化合物半導体であり得る。その窒化物系III‐Ｖ族化合物半導体の極性面は（０００１）面であって、(１１−２０）面または（１０−１０）面は無極性面であり、（０１−１２）面または（０１−１１）面は半極性面である。   The gate electrode can be a shot electrode. The compound semiconductor may be a nitride III-V compound semiconductor having a wurtzite crystal structure. The polar face of the nitride III-V compound semiconductor is the (0001) face, the (11-20) face or the (10-10) face is a nonpolar face, and the (01-12) face or ( The 01-11) plane is a semipolar plane.

以上のような本発明によれば、極性面に平行なヘテロ界面に沿った化合物半導体表面に一対のソース・ドレイン電極が形成されかつそれらの間に設けられた段差部において無極性面または半極性面に平行な化合物半導体表面にゲート電極が形成されるので、コンタクト抵抗が小さくかつゲートリーク電流が少なくて安定した特性を有するノーマリオフ型ＨＦＥＴを高い歩留まりで提供することができる。   According to the present invention as described above, the pair of source / drain electrodes are formed on the surface of the compound semiconductor along the heterointerface parallel to the polar face, and the nonpolar face or the semipolar face is provided in the step portion provided therebetween. Since the gate electrode is formed on the surface of the compound semiconductor parallel to the surface, a normally-off type HFET having a stable characteristic with a small contact resistance and a small gate leakage current can be provided with a high yield.

本発明者が鋭意検討を重ねた結果として、窒化物系III−Ｖ族化合物半導体の無極性面を部分的に利用することによって、ゲートリーク電流が少なくかつソース・ドレイン電極のコンタクト抵抗が小さいノーマリオフ型のＨＦＥＴを実現し得ることが見出された。   As a result of extensive studies by the inventor, the non-polar surface of the nitride-based III-V compound semiconductor is partially used so that the gate leakage current is small and the contact resistance of the source / drain electrodes is small. It has been found that a type of HFET can be realized.

すなわち、本発明では、上述のように極性面に平行なヘテロ界面に沿った化合物半導体表面に一対のソース・ドレイン電極が形成されかつそれらの間に設けられた段差部において無極性面または半極性面に平行な化合物半導体表面にゲート電極が形成されることを特徴としている。   That is, in the present invention, as described above, a pair of source / drain electrodes are formed on the surface of the compound semiconductor along the heterointerface parallel to the polar surface, and a nonpolar surface or semipolar surface is formed in the step portion provided therebetween. A gate electrode is formed on the surface of the compound semiconductor parallel to the surface.

より具体的には、分極性を有する化合物半導体において、極性面に平行にヘテロ接合を形成した場合、ピエゾ効果および自発分極によってそのヘテロ界面に１０13ｃｍ-2程度のシートキャリア密度を有する２ＤＥＧが形成され、この２ＤＥＧに近接してソース・ドレイン電極を形成することによって、接触抵抗の小さいオーミックのソース・ドレイン電極を実現することができる。他方、極性面に対して角度をなす無極性面または半極性面に平行にヘテロ接合を形成した場合、そのヘテロ接合においてピエゾ分極や自発分極が生じないかまたは不十分であるので、そのヘテロ接合に沿って高密度の２ＤＥＧ（キャリア）が存在しない。その結果、リーク電流が少なくて優れた特性を有するゲート電極を形成することが可能となる。 More specifically, in a compound semiconductor having polarizability, when a heterojunction is formed parallel to the polar surface, 2DEG having a sheet carrier density of about 10 13 cm −2 at the heterointerface due to the piezoelectric effect and spontaneous polarization By forming the source / drain electrodes in the vicinity of the 2DEG, ohmic source / drain electrodes with low contact resistance can be realized. On the other hand, when a heterojunction is formed parallel to a nonpolar or semipolar plane that forms an angle with respect to the polar plane, piezoelectric polarization or spontaneous polarization does not occur or is insufficient at the heterojunction. There is no high density 2DEG (carrier) along. As a result, it is possible to form a gate electrode having excellent characteristics with little leakage current.

(実施形態１)
図１においては、本発明の実施形態１によるＨＦＥＴが模式的断面図で図解されている。このＨＦＥＴに含まれるＧａＮ層１００は、（０００１）面に平行な主表面１００ａとその主表面に直交する（１１−２０）面または（１０−１０）面からなる段差表面１００ｂを有している。このような段差部は、例えば段差部を有するサファイア基板やＳｉＣ基板上にＧａＮ層を結晶成長させることによって形成し得るし、平坦なＧａＮ層表面にＲＩＥ（反応性イオンエッチング）などを施すことによって形成してもよい。 (Embodiment 1)
In FIG. 1, an HFET according to Embodiment 1 of the present invention is illustrated in a schematic cross-sectional view. The GaN layer 100 included in the HFET has a main surface 100a parallel to the (0001) plane and a step surface 100b composed of a (11-20) plane or a (10-10) plane orthogonal to the main surface. . Such a stepped portion can be formed, for example, by crystal growth of a GaN layer on a sapphire substrate or SiC substrate having the stepped portion, or by performing RIE (reactive ion etching) or the like on the flat GaN layer surface. It may be formed.

例えば、ＳｉＣ基板上において、Ｃｌ2やＳｉＣｌ4などの塩素系のガスまたはＣＦ4やＳＦ6などのフッ素系のガスを用いたＲＩＥまたはＩＣＰ（誘導結合プラズマ）によって、その基板表面に段差部を形成することができる。また、ＧａＮ層上においては、Ｃｌ2やＳｉＣｌ4などの塩素系のガスまたはＣＦ4やＳＦ6などのフッ素系のガスを用いたＲＩＥまたはＩＣＰによって、その表面に段差部を形成することができる。なお、このような異方性エッチングによって形成される段差部の側面はイオンやプラズマによるダメージを受けにくく、完成後のＨＦＥＴのチャネル領域におけるダメージとなる恐れが少ない。 For example, a step portion is formed on the surface of a SiC substrate by RIE or ICP (inductively coupled plasma) using a chlorine-based gas such as Cl 2 or SiCl 4 or a fluorine-based gas such as CF 4 or SF 6. Can be formed. On the GaN layer, a stepped portion can be formed on the surface by RIE or ICP using a chlorine-based gas such as Cl 2 or SiCl 4 or a fluorine-based gas such as CF 4 or SF 6. . Note that the side surface of the stepped portion formed by such anisotropic etching is less likely to be damaged by ions or plasma, and is less likely to be damaged in the channel region of the completed HFET.

ＧａＮ層１００上には、エピタキシャル結晶成長によって、ＡｌＧａＮ層１０１が積層される。したがって、そのＡｌＧａＮ層１０１も、（０００１）面に平行な主表面１０１ａとその主表面に直交する無極性の（１１−２０）面または（１０−１０）面からなる段差表面１０１ｂを有している。   An AlGaN layer 101 is stacked on the GaN layer 100 by epitaxial crystal growth. Therefore, the AlGaN layer 101 also has a main surface 101a parallel to the (0001) plane and a step surface 101b composed of a nonpolar (11-20) plane or (10-10) plane orthogonal to the main surface. Yes.

このＡｌＧａＮ層１０１の主表面１０１ａ上では、段差部の右側と左側に配置された一対のソース・ドレイン電極２ａ、２ｂとしてオーミック電極が形成される。そして、それらのソース・ドレイン電極２ａ、２ｂ間の段差表面１０１ｂ上に、ゲート電極１としてショットキ電極が形成される。   On the main surface 101a of the AlGaN layer 101, ohmic electrodes are formed as a pair of source / drain electrodes 2a and 2b arranged on the right and left sides of the stepped portion. Then, a Schottky electrode is formed as the gate electrode 1 on the step surface 101b between the source / drain electrodes 2a and 2b.

なお、ゲート電極としては、例えば複数種の材料が積層されたＷＮ(窒化タングステン)／Ａｕ電極、Ｐｔを主原料とするＴｉ／Ｐｔ／Ａｕ電極、Ｔｉ／Ａｕ電極などを利用することができる。また、ソース・ドレイン電極としては、例えばＴｉ／Ａｌ／Ａｕ電極を利用することができる。   As the gate electrode, for example, a WN (tungsten nitride) / Au electrode in which a plurality of kinds of materials are stacked, a Ti / Pt / Au electrode using Pt as a main material, a Ti / Au electrode, or the like can be used. As source / drain electrodes, for example, Ti / Al / Au electrodes can be used.

以上のように構成されている図１のＨＦＥＴでは、ソース・ドレイン電極２ａ、２ｂ下において極性面（０００１）に平行なＡｌＧａＮ／ＧａＮ界面１００ａに２次元電子ガス２００が生成しており、この２次元電子ガスはソース・ドレイン電極のコンタクト抵抗の低減に寄与し得る。したがって、ソース・ドレイン電極２ａ、２ｂのコンタクト抵抗を低減させるために、ＡｌＧａＮ層１０１に高濃度の不純物をドープする必要がない。   In the HFET of FIG. 1 configured as described above, the two-dimensional electron gas 200 is generated at the AlGaN / GaN interface 100a parallel to the polar plane (0001) under the source / drain electrodes 2a and 2b. The dimensional electron gas can contribute to the reduction of the contact resistance of the source / drain electrodes. Therefore, in order to reduce the contact resistance of the source / drain electrodes 2a and 2b, it is not necessary to dope the AlGaN layer 101 with a high concentration impurity.

他方、ショットキゲート電極１下においては、無極性面（１１−２０）または（１０−１０）に平行なＡｌＧａＮ／ＧａＮ界面１００ｂに２次元電子ガス２００が生成しない。したがって、本実施形態１による図１のＨＦＥＴにおいては、ノーマリオフ動作が可能である。   On the other hand, under the Schottky gate electrode 1, the two-dimensional electron gas 200 is not generated at the AlGaN / GaN interface 100b parallel to the nonpolar plane (11-20) or (10-10). Therefore, the normally off operation is possible in the HFET of FIG. 1 according to the first embodiment.

また、上述のようにＡｌＧａＮ層１０１のドーピング濃度が低くてもよいことと、ショットキゲート電極１下に２次元電子ガス２００が生成しないこととの効果として、ショットキゲート電極１においてはリーク電流が効果的に抑制され得る。すなわち、本実施形態１による図１のトランジスタは、優れたゲート耐圧を有するノーマルオフ型ＨＦＥＴであり得る。   In addition, as described above, a leakage current is effective in the Schottky gate electrode 1 because the doping concentration of the AlGaN layer 101 may be low and the two-dimensional electron gas 200 is not generated under the Schottky gate electrode 1. Can be suppressed. That is, the transistor of FIG. 1 according to Embodiment 1 can be a normally-off HFET having an excellent gate breakdown voltage.

(実施形態２)
図２では、本発明の実施形態２によるＨＦＥＴが模式的断面図で図解されている。図１に比べて、この図２のＨＦＥＴにおいては、ＧａＮ層１００が（０００１）面に平行な主表面１００ａに対して９０度未満の角度で交差する半極性の（０１−１２）面または（０１−１１）面からなる傾斜段差表面１００ｃを有していることにおいて異なっている。これに伴って、ＡｌＧａＮ層１０１も半極性の（０１−１２）面または（０１−１１）面からなる傾斜段差表面１０１ｃを有しており、この傾斜段差表面１０１ｃ上にショットキゲート電極１０が形成されている。 (Embodiment 2)
In FIG. 2, an HFET according to Embodiment 2 of the present invention is illustrated in a schematic cross-sectional view. Compared to FIG. 1, in the HFET of FIG. 2, the GaN layer 100 is a semipolar (01-12) plane intersecting the main surface 100 a parallel to the (0001) plane at an angle of less than 90 degrees or ( 01-11) It differs in having an inclined step surface 100c made of a plane. Accordingly, the AlGaN layer 101 also has an inclined step surface 101c made of a semipolar (01-12) plane or (01-11) plane, and the Schottky gate electrode 10 is formed on the inclined step surface 101c. Has been.

このように構成されている図２のＨＦＥＴにおいても、ソース・ドレイン電極２ａ、２ｂ下における極性面（０００１）に平行なＡｌＧａＮ／ＧａＮ界面１００ａに２次元電子ガス２００が生成しており、この２次元電子ガスはソース・ドレイン電極のコンタクト抵抗の低減に寄与し得る。したがって、ソース・ドレイン電極２ａ、２ｂのコンタクト抵抗を低減させるために、ＡｌＧａＮ層１０１に高濃度の不純物をドープする必要がない。   In the HFET of FIG. 2 configured as described above, the two-dimensional electron gas 200 is generated at the AlGaN / GaN interface 100a parallel to the polar plane (0001) under the source / drain electrodes 2a and 2b. The dimensional electron gas can contribute to the reduction of the contact resistance of the source / drain electrodes. Therefore, in order to reduce the contact resistance of the source / drain electrodes 2a and 2b, it is not necessary to dope the AlGaN layer 101 with a high concentration impurity.

また、ショットキゲート電極１０下においては、半極性面（０１−１２）または（０１−１１）に平行なＡｌＧａＮ／ＧａＮ界面１００ｃに２次元電子ガスが発生してもその濃度が希薄である。したがって、図２のＨＦＥＴにおいても、ノーマリオフ動作が可能である。   Also, under the Schottky gate electrode 10, even if a two-dimensional electron gas is generated at the AlGaN / GaN interface 100c parallel to the semipolar plane (01-12) or (01-11), the concentration is low. Therefore, the normally-off operation is also possible in the HFET of FIG.

また、実施形態１の場合と同様に、本実施形態２においてもＡｌＧａＮ層１０１のドーピング濃度が低くてよいことと、ショットキゲート電極１０下に２次元電子ガスが生成してもその濃度が希薄なこととの効果として、ショットキ電極１０においてもゲートリーク電流が効果的に抑制され得る。すなわち、本実施形態２による図２のトランジスタも、優れたゲート耐圧を有するノーマルオフ型ＨＦＥＴであり得る。   As in the case of the first embodiment, the doping concentration of the AlGaN layer 101 may be low also in the second embodiment, and even if a two-dimensional electron gas is generated under the Schottky gate electrode 10, the concentration is low. As an effect, the gate leakage current can be effectively suppressed also in the Schottky electrode 10. That is, the transistor of FIG. 2 according to the second embodiment can also be a normal-off type HFET having an excellent gate breakdown voltage.

(実施形態３)
図３では、本発明の実施形態３によるＨＦＥＴが模式的断面図で図解されている。図１に比べて、この図３のＨＦＥＴにおいては、ＧａＮ層１００が無極性の（１１−２０）面または（１０−１０）面からなる表面１０１ｂおよび半極性の（０１−１２）面または（０１−１１）面からなる表面１０１ｃを有する段差部を含んでいることにおいて異なっている。これに伴って、ＡｌＧａＮ層１０１も無極性の（１１−２０）面または（１０−１０）面からなる表面１０１ｂおよび半極性の（０１−１２）面または（０１−１１）面からなる表面１０１ｃを有する段差部を含んでおり、この段差部上にショットキゲート電極２０が形成されている。 (Embodiment 3)
In FIG. 3, an HFET according to Embodiment 3 of the present invention is illustrated in a schematic cross-sectional view. Compared to FIG. 1, in the HFET of FIG. 3, the GaN layer 100 has a nonpolar (11-20) plane or a (10-10) plane 101 b and a semipolar (01-12) plane ( 01-11) It differs in that it includes a stepped portion having a surface 101c composed of a plane. Along with this, the AlGaN layer 101 also has a nonpolar (11-20) or (10-10) surface 101b and a semipolar (01-12) or (01-11) surface 101c. The Schottky gate electrode 20 is formed on the stepped portion.

このように構成されている図３のＨＦＥＴは、図１と図２に示されたＨＦＥＴの両者の特徴を含んでおり、それらの中間的特性を有していると言える。すなわち、本実施形態３による図３のトランジスタも、優れたゲート耐圧を有するノーマルオフ型ＨＦＥＴであり得る。   The HFET of FIG. 3 configured as described above includes the characteristics of both the HFETs shown in FIGS. 1 and 2 and can be said to have an intermediate characteristic between them. That is, the transistor of FIG. 3 according to the third embodiment can also be a normally-off HFET having an excellent gate breakdown voltage.

なお、上述の実施形態１−３ではＡｌＧａＮ／ＧａＮヘテロ接合を含むＨＦＥＴが例示されたが、本発明は分極性を有する他の種々の化合物半導体によるヘテロ接合を含むＨＦＥＴにも適用され得ることが明らかであろう。   In the above-described Embodiments 1-3, the HFET including the AlGaN / GaN heterojunction is illustrated. However, the present invention can also be applied to an HFET including a heterojunction of various other compound semiconductors having polarizability. It will be clear.

また、上述の実施形態では、段差部を構成する結晶面として無極性の（１１−２０）面と（１０−１０）面および半極性の（０１−１２）面と（０１−１１）面が例示されたが、（１１−２０）面と（１０−１０）面に限らず（０００１）面に直交するその他の面も無極性であって、（０００１）面に対して傾斜しているその他の面も半極性面であり得ることが理解されよう。   In the above-described embodiment, the nonpolar (11-20) plane and (10-10) plane and the semipolar (01-12) plane and (01-11) plane are the crystal planes constituting the stepped portion. Although illustrated, not only the (11-20) plane and the (10-10) plane, but other planes orthogonal to the (0001) plane are also nonpolar and are inclined with respect to the (0001) plane. It will be appreciated that this plane can also be a semipolar plane.

以上のように、本発明によって、コンタクト抵抗が小さくかつゲートリーク電流の少ないノーマリオフ型ＨＦＥＴを高い生産歩留まりで提供することができる。   As described above, according to the present invention, a normally-off HFET having a small contact resistance and a small gate leakage current can be provided with a high production yield.

本発明の一実施形態によるノーマリオフ型ＨＦＥＴを示す模式的断面図である。1 is a schematic cross-sectional view showing a normally-off HFET according to an embodiment of the present invention. 本発明の他の実施形態によるノーマリオフ型ＨＦＥＴを示す模式的断面図である。FIG. 5 is a schematic cross-sectional view showing a normally-off HFET according to another embodiment of the present invention. 本発明のさらに他の実施形態によるノーマリオフ型ＨＦＥＴを示す模式的断面図である。FIG. 6 is a schematic cross-sectional view showing a normally-off type HFET according to still another embodiment of the present invention. ＡｌＧａＮ／ＧａＮ界面においてピエゾ効果と自発分極によって２ＤＥＧが形成される様子を説明するための模式的断面図である。It is typical sectional drawing for demonstrating a mode that 2DEG is formed by the piezoelectric effect and spontaneous polarization in an AlGaN / GaN interface. 従来のノーマリオン型ＨＦＥＴを示す模式的断面図である。It is typical sectional drawing which shows the conventional normally-on type HFET. 従来のノーマリオフ型ＨＦＥＴを示す模式的断面図である。It is typical sectional drawing which shows the conventional normally-off type HFET.

符号の説明Explanation of symbols

１、１０、２０、３０、４０ ゲート電極、２ａ、２ｂ ソース・ドレイン電極、１１、１００、１３０ ＧａＮ層、１２、１０１、１３１ ＡｌＧａＮ層、１３１ａ ＡｌＧａＮ層表面の凹部、１００ａ ＧａＮ層の極性主面、１０１ａ ＡｌＧａＮ層の極性主面、１００ｂ ＧａＮ層における無極性の段差面、１０１ｂ ＡｌＧａＮ層における無極性の段差面、１００ｃ ＧａＮ層における半極性の傾斜段差面、１０１ｃ ＡｌＧａＮ層における半極性の傾斜段差面、２００、２６０、２６０ａ ２次元電子ガス、４００、４１０ 空乏層。   1, 10, 20, 30, 40 Gate electrode, 2a, 2b Source / drain electrode, 11, 100, 130 GaN layer, 12, 101, 131 AlGaN layer, 131a Recessed surface of AlGaN layer, Polar main surface of 100a GaN layer , 101a Polar main surface of the AlGaN layer, nonpolar step surface in the 100b GaN layer, nonpolar step surface in the 101b AlGaN layer, semipolar inclined step surface in the 100c GaN layer, semipolar inclined step surface in the 101c AlGaN layer 200, 260, 260a Two-dimensional electron gas, 400, 410 Depletion layer.

Claims (5)

分極性を有する化合物半導体を用いて作製されたヘテロ接合電界効果型トランジスタであって、
前記トランジスタに含まれるヘテロ接合界面は前記化合物半導体の極性面に平行な第１と第２の領域とそれらの間の段差領域とを含み、
前記第１と第２の領域に平行な化合物半導体表面上に一対のソース・ドレイン電極が設けられ、
前記ソース・ドレイン電極間において前記段差領域に平行な化合物半導体表面上にゲート電極が設けられており、
前記段差領域は前記極性面に対して角度を有する無極性面または半極性面を含んでいることを特徴とするトランジスタ。 A heterojunction field-effect transistor manufactured using a compound semiconductor having a polarity,
The heterojunction interface included in the transistor includes first and second regions parallel to the polar surface of the compound semiconductor and a step region therebetween.
A pair of source / drain electrodes is provided on the surface of the compound semiconductor parallel to the first and second regions;
A gate electrode is provided on the surface of the compound semiconductor parallel to the step region between the source / drain electrodes,
The transistor is characterized in that the step region includes a nonpolar surface or a semipolar surface having an angle with respect to the polar surface. 前記ゲート電極はショトキ電極であることを特徴とする請求項１に記載のトランジスタ。   The transistor according to claim 1, wherein the gate electrode is a Schottky electrode. 前記化合物半導体はウルツ鉱型結晶構造を有する窒化物系III‐Ｖ族化合物半導体であることを特徴とする請求項１または２に記載のトランジスタ。   3. The transistor according to claim 1, wherein the compound semiconductor is a nitride III-V group compound semiconductor having a wurtzite crystal structure. 前記極性面は（０００１）面であることを特徴とする請求項３に記載のトランジスタ。   The transistor according to claim 3, wherein the polar plane is a (0001) plane. 前記無極性面は(１１−２０）面または（１０−１０）面であり、前記半極性面は（０１−１２）面または（０１−１１）面であることを特徴とする請求項３または４に記載のトランジスタ。   The nonpolar plane is a (11-20) plane or a (10-10) plane, and the semipolar plane is a (01-12) plane or a (01-11) plane. 5. The transistor according to 4.
JP2007270042A 2007-10-17 2007-10-17 Hetero-junction field effect transistor Pending JP2009099774A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007270042A JP2009099774A (en) 2007-10-17 2007-10-17 Hetero-junction field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007270042A JP2009099774A (en) 2007-10-17 2007-10-17 Hetero-junction field effect transistor

Publications (1)

Publication Number Publication Date
JP2009099774A true JP2009099774A (en) 2009-05-07

Family

ID=40702493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007270042A Pending JP2009099774A (en) 2007-10-17 2007-10-17 Hetero-junction field effect transistor

Country Status (1)

Country Link
JP (1) JP2009099774A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082445A (en) * 2009-10-09 2011-04-21 Sumitomo Electric Ind Ltd Semiconductor device and method of manufacturing the same
JP2011222765A (en) * 2010-04-09 2011-11-04 Sumitomo Electric Ind Ltd Nitride electronic device and method of manufacturing the nitride electronic device
JP2012204577A (en) * 2011-03-25 2012-10-22 Nippon Telegr & Teleph Corp <Ntt> Nitride semiconductor device and method of manufacturing the same
CN102856355A (en) * 2012-09-04 2013-01-02 程凯 Enhanced semiconductor device
WO2015009576A1 (en) * 2013-07-15 2015-01-22 Hrl Laboratories, Llc Hemt device and method
US9601610B1 (en) 2015-06-18 2017-03-21 Hrl Laboratories, Llc Vertical super junction III/nitride HEMT with vertically formed two dimensional electron gas
US10090406B2 (en) 2014-09-18 2018-10-02 Infineon Technologies Austria Ag Non-planar normally off compound semiconductor device
US10283633B2 (en) 2017-09-19 2019-05-07 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
CN112397586A (en) * 2020-11-23 2021-02-23 江苏大学 Normally-on silicon substrate high electron mobility transistor and manufacturing method thereof
CN112397587A (en) * 2020-11-23 2021-02-23 江苏大学 Normally-on high electron mobility transistor and manufacturing method thereof
WO2022061525A1 (en) * 2020-09-22 2022-03-31 苏州晶湛半导体有限公司 Semiconductor structure and method for manufacture thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347315A (en) * 2002-05-23 2003-12-05 Sharp Corp Semiconductor device, manufacturing method thereof, power amplifier, and radio communication system
JP2006100820A (en) * 2004-09-24 2006-04-13 Internatl Rectifier Corp Power semiconductor device
JP2007088185A (en) * 2005-09-21 2007-04-05 Toshiba Corp Semiconductor device and its fabrication process
JP2008004720A (en) * 2006-06-22 2008-01-10 Nippon Telegr & Teleph Corp <Ntt> Hetero-structure field effect transistor using nitride semiconductor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003347315A (en) * 2002-05-23 2003-12-05 Sharp Corp Semiconductor device, manufacturing method thereof, power amplifier, and radio communication system
JP2006100820A (en) * 2004-09-24 2006-04-13 Internatl Rectifier Corp Power semiconductor device
JP2007088185A (en) * 2005-09-21 2007-04-05 Toshiba Corp Semiconductor device and its fabrication process
JP2008004720A (en) * 2006-06-22 2008-01-10 Nippon Telegr & Teleph Corp <Ntt> Hetero-structure field effect transistor using nitride semiconductor

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011082445A (en) * 2009-10-09 2011-04-21 Sumitomo Electric Ind Ltd Semiconductor device and method of manufacturing the same
JP2011222765A (en) * 2010-04-09 2011-11-04 Sumitomo Electric Ind Ltd Nitride electronic device and method of manufacturing the nitride electronic device
JP2012204577A (en) * 2011-03-25 2012-10-22 Nippon Telegr & Teleph Corp <Ntt> Nitride semiconductor device and method of manufacturing the same
CN102856355A (en) * 2012-09-04 2013-01-02 程凯 Enhanced semiconductor device
WO2015009576A1 (en) * 2013-07-15 2015-01-22 Hrl Laboratories, Llc Hemt device and method
US9490357B2 (en) 2013-07-15 2016-11-08 Hrl Laboratories, Llc Vertical III-nitride semiconductor device with a vertically formed two dimensional electron gas
US10325997B2 (en) 2013-07-15 2019-06-18 Hrl Laboratories, Llc Vertical III-nitride semiconductor device with a vertically formed two dimensional electron gas
US10090406B2 (en) 2014-09-18 2018-10-02 Infineon Technologies Austria Ag Non-planar normally off compound semiconductor device
US9799726B1 (en) 2015-06-18 2017-10-24 Hrl Laboratories, Llc Vertical super junction III/nitride HEMT with vertically formed two dimensional electron gas
US9601610B1 (en) 2015-06-18 2017-03-21 Hrl Laboratories, Llc Vertical super junction III/nitride HEMT with vertically formed two dimensional electron gas
US10283633B2 (en) 2017-09-19 2019-05-07 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US10475915B2 (en) 2017-09-19 2019-11-12 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
WO2022061525A1 (en) * 2020-09-22 2022-03-31 苏州晶湛半导体有限公司 Semiconductor structure and method for manufacture thereof
CN112397586A (en) * 2020-11-23 2021-02-23 江苏大学 Normally-on silicon substrate high electron mobility transistor and manufacturing method thereof
CN112397587A (en) * 2020-11-23 2021-02-23 江苏大学 Normally-on high electron mobility transistor and manufacturing method thereof
CN112397587B (en) * 2020-11-23 2022-06-21 江苏大学 Normally-on high electron mobility transistor and manufacturing method thereof

Similar Documents

Publication Publication Date Title
JP2009099774A (en) Hetero-junction field effect transistor
JP6174874B2 (en) Semiconductor device
US10367087B2 (en) Transistor structure including a scandium gallium nitride back-barrier layer
JP5217157B2 (en) Field effect transistor and manufacturing method thereof
JP5383652B2 (en) Field effect transistor and manufacturing method thereof
JP5400266B2 (en) Field effect transistor
JP5780613B2 (en) Semiconductor device having improved adhesion and method for manufacturing the same
US8405125B2 (en) Semiconductor device and method for producing the same
KR101092467B1 (en) Enhancement normally off nitride semiconductor device and manufacturing method thereof
JP5577681B2 (en) Semiconductor device
US20100219452A1 (en) GaN HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) STRUCTURES
US9252255B2 (en) High electron mobility transistor and method of manufacturing the same
US8330187B2 (en) GaN-based field effect transistor
KR20110099546A (en) High electron mobility transistor representing dual depletion and method of manufacturing the same
US10868165B2 (en) Transistor structure with depletion-mode and enhancement mode-devices
US20150263155A1 (en) Semiconductor device
JPWO2010064706A1 (en) Semiconductor device
JP2007080855A (en) Field effect transistor
JP5134265B2 (en) Semiconductor device and manufacturing method thereof
JP6639260B2 (en) Semiconductor device
JP2007103778A (en) Field effect transistor
TWM508782U (en) Semiconductor device
JP2011108712A (en) Nitride semiconductor device
JP2010245240A (en) Heterojunction field-effect semiconductor device and method of manufacturing the same
US20190035922A1 (en) Semiconductor device, electronic part, electronic apparatus, and method for fabricating semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20100514

Free format text: JAPANESE INTERMEDIATE CODE: A621

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120710

A02 Decision of refusal

Effective date: 20121204

Free format text: JAPANESE INTERMEDIATE CODE: A02