JP2009094545A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2009094545A
JP2009094545A JP2009022023A JP2009022023A JP2009094545A JP 2009094545 A JP2009094545 A JP 2009094545A JP 2009022023 A JP2009022023 A JP 2009022023A JP 2009022023 A JP2009022023 A JP 2009022023A JP 2009094545 A JP2009094545 A JP 2009094545A
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Japan
Prior art keywords
bumps
cutting
bump
semiconductor
semiconductor substrate
Prior art date
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Granted
Application number
JP2009022023A
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Japanese (ja)
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JP4785937B2 (en
Inventor
Masataka Mizukoshi
正孝 水越
Yoshikatsu Ishizuki
義克 石月
Kanae Nakagawa
香苗 中川
Keishiro Okamoto
圭史郎 岡本
Kazuo Teshirogi
和雄 手代木
Taiji Sakai
泰治 酒井
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2009022023A priority Critical patent/JP4785937B2/en
Publication of JP2009094545A publication Critical patent/JP2009094545A/en
Application granted granted Critical
Publication of JP4785937B2 publication Critical patent/JP4785937B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To planarize surfaces of fine bumps formed on a substrate inexpensively and at high speed, and to easily and reliably connect bumps with each other without causing inconvenience such as dishing. <P>SOLUTION: A plurality of first bumps are formed on the surface of a first substrate, and a first insulating film is formed between the plurality of the first bumps. Planarization is performed by cutting using a byte so that the surfaces of the plurality of first bumps and the surface of the first insulating film become continuously planarized. A plurality of second bumps are formed on the surface of a second substrate, and a second insulating film is formed between the plurality of second bumps. The planarization is performed by cutting using the byte so that the surfaces of the plurality of second bumps and the surface of the second insulating film become continuously planarized. Then, the plurality of first bumps and the plurality of second bumps, and the first insulating film and the second insulating film are opposed to each other and connected with each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、基板の表面に外部と電気的接続を行うための微細なバンプを形成する半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device in which fine bumps for electrical connection to the outside are formed on the surface of a substrate.

従来、半導体基板の表面で外部と電気的接続を行うため微細な金属端子には、金（Ａｕ
）バンプ等が用いられている。このＡｕバンプはメッキで形成されており、表面の粗さが大きい。このような金属端子を平坦化するためには、化学機械研磨（Chemical Mechanical Polishing：ＣＭＰ）法が用いられている。この方法は、被加工面となる金属及び樹脂を予め比較的平坦に形成し、平坦な研磨パッドを押し当て、スラリー（化学的研磨材）を用いて化学的・機械的に表面を精緻に平坦加工するものである。予め設けられた硬い樹脂や金属面がストップ層となり、ＣＭＰは完了する。ＣＭＰ法は、半導体基板の厚みのばらつきや半導体基板の最大厚みと最小厚みとの差で定義されるＴＴＶ（Total Thickness Variation）には依存しない方法である。 Conventionally, gold (Au) is used as a fine metal terminal for electrical connection to the outside on the surface of a semiconductor substrate.
) Bumps are used. The Au bump is formed by plating and has a large surface roughness. In order to planarize such a metal terminal, a chemical mechanical polishing (CMP) method is used. In this method, a metal and a resin to be processed are formed in a relatively flat state in advance, a flat polishing pad is pressed against the surface, and the surface is precisely and mechanically flattened using a slurry (chemical abrasive). To be processed. The hard resin or metal surface provided in advance serves as a stop layer, and CMP is completed. The CMP method is a method that does not depend on TTV (Total Thickness Variation) defined by the variation in the thickness of the semiconductor substrate or the difference between the maximum thickness and the minimum thickness of the semiconductor substrate.

また、従来の表面の粗さが大きいＡｕバンプ等の接合には、その粗さが無くなるまで、荷重、熱、あるいは超音波等によりバンプへ負荷を与える実装方法が必要である。   In addition, the conventional bonding of Au bumps or the like having a large surface roughness requires a mounting method in which a load is applied to the bumps by a load, heat, ultrasonic waves, or the like until the roughness is eliminated.

ＣＭＰ以外でも、例えば切削工具を用いた平坦化方法がいくつか案出されている（例えば特許文献１〜４参照）。しかしながら、いずれもＬＳＩ上における部分領域のＳＯＧ膜の平坦化を対象としたものであり、ＣＭＰと同様、被切削面を基準として切削する方法であって半導体基板のＴＴＶには依存しない。また、バンプを切削して表面を露出させる方法（特許文献４参照）もあるが、これはＬＳＩ上に形成されたバンプ部分の平坦化を対象としており、被切削面を基準として切削する方法であって、半導体基板のＴＴＶには依存しない。   In addition to CMP, for example, several planarization methods using a cutting tool have been devised (see, for example, Patent Documents 1 to 4). However, both are intended for flattening the SOG film in a partial region on the LSI, and, like CMP, are methods based on the surface to be cut and do not depend on the TTV of the semiconductor substrate. There is also a method of exposing the surface by cutting the bump (see Patent Document 4), but this is intended for flattening the bump portion formed on the LSI, and is a method of cutting based on the surface to be cut. Thus, it does not depend on the TTV of the semiconductor substrate.

特開平７−３２６６１４号公報JP 7-326614 A 特開平８−１１０４９号公報JP-A-8-11049 特開平９−８２６１６号公報Japanese Patent Laid-Open No. 9-82616 特開２０００−１７３９５４号公報Japanese Patent Application Laid-Open No. 2000-173954

上述のように、微細な接続にはＡｕバンプが用いられているが、バンプ表面の粗さが大きいことで、それらのバンプ同士を接合するのは困難である。また、Ａｕなどの金属と樹脂を同時にＣＭＰを用いて平坦化する場合、金属と樹脂の研磨速度の違いに起因してディッシングと呼ばれる窪みが現れる。このディッシングにより、確実なバンプ接合を得るために、荷重、熱、あるいは超音波等の大きな負荷をバンプに与えることを要する。   As described above, Au bumps are used for fine connection, but it is difficult to join the bumps due to the large roughness of the bump surface. In addition, when a metal such as Au and a resin are simultaneously planarized using CMP, a recess called dishing appears due to a difference in polishing rate between the metal and the resin. In order to obtain reliable bump bonding by this dishing, it is necessary to apply a large load such as a load, heat, or ultrasonic waves to the bump.

本発明は、上記の課題に鑑みてなされたものであり、ＣＭＰに替わり、基板上に形成された微細なバンプの表面を安価に高速で平坦化し、バンプ同士の接続を、ディッシング等の不都合を発生させることなく容易且つ確実に行うことを可能とする半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of the above problems, and instead of CMP, the surface of fine bumps formed on a substrate is flattened at low speed and at high speed, and the bumps are connected with each other with inconvenience such as dishing. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be easily and reliably performed without generating the semiconductor device.

本発明の半導体装置の製造方法は、第１の基板の表面に、複数の第１のバンプを形成する工程と、前記複数の第１のバンプ間に第１の絶縁膜を形成する工程と、バイトを用いた切削加工により、前記複数の第１のバンプの表面及び前記第１の絶縁膜の表面が連続して平坦となるように平坦化処理する工程と、第２の基板の表面に、複数の第２のバンプを形成する工程と、前記複数の第２のバンプ間に第２の絶縁膜を形成する工程と、バイトを用いた切削加工により、前記複数の第２のバンプの表面及び前記第２の絶縁膜の表面が連続して平坦となるように平坦化処理する工程と、前記複数の第１のバンプと前記複数の第２のバンプ、及び、前記第１の絶縁膜と前記第２の絶縁膜を対向させて、それぞれを接続する工程とを含む。   The method for manufacturing a semiconductor device of the present invention includes a step of forming a plurality of first bumps on a surface of a first substrate, a step of forming a first insulating film between the plurality of first bumps, By a cutting process using a cutting tool, a step of flattening so that the surfaces of the plurality of first bumps and the surface of the first insulating film are continuously flat, and the surface of the second substrate, A step of forming a plurality of second bumps, a step of forming a second insulating film between the plurality of second bumps, a cutting process using a cutting tool, and a surface of the plurality of second bumps; A step of planarizing the surface of the second insulating film so as to be continuously flat, the plurality of first bumps, the plurality of second bumps, and the first insulating film; And a step of connecting each of the second insulating films to face each other.

本発明の半導体装置の製造方法は、第１の基板の表面に、複数の第１のバンプを形成する工程と、バイトを用いた切削加工により、前記複数の第１のバンプの表面が連続して平坦となるように平坦化処理する工程と、第２の基板の表面に、複数の第２のバンプを形成する工程と、バイトを用いた切削加工により、前記複数の第２のバンプの表面が連続して平坦となるように平坦化処理する工程と、前記第１の基板及び前記複数の第１のハンプ上に、導電性微粒子を含有する絶縁膜を形成する工程と、前記複数の第１のバンプと前記複数の第２のハンプとを前記導電性微粒子を含有する絶縁膜を介して対向させ、それぞれを接続する工程とを含む。   In the method of manufacturing a semiconductor device according to the present invention, the surface of the plurality of first bumps is continuously formed by a step of forming the plurality of first bumps on the surface of the first substrate and a cutting process using a cutting tool. The surface of the plurality of second bumps is formed by a flattening process so as to be flat, a step of forming a plurality of second bumps on the surface of the second substrate, and a cutting process using a cutting tool. Flattening process so as to be continuously flat, forming an insulating film containing conductive fine particles on the first substrate and the plurality of first humps, and And a step of making one bump and the plurality of second humps face each other through an insulating film containing the conductive fine particles, and connecting each of them.

本発明によれば、ＣＭＰに替わり、基板上に形成された微細なバンプの表面を安価に高速で平坦化し、バンプ同士の接続を、ディッシング等の不都合を発生させることなく容易且つ確実に行うことが可能となる。   According to the present invention, instead of CMP, the surface of fine bumps formed on a substrate is flattened inexpensively and at high speed, and the bumps are connected easily and reliably without causing problems such as dishing. Is possible.

図１Ａは、第１の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 1A is a schematic cross-sectional view showing a bump forming method according to the first embodiment in the order of steps. 図１Ｂは、第１の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 1B is a schematic cross-sectional view showing the bump forming method according to the first embodiment in the order of steps. 図１Ｃは、第１の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 1C is a schematic cross-sectional view showing a bump forming method according to the first embodiment in the order of steps. 図１Ｄは、第１の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 1D is a schematic cross-sectional view showing the bump forming method according to the first embodiment in the order of steps. 図２Ａは、第１の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 2A is a schematic cross-sectional view showing a bump forming method according to the first embodiment in the order of steps. 図２Ｂは、第１の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 2B is a schematic cross-sectional view illustrating the bump forming method according to the first embodiment in the order of steps. 図３Ａは、切削加工による平坦化の結果を示す図である。FIG. 3A is a diagram illustrating a result of flattening by cutting. 図３Ｂは、切削加工による平坦化の結果を示す図である。FIG. 3B is a diagram illustrating a result of flattening by cutting. 図４Ａは、切削加工による平坦化の具体例を示す概略断面図である。FIG. 4A is a schematic cross-sectional view showing a specific example of flattening by cutting. 図４Ｂは、切削加工による平坦化の具体例を示す概略断面図である。FIG. 4B is a schematic cross-sectional view showing a specific example of flattening by cutting. 図５は、切削加工による平坦化の具体例を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing a specific example of flattening by cutting. 図６は、切削加工装置の構成を表したブロック図である。FIG. 6 is a block diagram showing the configuration of the cutting apparatus. 図７は、切削加工装置の概略構成図である。FIG. 7 is a schematic configuration diagram of the cutting apparatus. 図８は、切削加工工程のフロー図である。FIG. 8 is a flowchart of the cutting process. 図９Ａは、第２の実施形態による半導体装置の製造方法を工程順に示す概略平面図である。FIG. 9A is a schematic plan view illustrating the manufacturing method of the semiconductor device according to the second embodiment in the order of steps. 図９Ｂは、第２の実施形態による半導体装置の製造方法を工程順に示す概略平面図である。FIG. 9B is a schematic plan view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. 図９Ｃは、第２の実施形態による半導体装置の製造方法を工程順に示す概略平面図である。FIG. 9C is a schematic plan view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. 図１０Ａは、第２の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 10A is a schematic cross-sectional view showing a bump forming method according to the second embodiment in the order of steps. 図１０Ｂは、第２の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 10B is a schematic cross-sectional view showing the bump forming method according to the second embodiment in the order of steps. 図１０Ｃは、第２の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 10C is a schematic cross-sectional view showing the bump forming method according to the second embodiment in the order of steps. 図１０Ｄは、第２の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 10D is a schematic cross-sectional view illustrating the bump forming method according to the second embodiment in the order of steps. 図１０Ｅは、第２の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 10E is a schematic cross-sectional view showing the bump forming method according to the second embodiment in the order of steps. 図１０Ｆは、第２の実施形態によるバンプの形成方法を工程順に示す概略断面図である。FIG. 10F is a schematic cross-sectional view showing the bump forming method according to the second embodiment in the order of steps. 図１１Ａは、第３の実施形態による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 11A is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps. 図１１Ｂは、第３の実施形態による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 11B is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps. 図１２Ａは、第３の実施形態の変形例１による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 12A is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first modification of the third embodiment in the order of steps. 図１２Ｂは、第３の実施形態の変形例１による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 12B is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first modification of the third embodiment in the order of steps. 図１２Ｃは、第３の実施形態の変形例１による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 12C is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first modification of the third embodiment in the order of steps. 図１３Ａは、第３の実施形態の変形例２による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 13A is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second modification of the third embodiment in the order of steps. 図１３Ｂは、第３の実施形態の変形例２による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 13B is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second modification of the third embodiment in the order of steps. 図１３Ｃは、第３の実施形態の変形例２による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 13C is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second modification of the third embodiment in the order of steps. 図１４Ａは、第４の実施形態による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 14A is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. 図１４Ｂは、第４の実施形態による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 14B is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. 図１４Ｃは、第４の実施形態による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 14C is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. 図１４Ｄは、第４の実施形態による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 14D is a schematic sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. 図１４Ｅは、第４の実施形態による半導体装置の製造方法を工程順に示す概略断面図である。FIG. 14E is a schematic sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. 図１４Ｆは、第４の実施形態による半導体装置の製造方法を工程順に示概略断面図である。FIG. 14F is a schematic sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. 図１５Ａは、第４の実施形態による切削終点検出方法を示す図である。FIG. 15A is a diagram illustrating a cutting end point detection method according to a fourth embodiment. 図１５Ｂは、第４の実施形態による切削終点検出方法を示す図である。FIG. 15B is a diagram illustrating a cutting end point detection method according to the fourth embodiment. 図１５Ｃは、第４の実施形態による切削終点検出方法を示す図である。FIG. 15C is a diagram illustrating a cutting end point detection method according to the fourth embodiment. 図１５Ｄは、第４の実施形態による切削終点検出方法を示す図である。FIG. 15D is a diagram illustrating a cutting end point detection method according to the fourth embodiment. 図１６は、第５の実施形態半導体装置の製造方法を示す概略断面図である。FIG. 16 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the fifth embodiment. 図１７は、第５の実施形態半導体装置の製造方法を示す概略断面図である。FIG. 17 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the fifth embodiment. 図１８は、第６の実施形態による半導体製造装置を示す模式図である。FIG. 18 is a schematic view showing a semiconductor manufacturing apparatus according to the sixth embodiment.

−本発明の基本骨子−
初めに、本発明の基本骨子について説明する。
本発明者は、ＣＭＰ法に替わり、基板上に形成された多数の微細バンプの表面を安価に高速で一斉に平坦化する手法として、バイトを用いた切削加工を適用することに想到した。
この切削加工によれば、半導体基板上で絶縁膜内にバンプが埋め込み形成されているような場合でも、ＣＭＰ法のように金属と絶縁物の研磨速度等に依存することなく、基板上で一斉に金属と絶縁物を連続して切削し、ディッシング等を発生せしめることなく全体的に両者を均一に平坦化することができる。銅、アルミニウム、ニッケル等の金属やポリイミド等の絶縁材料は、容易にバイトで切削可能な材料である。本発明では、バンプの金属材料及び絶縁材料としては、前者が延性金属であり、後者が例えば２００ＧＰａ以上の剛性率を有する樹脂等であれば、好適である。 -Basic outline of the present invention-
First, the basic outline of the present invention will be described.
The present inventor has come up with the idea of applying cutting using a cutting tool as a technique for simultaneously flattening the surface of a large number of fine bumps formed on a substrate at a low cost and at a high speed instead of the CMP method.
According to this cutting process, even when a bump is embedded in an insulating film on a semiconductor substrate, it does not depend on the polishing rate of the metal and the insulator as in the CMP method, and can be performed simultaneously on the substrate. In addition, the metal and the insulator can be continuously cut, and both can be uniformly flattened without causing dishing or the like. Metals such as copper, aluminum, and nickel, and insulating materials such as polyimide are materials that can be easily cut with a cutting tool. In the present invention, as the metal material and insulating material of the bump, it is preferable that the former is a ductile metal and the latter is a resin having a rigidity of, for example, 200 GPa or more.

この場合、上述の切削加工をバンプ表面の平坦化に利用するためには、切削を基板の背面（裏面）基準で行うことが好適である。一般的に、シリコン基板のＴＴＶは、１μｍ〜５μｍの範囲内にあり、ＬＳＩのプロセスでは５μｍ程度のＴＴＶはフォトリソグラフィーに影響を与えることはなく、通常では考慮の対象外となる。しかしながら、切削加工の場合ではＴＴＶの値に大きく影響される。切削による平坦精度はＴＴＶの値以下にはならない。従って、切削加工を半導体基板の平坦化に用いる場合には、基板のＴＴＶを目標の切削精度以下に制御することが先ず必要になる。   In this case, in order to use the above-described cutting process for the flattening of the bump surface, it is preferable to perform the cutting on the basis of the back surface (back surface) of the substrate. In general, the TTV of a silicon substrate is in the range of 1 μm to 5 μm. In the LSI process, a TTV of about 5 μm does not affect photolithography and is usually not considered. However, in the case of cutting, it is greatly influenced by the value of TTV. Flatness accuracy by cutting does not fall below the TTV value. Therefore, when cutting is used for flattening a semiconductor substrate, it is first necessary to control the TTV of the substrate to a target cutting accuracy or less.

本発明者は、上記の事情を勘案し、上述の切削加工をバンプ表面の平坦化に利用するに際して、当該平坦化を確実に行う具体的手法として、基板表面を基準にその裏面を研削し、半導体基板のＴＴＶを目的とする切削精度以下に小さく抑えることに想到した。この場合、ＴＴＶを小さくして且つ個々の半導体基板の厚みばらつきも切削精度以下に抑えることが理想的である。しかしながら、ＴＴＶさえ小さくできれば、個々の半導体基板の厚みについては切削時に検出可能である。切削量は、この個々の半導体基板の厚みを検出することにより制御可能である。   In consideration of the above circumstances, the present inventor, when using the above-described cutting process for the flattening of the bump surface, as a specific method for reliably performing the flattening, grinding the back surface with respect to the substrate surface, The inventors have conceived that the TTV of the semiconductor substrate is kept below the target cutting accuracy. In this case, it is ideal that the TTV is made small and the thickness variation of each semiconductor substrate is suppressed to below the cutting accuracy. However, as long as the TTV can be reduced, the thickness of each semiconductor substrate can be detected during cutting. The cutting amount can be controlled by detecting the thickness of each individual semiconductor substrate.

バンプとしては、メッキ法により形成されるものの他、ワイヤボンディング法、即ちボンディングワイヤの先端を溶融して形成したボール状の塊を電極パッド上に圧着し、当該ワイヤを引きちぎることにより形成されたバンプ（以下、スタッドバンプと称する。）
がある。 In addition to the bumps formed by plating, the bumps are formed by wire bonding, that is, bumps formed by melting the tip of the bonding wire on the electrode pad and tearing the wire. (Hereinafter referred to as stud bump)
There is.

スタッドバンプを形成する場合、ボンディングワイヤの引きちぎりにより、ピン状の突起が形成されるため、かかる突起を平坦化する必要がある。本発明では、上述の切削加工による平坦化法をスタッドバンプにも適用する。この場合、ワイヤの引きちぎり（プレカット）時には各突起部の高さが異なり、最も低いバンプに揃えて平坦化することになるが、スタッドバンプの高さは高いほどデバイスへの応力を緩和し、デバイス寿命を延ばすことが可能であるため、各突起部の高さを規定することが必要である。本発明では、プレカット時の突起部の電極パッドからの高さをワイヤ径の２倍以上に規定し、切削加工の終点として、全てのスタッドバンプについて、切削面の径がワイヤ径と同等以上になった時点とする。これにより、切削平坦化後におけるスタッドバンプの高さを、ワイヤ径を規定しない場合に比べて１．５倍以上とすることができ、半導体素子への応力を緩和することが可能となり、デバイス寿命を延ばすことが可能となる。   When the stud bump is formed, a pin-shaped protrusion is formed by tearing of the bonding wire, and it is necessary to flatten the protrusion. In the present invention, the above-described flattening method by cutting is also applied to the stud bump. In this case, when the wire is torn (pre-cut), the height of each projection is different and flattened to align with the lowest bump, but the higher the stud bump height, the less stress on the device, Since the device life can be extended, it is necessary to define the height of each protrusion. In the present invention, the height from the electrode pad of the protruding portion at the time of pre-cut is specified to be twice or more of the wire diameter, and the cutting surface diameter is equal to or more than the wire diameter for all stud bumps as the end point of the cutting process. It becomes the time when it became. As a result, the height of the stud bump after the flattening of cutting can be made 1.5 times or more compared to the case where the wire diameter is not specified, and the stress on the semiconductor element can be relaxed, and the device life Can be extended.

そして、上述のようにＴＴＶを制御し、切削加工により微細なバンプの表面を平坦化した後、半導体基板（ウェーハ）から半導体部品となる個々の半導体チップを切り出す。しかる後、平坦化された表面を有する半導体基板と半導体チップ、又は半導体チップ同士を、バンプを対向させて電気的に接続して接合する。このとき、対向するバンプの上面が共に高精度に平坦化されているため、従来のように高温・高圧等を要することなく容易に接合される。   And after controlling TTV as mentioned above and planarizing the surface of a fine bump by cutting, each semiconductor chip used as a semiconductor component is cut out from a semiconductor substrate (wafer). Thereafter, the semiconductor substrate having a planarized surface and the semiconductor chip, or the semiconductor chips are electrically connected with the bumps facing each other and bonded. At this time, since the upper surfaces of the opposing bumps are both flattened with high precision, they can be easily joined without requiring high temperature and high pressure as in the prior art.

ここで、本発明者は更に、対向するバンプ同士の接合を確実に実現するための具体的条件・状態を模索した。上述の接合時にもバンプを切削加工直後の平坦化状態に保つことが理想的であることに鑑み、切削加工直後の平坦化状態を可及的に保持するため、平坦化工程と接合工程を共に清浄化雰囲気、具体的には不活性雰囲気内で行うことに想到した。この点、接合工程の直前にＡｒプラズマ等を用いた清浄化工程を付加することで対処することもできるが、工程数の増加を招くという欠点がある。本発明では、工程数の増加を招くことなく比較的容易に理想に極めて近い平坦化状態を維持することができ、バンプの確実な接合が可能となる。   Here, the inventor further sought specific conditions and states for reliably realizing the bonding between the bumps facing each other. Considering that it is ideal to keep the bumps in the flattened state immediately after the cutting process even during the above-mentioned bonding, both the flattening process and the bonding process are performed in order to keep the flattened state immediately after the cutting process as much as possible. It was conceived to carry out in a cleaning atmosphere, specifically in an inert atmosphere. Although this point can be dealt with by adding a cleaning step using Ar plasma or the like immediately before the bonding step, there is a drawback that the number of steps increases. In the present invention, a planarized state that is extremely close to the ideal can be maintained relatively easily without causing an increase in the number of steps, and the bumps can be reliably bonded.

本発明者は、本発明の他の態様として、この半導体チップの状態に着目する。即ち、ウェーハレベルでは、上述のように当該半導体基板のＴＴＶが問題となるが、半導体チップなどの個片化されたものについては、そのサイズが小さいためにチップエリア内におけるＴＴＶは、切削時には殆ど無視できる程度の影響しか受けない。   The inventor pays attention to the state of the semiconductor chip as another aspect of the present invention. In other words, at the wafer level, the TTV of the semiconductor substrate becomes a problem as described above. However, since the size of individual chips such as semiconductor chips is small, the TTV in the chip area is almost not at the time of cutting. Only a negligible influence is received.

そこで本発明者は、先ず半導体基板から各半導体チップを切り出した後、この半導体チップの状態で上述のバンプを用いた切削加工により微細なバンプの表面を平坦化することに想到した。そして、半導体チップ同士を、バンプを対向させて電気的に接続して接合する。これにより、ＴＴＶを制御する工程を省略できるとともに、容易にバンプ接合を行うことが可能となる。   Therefore, the present inventor has first conceived that after cutting each semiconductor chip from the semiconductor substrate, the surface of the fine bump is flattened by cutting using the above-described bump in the state of the semiconductor chip. Then, the semiconductor chips are joined by electrically connecting the bumps to each other. Thereby, the step of controlling the TTV can be omitted and the bump bonding can be easily performed.

また本発明では、上述した切削加工技術を、いわゆるＴＡＢボンディング法による半導体装置にも適用する。
通常、ＴＡＢ接続は、メッキバンプ法による場合では、金メッキバンプに直接に金の表面処理を施された短冊状の銅箔リードを位置合わせして３００℃以上に加熱し、１つのバンプ当たり３０ｇ以上の加圧圧着を必要とする。他方、スタッドバンプ法にいる場合では、予めスタッドバンプの形成された半導体チップを、ガラス板又は金属板に押し当て加熱し、スタッドバンプ先端を平坦に加工して用いることが必要である。 In the present invention, the above-described cutting technique is also applied to a semiconductor device using a so-called TAB bonding method.
Normally, when the TAB connection is based on the plating bump method, a strip-shaped copper foil lead subjected to gold surface treatment directly on the gold plating bump is aligned and heated to 300 ° C. or higher, and 30 g or more per bump. Requires pressure bonding. On the other hand, in the case of the stud bump method, it is necessary to heat a semiconductor chip on which a stud bump has been formed in advance by pressing it against a glass plate or a metal plate and processing the tip of the stud bump flatly.

メッキ終端面には、凹凸や表面に特有の金属的及び有機的汚染がある。また、チップ内でのメッキ高さのばらつきも数ミクロンのレベルで発生している。これらのメッキ終端面にＴＡＢボンディングする場合、高温と高荷重が必要になる。ボンディング時に高温になると微細なピッチのリードの接続では、銅とシリコンの熱膨張率の差が大きくなるため位置ずれが発生し易い。他方、スタッドバンプにおいては、高さにバラツキが大きく、形状も一定でないことから更に高温及び高荷重が必要であり、同様に微細ピッチの接続は難しい。   The plating end surface has irregularities and metallic and organic contamination peculiar to the surface. In addition, variations in the plating height within the chip occur at a level of several microns. When TAB bonding is performed on these plating end faces, high temperature and high load are required. When a high temperature is used during bonding, a difference in the thermal expansion coefficient between copper and silicon becomes large in connecting fine pitch leads, and thus misalignment is likely to occur. On the other hand, the stud bump has a large variation in height and the shape thereof is not constant, so that a higher temperature and a higher load are required, and it is difficult to connect fine pitches.

ＴＡＢボンディング時の位置ずれを小さくするためには、温度を下げるとともに、銅のリード端子が同時にバンプに接触することが必要である。本発明では、バイトによる切削技術を用いメッキバンプ及びスタッドバンプの表面を切削加工により平坦化して清浄化を図り、これによりＴＡＢボンディング時の温度及び荷重を低減させ、微細ピッチのリードを位置ずれなく接続することが可能となる。   In order to reduce misalignment during TAB bonding, it is necessary to lower the temperature and simultaneously contact the copper lead terminals with the bumps. In the present invention, the surface of the plating bump and the stud bump is flattened by cutting using a cutting technique using a cutting tool, thereby reducing the temperature and load at the time of TAB bonding, and the fine pitch lead is not displaced. It becomes possible to connect.

−本発明の具体的な実施形態−
以下、上述した基本骨子を踏まえ、本発明の具体的な諸実施形態について図面を用いて詳細に説明する。 -Specific embodiment of the present invention-
Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings based on the basic outline described above.

［第１の実施形態］
ここでは、基板としてシリコン半導体基板を例示し、この半導体基板上に外部と電気的接続を行うために設けられてなるバンプを形成する方法及びこの方法を用いた半導体装置及びその製造方法について開示する。 [First Embodiment]
Here, a silicon semiconductor substrate is exemplified as the substrate, and a method of forming bumps provided on the semiconductor substrate for electrical connection with the outside, a semiconductor device using the method, and a method of manufacturing the same are disclosed. .

（バンプの形成方法）
図１Ａ〜図１Ｄ，図２Ａ，図２Ｂは、本実施形態によるバンプの形成方法を工程順に示す概略断面図である。 (Bump formation method)
1A to 1D, 2A, and 2B are schematic cross-sectional views illustrating the bump forming method according to the present embodiment in the order of steps.

先ず、シリコン半導体基板１を用意し、基板表面１ａの素子形成部位に所望のＬＳＩ半導体素子（不図示）を形成する。このように、素子形成部位にＬＳＩ半導体素子等の形成された半導体基板１について、以下で各工程を説明する。   First, a silicon semiconductor substrate 1 is prepared, and a desired LSI semiconductor element (not shown) is formed at an element formation site on the substrate surface 1a. Each step of the semiconductor substrate 1 on which the LSI semiconductor element or the like is formed in the element formation site will be described below.

図１Ａに示すように、通常、シリコン半導体基板は、図示の如く厚みが一様ではなく、しかもうねりを伴う状態にある。そこで、半導体基板１の表面１ａに後述するバイトを用いた切削加工を施すための前工程として、その裏面１ｂを平坦化する。   As shown in FIG. 1A, normally, the silicon semiconductor substrate is not uniform in thickness as shown in the figure, but is in a state accompanied by waviness. Therefore, the back surface 1b is flattened as a pre-process for cutting the surface 1a of the semiconductor substrate 1 using a cutting tool which will be described later.

具体的には、支持面が平坦とされた基板支持台（不図示）を用意し、この支持面に吸着、例えば真空吸着により表面１ａを吸着させて半導体基板１を基板支持台に固定する。このとき、表面１ａは支持面への吸着により強制的に平坦とされており、これにより表面１ａが裏面１ｂの平坦化の基準面となる。この状態で、裏面１ｂを機械加工、ここでは機械研削し、裏面１ｂの凸部１ｃを研削除去して平坦化処理する。この場合、裏面１ｂの切削量を表面１ａからの距離により制御することが好ましい。これにより、図１Ｂに示すように、半導体基板１の厚みが一定、具体的にはＴＴＶ（基板の最大厚みと最小厚みとの差）が所定値以下となるように、具体的にはＴＴＶが１μｍ以下に制御されることになる。   Specifically, a substrate support base (not shown) having a flat support surface is prepared, and the semiconductor substrate 1 is fixed to the substrate support base by adsorbing the surface 1a to the support surface by, for example, vacuum adsorption. At this time, the surface 1a is forcibly flattened by adsorption to the support surface, and thus the surface 1a becomes a reference surface for flattening the back surface 1b. In this state, the back surface 1b is machined, here, mechanically ground, and the convex portion 1c of the back surface 1b is removed by grinding and flattened. In this case, it is preferable to control the cutting amount of the back surface 1b by the distance from the front surface 1a. As a result, as shown in FIG. 1B, the thickness of the semiconductor substrate 1 is constant, specifically, TTV (specifically, the difference between the maximum thickness and the minimum thickness of the substrate) is a predetermined value or less. It is controlled to 1 μm or less.

続いて、図１Ｃに示すように、半導体基板１を基板支持台から外し、半導体基板１の表面１ａ上に感光性樹脂、例えばフォトレジストを塗布し、このフォトレジストをフォトリソグラフィーにより加工して、所定のバンプパターン１２ａを有するレジストマスク１２を形成する。   Subsequently, as shown in FIG. 1C, the semiconductor substrate 1 is removed from the substrate support, a photosensitive resin, for example, a photoresist is applied onto the surface 1a of the semiconductor substrate 1, and the photoresist is processed by photolithography. A resist mask 12 having a predetermined bump pattern 12a is formed.

続いて、レジストマスク１２をマスクとして用い、例えば蒸着法により金属、例えば銅膜を形成し、メッキ電極（不図示）を形成した後、図１Ｄに示すように、メッキ電極をシードとしてメッキ法によりレジストマスク１２の各バンプパターン１２ａを埋め込むように金（Ａｕ）を堆積させ、Ａｕ突起２を形成する。なお、Ａｕ以外にもＣｕ，Ａｇ，Ｎｉ，Ｓｎ又はこれらの合金等を用いて突起を形成しても良い。   Subsequently, using the resist mask 12 as a mask, for example, a metal, for example, a copper film is formed by an evaporation method, and a plating electrode (not shown) is formed. Then, as shown in FIG. Gold (Au) is deposited so as to embed each bump pattern 12a of the resist mask 12, and Au protrusions 2 are formed. In addition, you may form a protrusion using Cu, Ag, Ni, Sn or these alloys other than Au.

続いて、半導体基板１の表面１ａにバイトを用いた切削加工を施し、平坦化する。
具体的には、図２Ａに示すように、基板支持台１１の支持面１１ａに例えば真空吸着により裏面１ｂを吸着させ、半導体基板１を基板支持台１１に固定する。このとき、裏面１ｂへの図１Ｂの平坦化処理により半導体基板１の厚みが一定の状態とされており、更に裏面１ｂが支持面１１ａへの吸着により強制的にうねり等もない状態となり、これにより裏面１ｂが表面１ａの平坦化の基準面となる。この状態で、表面１ａにおける各Ａｕ突起２及びフォトレジスト１２の表層を機械加工、ここではダイヤモンド等からなるバイト１０を用いて切削加工し、各Ａｕ突起２及びレジストマスク１２の表面が連続して平坦となるように平坦化処理する。これにより、Ａｕ突起２の上面が鏡面状に平坦化される。 Subsequently, the surface 1a of the semiconductor substrate 1 is subjected to a cutting process using a cutting tool and flattened.
Specifically, as shown in FIG. 2A, the back surface 1 b is adsorbed to the support surface 11 a of the substrate support table 11 by, for example, vacuum adsorption, and the semiconductor substrate 1 is fixed to the substrate support table 11. At this time, the thickness of the semiconductor substrate 1 is made constant by the flattening process of FIG. 1B on the back surface 1b, and the back surface 1b is not forcedly swelled by adsorption to the support surface 11a. Thus, the back surface 1b becomes a reference surface for flattening the front surface 1a. In this state, the surface layer of each Au protrusion 2 and the photoresist 12 on the surface 1a is machined, in this case using a cutting tool 10 made of diamond or the like, and the surface of each Au protrusion 2 and the resist mask 12 is continuously formed. A flattening process is performed so as to be flat. Thereby, the upper surface of the Au protrusion 2 is flattened into a mirror surface.

この切削加工による平坦化の結果を図３Ａ，図３Ｂの顕微鏡写真の図及び模式図に示す。
切削加工前には、図３ＡのようにＡｕ突起の表面は凹凸状であったのに対して、切削加工後には、図３Ｂに示すように、Ａｕ突起の表面が高精度に平坦化されていることが判る。 The results of planarization by this cutting process are shown in the micrographs and schematic diagrams of FIGS. 3A and 3B.
Before cutting, the surface of the Au protrusion was uneven as shown in FIG. 3A, whereas after cutting, the surface of the Au protrusion was flattened with high accuracy as shown in FIG. 3B. I know that.

続いて、図２Ｂに示すように、レジストマスク１２を灰化処理等により除去する。このとき、半導体基板１の表面１ａ上には、高さが均一であり、各Ａｕ突起２が切削加工されて上面３ａが一様に平坦化されてなるバンプ３が形成される。この半導体基板１を用い、例えばこれをチップ化した後、他の半導体基板４とバンプ３により電気的に接続する。   Subsequently, as shown in FIG. 2B, the resist mask 12 is removed by ashing or the like. At this time, on the surface 1 a of the semiconductor substrate 1, bumps 3 having a uniform height, each Au protrusion 2 being cut, and the upper surface 3 a being uniformly flattened are formed. Using this semiconductor substrate 1, for example, after making it into a chip, it is electrically connected to another semiconductor substrate 4 by bumps 3.

なお、本実施形態では、１枚の半導体基板について説明したが、ロットを構成する複数の半導体基板について本実施形態の各工程を実行し、各半導体基板の厚みを同一に均一化することが好適である。   In the present embodiment, a single semiconductor substrate has been described. However, it is preferable that the steps of the present embodiment be performed on a plurality of semiconductor substrates constituting a lot so that the thickness of each semiconductor substrate is made uniform. It is.

また、図２Ａの平坦化工程において、図４Ａ，図４Ｂに示すように、裏面１ｂを基準に半導体基板１の平行出しを行うとともに、表面１ａの位置を検出し、検出された表面１ａから削り量を算出して制御する。   Further, in the planarization process of FIG. 2A, as shown in FIGS. 4A and 4B, the semiconductor substrate 1 is parallelized with reference to the back surface 1b, and the position of the front surface 1a is detected and shaved from the detected front surface 1a. Calculate and control the amount.

具体的には、図４Ａに示すように、表面１ａの位置を検出する際に、半導体基板１の表面１ａの周辺部位の複数箇所、ここでは例えば図４Ｂに示す３箇所Ａ，Ｂ，Ｃにおけるレジストマスク１２にレーザ光１３を照射し、これらを加熱飛散させ、表面１ａの一部を露出させることが好適である。   Specifically, as shown in FIG. 4A, when detecting the position of the surface 1a, a plurality of locations around the surface 1a of the semiconductor substrate 1, for example, three locations A, B, and C shown in FIG. It is preferable to irradiate the resist mask 12 with the laser beam 13 to heat and scatter these to expose a part of the surface 1a.

またこの場合、図５に示すように、表面１ａの位置を検出する際に、半導体基板１を開口１１ｂの形成された基板支持台１１に吸着固定し、開口１１ｂから裏面１ｂに赤外レーザ光を照射して、表面１ａからの反射光を例えば赤外レーザ測定器１４により測定するようにしても良い。   Further, in this case, as shown in FIG. 5, when detecting the position of the front surface 1a, the semiconductor substrate 1 is adsorbed and fixed to the substrate support 11 on which the opening 11b is formed, and infrared laser light is applied from the opening 11b to the back surface 1b. The reflected light from the surface 1a may be measured by, for example, the infrared laser measuring device 14.

（切削加工装置の構成）
ここで、上述した切削加工工程を実行するための具体的な装置構成を説明する。
図６は切削加工装置の構成を表したブロック図、図７は同様の概略構成図である。この切削加工装置は、半導体基板を収納する収納部１０１、半導体基板１を各処理部へ搬送するためのハンド部１０２、半導体基板１の位置決めを行うセンシング部１０３、切削時の半導体基板１をチャックするチャックテーブル部１０４、半導体基板１の平坦化切削を行う切削部１０５、切削後の洗浄を行う洗浄部１０６、そしてこれらをコントロールする制御部１０７を有して構成されている。チャックテーブル部１０４は、上述したように半導体基板１を載置固定する基板支持台（チャックテーブル）１１を構成しており、切削部１０５はダイヤモンド等からなる切削工具である硬質のバイト１０を有している。 (Configuration of cutting device)
Here, the specific apparatus structure for performing the cutting process mentioned above is demonstrated.
FIG. 6 is a block diagram showing the configuration of the cutting apparatus, and FIG. 7 is a similar schematic configuration diagram. The cutting apparatus includes a storage unit 101 for storing a semiconductor substrate, a hand unit 102 for transporting the semiconductor substrate 1 to each processing unit, a sensing unit 103 for positioning the semiconductor substrate 1, and a chuck for the semiconductor substrate 1 at the time of cutting. A chuck table 104, a cutting unit 105 for performing flattening cutting of the semiconductor substrate 1, a cleaning unit 106 for performing cleaning after cutting, and a control unit 107 for controlling them. As described above, the chuck table portion 104 constitutes the substrate support (chuck table) 11 on which the semiconductor substrate 1 is placed and fixed, and the cutting portion 105 has a hard bit 10 that is a cutting tool made of diamond or the like. is doing.

次に、切削加工工程のフローについて、図７及び図８を用いて説明する。
先ず、半導体基板１が収納された収納部１０１の収納カセット１１１から、ハンド部１０２の搬送ハンドが半導体基板１を取り出す。収納部１０１にはエレベータ機構があり、搬送ハンドの半導体基板１の取り出し高さまで昇降する。次に搬送ハンドが半導体基板をバキューム吸着し、センシング部１０３へ搬送する。搬送ハンドは、Θ３軸とＺ軸のスカラー型ロボットになっており、各処理部へ容易にハンドリングすることができる。ロボットの機構はこの限りではなく、ＸＹ軸直行型でも良い。 Next, the flow of the cutting process will be described with reference to FIGS.
First, the transport hand of the hand unit 102 takes out the semiconductor substrate 1 from the storage cassette 111 of the storage unit 101 in which the semiconductor substrate 1 is stored. The storage unit 101 has an elevator mechanism that moves up and down to the height at which the semiconductor substrate 1 of the transport hand is taken out. Next, the transport hand vacuum-sucks the semiconductor substrate and transports it to the sensing unit 103. The transport hand is a Θ3-axis and Z-axis scalar robot, and can be easily handled by each processing unit. The robot mechanism is not limited to this, and may be an XY axis orthogonal type.

センシング部１０３では、回転テーブル１１２により半導体基板１を３６０°回転させ、その半導体基板１の外周をＣＣＤカメラ１１１で撮像し、その結果を制御部１０７の演算部で処理して半導体基板１のセンター位置を算出する。   In the sensing unit 103, the semiconductor substrate 1 is rotated 360 ° by the rotary table 112, the outer periphery of the semiconductor substrate 1 is imaged by the CCD camera 111, and the result is processed by the arithmetic unit of the control unit 107 and the center of the semiconductor substrate 1 is processed. Calculate the position.

次に、搬送ハンドは、その結果を元に、位置を補正して半導体基板１をチャックテーブル部１０４へ搬送し、チャックテーブル１１はバキュームによってこれを固定する。このチャックテーブル１１が加工の基準面となる。従って固定時及び加工時の平面精度を保つため、チャック面は多穴質の材料を使用して半導体基板１を全面チャックする構造が好ましい。材質は金属系、セラミック系、樹脂系などを用いる。チャックされた半導体基板１と対向して投光部１１４である光センサ部が配置され、受光部１１５であるカメラ部と共に半導体基板１の寸法を測定及び演算し、その結果を切削部１０５のＸ軸駆動部へフィードバックし、切削するための移動量を指令する。   Next, based on the result, the transport hand corrects the position and transports the semiconductor substrate 1 to the chuck table unit 104, and the chuck table 11 is fixed by vacuum. This chuck table 11 serves as a processing reference surface. Therefore, in order to maintain the flatness accuracy during fixing and processing, the chuck surface preferably has a structure in which the semiconductor substrate 1 is chucked over the entire surface using a multi-hole material. The material is metal, ceramic, or resin. An optical sensor unit that is a light projecting unit 114 is arranged to face the chucked semiconductor substrate 1, and the dimensions of the semiconductor substrate 1 are measured and calculated together with the camera unit that is the light receiving unit 115, and the result is calculated as X of the cutting unit 105. Feedback to the shaft drive unit and command the amount of movement for cutting.

切削面が配線形成面の場合、具体的には図４に示すように、レーザ光を照射し、レジストマスクを加熱飛散させ、表面を露出させることが好ましい。そして図５に示すように、赤外レーザ光を利用した透過型センサを利用して位置を計測する。そして、そこで演算された結果を元に、実際に切削を行うバイト１０が搭載されたテーブルがＸ方向に移動し、切削を開始する。ここで使用するバイト１０は、ダイヤモンド等からなる。このようにして設定寸法までの切削を完了する。   When the cutting surface is a wiring forming surface, specifically, as shown in FIG. 4, it is preferable to irradiate a laser beam to heat and scatter the resist mask to expose the surface. And as shown in FIG. 5, a position is measured using the transmissive | pervious sensor using an infrared laser beam. Then, based on the result calculated there, the table on which the cutting tool 10 that actually performs cutting moves in the X direction and starts cutting. The cutting tool 10 used here is made of diamond or the like. In this way, the cutting to the set dimension is completed.

次に、搬送ハンドがチャックテーブル１１から半導体基板１を取り出し、洗浄部へと搬送する。洗浄部１０５では半導体基板１をバキューム固定して回転させながら、洗浄水により加工後の表面残留異物を洗い流す。その後、エアブローしながら高速回転させ、洗浄水を吹き飛ばしながら乾燥させる。乾燥が完了したら、再び搬送ハンドが半導体基板１を取り出し、最後に収納部１０１の収納カセット１１１に収納する。   Next, the transport hand takes out the semiconductor substrate 1 from the chuck table 11 and transports it to the cleaning unit. In the cleaning unit 105, the semiconductor substrate 1 is vacuum fixed and rotated, and the processed surface residual foreign matter is washed away with cleaning water. After that, it is rotated at a high speed while blowing air, and is dried while blowing off cleaning water. When the drying is completed, the transport hand takes out the semiconductor substrate 1 again and finally stores it in the storage cassette 111 of the storage unit 101.

以上の各工程を、先ずバンプ及びバンプ間に絶縁膜が形成されている面を基準として裏面を切削し、その後、裏面を基準として各バンプの表面及び絶縁膜の表面を切削という処理を行い、平坦化処理を完了する。   For each of the above steps, first, the back surface is cut on the basis of the bump and the surface on which the insulating film is formed between the bumps, and then the surface of each bump and the surface of the insulating film are cut on the back surface as a reference, Complete the planarization process.

（半導体装置及びその製造方法）
次に、上述したバンプの形成方法を実行する半導体製造装置を用いて、半導体装置を製造する方法について説明する。なおここでは、半導体装置の構成をその製造方法と共に述べる。
図９Ａ〜図９Ｃは、本実施形態による半導体装置の製造方法を工程順に示す概略平面図である。 (Semiconductor device and manufacturing method thereof)
Next, a method of manufacturing a semiconductor device using a semiconductor manufacturing apparatus that executes the above-described bump forming method will be described. Here, the configuration of the semiconductor device is described together with the manufacturing method thereof.
9A to 9C are schematic plan views showing the method for manufacturing the semiconductor device according to the present embodiment in the order of steps.

先ず、図１及び図２で説明した各工程を経て、ＬＳＩ素子等が搭載され、バイトを用いた切削加工により上面３ａの平坦化されたバンプ３を有する半導体基板１から、図９Ａに示すように、各半導体チップ２１を切り出す。   First, through each step described in FIGS. 1 and 2, an LSI element or the like is mounted, and a semiconductor substrate 1 having bumps 3 whose upper surface 3a is flattened by cutting using a cutting tool is shown in FIG. 9A. Then, each semiconductor chip 21 is cut out.

続いて、図９Ｂに示すように、バイトを用いた切削加工により上面の平坦化されたバンプ３を有する半導体基板２２を用意し、この半導体基板２２上に、各半導体チップ２１をバンプ３の平坦化された上面３ａ同士で電気的に接続する。具体的には、半導体基板２２と半導体チップ２１とを上面３ａ同士で対向するように配置し、室温〜３５０℃、ここでは１７０℃程度で圧着させ、接続する。各上面３ａは共に高精度に平坦化されているため、従来のように高温・高圧等を要することなく、半導体基板２２と半導体チップ２１とを容易に接続することができる。   Subsequently, as shown in FIG. 9B, a semiconductor substrate 22 having bumps 3 whose upper surfaces are flattened by cutting using a cutting tool is prepared, and each semiconductor chip 21 is flattened on the semiconductor substrate 22. The formed upper surfaces 3a are electrically connected to each other. Specifically, the semiconductor substrate 22 and the semiconductor chip 21 are arranged so that the upper surfaces 3a face each other, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface 3a is flattened with high accuracy, the semiconductor substrate 22 and the semiconductor chip 21 can be easily connected without requiring high temperature and high pressure as in the prior art.

そして、図９Ｃに示すように、半導体チップ２１の接続された半導体基板２２から半導体チップ２３毎に切り出し、ワイヤボンディング法（ワイヤ２５を用いた接続）等の工程を経て、基板２４上に半導体チップ２３を搭載し、半導体装置を完成させる。   Then, as shown in FIG. 9C, each semiconductor chip 23 is cut out from the semiconductor substrate 22 to which the semiconductor chip 21 is connected, and the semiconductor chip is formed on the substrate 24 through a process such as a wire bonding method (connection using the wire 25). 23 is mounted to complete the semiconductor device.

以上説明したように、本実施形態によれば、ＣＭＰに替わり、半導体基板１上に形成された微細なバンプ３の表面を、ディッシング等の不都合を発生させることなく安価に高速で平坦化し、バンプ３の接続を容易且つ確実に行うことが可能となる。これにより、バンプ３同士の高温・高圧等の条件を要しない接続が可能となり、信頼性の高い半導体装置を歩留まり良く製造することができる。   As described above, according to the present embodiment, instead of CMP, the surface of the fine bump 3 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. 3 can be connected easily and reliably. As a result, the bumps 3 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield.

［第２の実施形態］
次に、第２の実施形態について説明する。第１の実施形態では、バンプ材料としてＡｕを例示したが、本実施形態ではニッケル（Ｎｉ）を用いる場合を例示する。
図１０Ａ〜図１０Ｆは、本実施形態によるバンプの形成方法を工程順に示す概略断面図である。 [Second Embodiment]
Next, a second embodiment will be described. In the first embodiment, Au is exemplified as the bump material. However, in this embodiment, a case where nickel (Ni) is used is illustrated.
10A to 10F are schematic cross-sectional views illustrating the bump forming method according to the present embodiment in the order of steps.

先ず、第１の実施形態の図１Ａ，Ｂと同様の工程を経て、半導体基板１を裏面研削し、ＴＴＬを所定値以下、具体的には１μｍ以下に制御する。
この半導体基板１を用い、図１０Ａに示すように、半導体基板１の表面アルミニウム系金属からなる電極３１をパターン形成した後、この電極３１に無電解メッキ法によりニッケルリンメッキ膜３２を膜厚５μｍ〜１０μｍ程度に形成する。 First, through the same steps as in FIGS. 1A and 1B of the first embodiment, the semiconductor substrate 1 is ground on the back surface, and the TTL is controlled to a predetermined value or less, specifically to 1 μm or less.
Using this semiconductor substrate 1, as shown in FIG. 10A, after patterning an electrode 31 made of an aluminum metal on the surface of the semiconductor substrate 1, a nickel phosphor plating film 32 is formed on the electrode 31 by an electroless plating method to a thickness of 5 μm. It is formed to about 10 μm.

ニッケルリンメッキ膜３２は、汎用の無電解メッキ法によって、ニッケル−リン、ニッケル−リン−ホウ素、ニッケル−ホウ素などを用いて形成する。例えば、ニッケル−リン合金は次亜リン酸浴(次亜リン酸ナトリウムまたは次亜リン酸カリウム)で形成し、ニッケ
ル−ホウ素合金は水素化ホウ素ナトリウム浴またはジメチルアミノボランを用い弱酸性浴または中性浴で形成し、ニッケル−リン−ホウ素合金は中性浴で形成する。 The nickel phosphorous plating film 32 is formed using nickel-phosphorus, nickel-phosphorus-boron, nickel-boron or the like by a general electroless plating method. For example, a nickel-phosphorus alloy is formed with a hypophosphite bath (sodium hypophosphite or potassium hypophosphite), and a nickel-boron alloy is a weakly acidic bath or medium using a sodium borohydride bath or dimethylaminoborane. The nickel-phosphorus-boron alloy is formed with a neutral bath.

ここで、ニッケルリン系無電解メッキでは、上述した如何なる合金系を選択しても、ニッケルリンメッキ膜３２の表層に機械的な脆弱層であるリン濃縮層３３が形成される。半田バンプ形成後、このリン濃縮層が原因となりメッキと半田バンプとの界面強度が低下する。このリン濃縮層の厚みは、２０ｎｍ〜４０ｎｍ程度であり、メッキ浴中のリン含有率が高くなるほど厚くなる。   Here, in nickel-phosphorus electroless plating, a phosphorus-enriched layer 33 that is a mechanical fragile layer is formed on the surface layer of the nickel-phosphorous plating film 32 regardless of which alloy system is selected. After the formation of the solder bump, the phosphorus concentrated layer causes the interface strength between the plating and the solder bump to decrease. The thickness of this phosphorus concentration layer is about 20 nm to 40 nm, and becomes thicker as the phosphorus content in the plating bath increases.

また、このリン濃縮層は下地の材料(ガラス基板、鉄基板、アルミニウム基板)によらず
、またメッキの厚みに依らず生成される。また、例えば特許文献６で記載されているようなニッケル系無電解メッキを半田融点以上のアニール処理をしても、表層には必ずリン濃縮層が生成される。リン濃縮層を除去しなければ、高信頼性のあるメッキ被膜と半田バンプの形成は困難である。 In addition, this phosphorus-enriched layer is generated regardless of the underlying material (glass substrate, iron substrate, aluminum substrate) and regardless of the plating thickness. Further, even if nickel-based electroless plating as described in Patent Document 6, for example, is annealed to a temperature higher than the solder melting point, a phosphorus-enriched layer is always generated on the surface layer. Unless the phosphorus-enriched layer is removed, it is difficult to form a highly reliable plating film and solder bump.

これらの問題について、半田材料に銅を添加することにより、銅−ニッケル−錫系の化合物層が形成され、そのバリア効果によりリン濃縮層の形成を抑制する方法がある。ところが、Ａｕメッキ厚が５００ｎｍ以上ではリン濃縮層が形成されるなど、Ａｕメッキ厚の制約や、半田材料の選択性が狭まるという問題点がある。   Regarding these problems, there is a method in which a copper-nickel-tin compound layer is formed by adding copper to the solder material, and the formation of a phosphorus-enriched layer is suppressed by its barrier effect. However, when the Au plating thickness is 500 nm or more, there is a problem that the limitation of the Au plating thickness and the selectivity of the solder material are narrowed, such as the formation of a phosphorus concentrated layer.

そこで本例では、ニッケルリンメッキ膜３２の切削加工による平坦化時に、同時にこのリン濃縮層３３を除去する。
具体的には、先ず図１０Ｂに示すように、基板表面を覆うように保護膜３４として液状レジストを被覆し、後述の切削加工による物理的衝撃の緩和層とする。保護膜３４は、回転塗布等で１０μｍ〜１５μｍ程度の厚みに塗布し、キュアすることにより形成する。 Therefore, in this example, at the time of flattening the nickel phosphorus plating film 32 by cutting, the phosphorus concentrated layer 33 is removed at the same time.
Specifically, as shown in FIG. 10B, first, a liquid resist is coated as a protective film 34 so as to cover the substrate surface to form a physical impact mitigation layer by a cutting process described later. The protective film 34 is formed by applying and curing to a thickness of about 10 μm to 15 μm by spin coating or the like.

その後、図２Ａと同様、基板支持台の支持面に例えば真空吸着により裏面を吸着させ、半導体基板１を基板支持台に固定する。このとき、裏面１ｂへの図１Ｂの平坦化処理により半導体基板１の厚みが一定の状態とされており、更に裏面１ｂが支持面１１ａへの吸着により強制的にうねり等もない状態となり、これにより裏面１ｂが表面１ａの平坦化の基準面となる。この状態で、図１０Ｃに示すように、表面１ａにおける各ニッケルリンメッキ膜３２及び保護膜３４の表層を機械加工、ここではダイヤモンド等からなるバイトを用いて切削加工し、ニッケルリンメッキ膜３２のリン濃縮層３３を除去するとともに、ニッケルリンメッキ膜３２及び保護膜３４の表面が連続して平坦となるように平坦化処理する。切削量は、リン濃縮層３３を確実に除去できる１μｍ〜２μm程度とする。   Thereafter, as in FIG. 2A, the back surface is adsorbed on the support surface of the substrate support table by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support table. At this time, the thickness of the semiconductor substrate 1 is made constant by the flattening process of FIG. 1B on the back surface 1b, and the back surface 1b is not forcedly swelled by adsorption to the support surface 11a. Thus, the back surface 1b becomes a reference surface for flattening the front surface 1a. In this state, as shown in FIG. 10C, the surface layers of the nickel phosphorous plating film 32 and the protective film 34 on the surface 1a are machined, and in this case, cutting is performed using a cutting tool made of diamond or the like. The phosphorus concentration layer 33 is removed, and a flattening process is performed so that the surfaces of the nickel phosphorus plating film 32 and the protective film 34 are continuously flat. The cutting amount is set to about 1 μm to 2 μm so that the phosphorus concentrated layer 33 can be reliably removed.

続いて、必要に応じて、図１０Ｄに示すように、無電解メッキ法により、ニッケルリンメッキ膜３２上に金メッキ膜３５を形成する。金メッキ膜３５の厚みは３０ｎｍ〜５０ｎｍ程度が好ましい。   Subsequently, as shown in FIG. 10D, a gold plating film 35 is formed on the nickel phosphorous plating film 32 by an electroless plating method as necessary. The thickness of the gold plating film 35 is preferably about 30 nm to 50 nm.

続いて、図１０Ｅに示すように、保護膜３４を灰化処理等により除去する。このとき、半導体基板１の表面１ａ上には、高さが均一であり、切削加工により上面が一様に平坦化され、金メッキ膜３５が形成されてなるバンプ３６が形成される。   Subsequently, as shown in FIG. 10E, the protective film 34 is removed by ashing or the like. At this time, on the surface 1 a of the semiconductor substrate 1, bumps 36 are formed which are uniform in height, are uniformly flattened by cutting, and are formed with a gold plating film 35.

そして、必要に応じて、図１０Ｆに示すように、バンプ３６上に半田バンプ３７を形成する。この半田バンプ３７は、スクリーン印刷、半田ボール法、溶融等により形成する。半田の材質としては、鉛を含まない、スズ−銀系、スズ−亜鉛系、等の半田を用いることが望ましい。   Then, as necessary, solder bumps 37 are formed on the bumps 36 as shown in FIG. 10F. The solder bumps 37 are formed by screen printing, a solder ball method, melting, or the like. As a material for the solder, it is desirable to use a lead-free solder such as tin-silver or tin-zinc.

その後、フルカットダイシングにより半導体基板１を分割して半導体チップを切り出し、第１の実施形態と同様に半導体装置を完成させる。   Thereafter, the semiconductor substrate 1 is divided by full-cut dicing to cut out a semiconductor chip, and the semiconductor device is completed as in the first embodiment.

以上説明したように、本実施形態によれば、ＣＭＰに替わり、半導体基板１上に形成されたニッケルのバンプ３６の表面を、ディッシング等の不都合を発生させることなく安価に高速で平坦化し、これにより、バンプ３６同士の高温・高圧等の条件を要しない接続が可能となり、信頼性の高い半導体装置を歩留まり良く製造することができる。しかも、バンプ３６と半田バンプ３７との接合部位における信頼性を低下させるリン濃縮層３４を低コストで完全に除去できるため、上面が平坦化されたバンプ３６上に半田バンプ３７を確実に形成することが可能となる。   As described above, according to the present embodiment, instead of CMP, the surface of the nickel bump 36 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. Therefore, it is possible to connect the bumps 36 without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with a high yield. In addition, since the phosphorus-enriched layer 34 that lowers the reliability at the joint portion between the bump 36 and the solder bump 37 can be completely removed at low cost, the solder bump 37 is reliably formed on the bump 36 whose upper surface is flattened. It becomes possible.

［第３の実施形態］
次に、第３の実施形態について説明する。第１の実施形態では、半導体基板に多数の半導体チップを接合する場合について例示したが、本実施形態では半導体チップの状態で上述の平坦化処理を実行し、この半導体チップ同士を接合する場合について開示する。
図１１Ａ，図１１Ｂは、本実施形態による半導体装置の製造方法を工程順に示す概略断面図である。 [Third Embodiment]
Next, a third embodiment will be described. In the first embodiment, the case where a large number of semiconductor chips are bonded to the semiconductor substrate is illustrated. However, in the present embodiment, the above-described planarization process is performed in the state of the semiconductor chip, and the semiconductor chips are bonded to each other. Disclose.
11A and 11B are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.

先ず、図１１Ａに示すように、第１の実施形態の裏面研削をすることなく、ＬＳＩ素子等が搭載され、高さの異なる（未だ高さにバラツキのある）複数のバンプ、ここではＡｕバンプ４２が形成されてなる半導体基板から、個々の半導体チップ４１を切り出す。   First, as shown in FIG. 11A, a plurality of bumps, which are mounted with LSI elements and have different heights (there are still variations in height), here Au bumps, without the back surface grinding of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.

続いて、半導体チップ４１の表層を機械加工、ここでは第１の実施形態と同様にダイヤモンド等からなるバイトを用いて切削加工し、各Ａｕバンプ４２の表面が連続して平坦となるように平坦化処理する。これにより、各Ａｕバンプ４２の高さが均一化されるとともに、上面が鏡面状に平坦化される。   Subsequently, the surface layer of the semiconductor chip 41 is machined. Here, the surface of each Au bump 42 is flattened by cutting using a cutting tool made of diamond or the like as in the first embodiment. Process. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.

続いて、図１１Ｂに示すように、一対の半導体チップ４１を対向させ、Ａｕバンプ４２の平坦化された上面同士で両者を電気的に接続する。具体的には、一対の半導体チップ４１を上面同士で対向するように配置し、室温〜３５０℃、ここでは１７０℃程度で圧着させ、接続する。各上面は共に高精度に平坦化されているため、従来のように高温・高圧等を要することなく、一対の半導体チップ４１を容易に接続することができる。   Subsequently, as shown in FIG. 11B, the pair of semiconductor chips 41 are opposed to each other, and the two flattened upper surfaces of the Au bumps 42 are electrically connected to each other. Specifically, a pair of semiconductor chips 41 are arranged so as to face each other, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art.

このように、本実施形態によれば、ＣＭＰに替わり、半導体チップ４１上に形成された微細なＡｕバンプ４２の表面を、ディッシング等の不都合を発生させることなく安価に高速で平坦化し、一対の半導体チップ４１におけるＡｕバンプ４２の接続を容易且つ確実に行うことが可能となる。これにより、Ａｕバンプ４２同士の高温・高圧等の条件を要しない接続が可能となり、信頼性の高い半導体装置を歩留まり良く製造することができる。しかも、半導体基板から個々の半導体チップ４１に切り出した後に上述の切削加工を実行するため、ＴＴＶを制御する工程を省略することができ、工程数削減に寄与する。   As described above, according to the present embodiment, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It becomes possible to connect the Au bumps 42 in the semiconductor chip 41 easily and reliably. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.

［変形例１］
ここで、本実施形態の変形例１について説明する。
図１２Ａ〜図１２Ｃは、変形例１による半導体装置の製造方法を工程順に示す概略断面図である。 [Modification 1]
Here, the modification 1 of this embodiment is demonstrated.
12A to 12C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Modification 1 in the order of steps.

先ず、図１２Ａに示すように、第１の実施形態の裏面研削をすることなく、ＬＳＩ素子等が搭載され、高さの異なる（未だ高さにバラツキのある）複数のバンプ、ここではＡｕバンプ４２が形成されてなる半導体基板から、個々の半導体チップ４１を切り出す。   First, as shown in FIG. 12A, a plurality of bumps, which are mounted with LSI elements and having different heights (there are still variations in height), here Au bumps, without grinding the back surface of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.

続いて、半導体チップ４１の表面にＡｕバンプ４２を埋め込むように絶縁材からなる樹脂層４３を形成する。なお、半導体基板の状態でＡｕバンプ４２を埋め込むように樹脂層４３を形成した後、個々の半導体チップ４１を切り出すようにしても良い。   Subsequently, a resin layer 43 made of an insulating material is formed so as to embed Au bumps 42 on the surface of the semiconductor chip 41. In addition, after forming the resin layer 43 so as to embed the Au bumps 42 in the state of the semiconductor substrate, the individual semiconductor chips 41 may be cut out.

続いて、図１２Ｂに示すように、半導体チップ４１の表層を機械加工、ここでは第１の実施形態と同様にダイヤモンド等からなるバイトを用いて切削加工し、各Ａｕバンプ４２の表面及び樹脂層４３の表面が連続して平坦となるように平坦化処理する。これにより、各Ａｕバンプ４２の高さが均一化されるとともに、上面が鏡面状に平坦化される。   Subsequently, as shown in FIG. 12B, the surface layer of the semiconductor chip 41 is machined, here, similarly to the first embodiment, cutting is performed using a cutting tool made of diamond or the like, and the surface of each Au bump 42 and the resin layer The surface of 43 is flattened so as to be continuously flat. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.

続いて、一対の半導体チップ４１を対向させ、Ａｕバンプ４２及び樹脂層４３の平坦化された上面同士で両者を電気的に接続する。具体的には、一対の半導体チップ４１を上面同士で対向するように配置し、室温〜３５０℃、ここでは１７０℃程度で圧着させ、接続する。各上面は共に高精度に平坦化されているため、従来のように高温・高圧等を要することなく、一対の半導体チップ４１を容易に接続することができる。更に、樹脂膜４３が一対の半導体チップ４１の接合を確実にするとともに、電極４２等を保護するアンダーフィルとして寄与する。   Subsequently, the pair of semiconductor chips 41 are made to face each other, and the Au bumps 42 and the resin layer 43 are electrically connected to each other on the flattened upper surfaces. Specifically, a pair of semiconductor chips 41 are arranged so as to face each other, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art. Further, the resin film 43 ensures the bonding of the pair of semiconductor chips 41 and contributes as an underfill for protecting the electrodes 42 and the like.

このように、本変形例１によれば、ＣＭＰに替わり、半導体チップ４１上に形成された微細なＡｕバンプ４２の表面を、ディッシング等の不都合を発生させることなく安価に高速で平坦化し、一対の半導体チップ４１におけるＡｕバンプ４２の接続を容易且つ確実に行うことが可能となる。これにより、Ａｕバンプ４２同士の高温・高圧等の条件を要しない接続が可能となり、信頼性の高い半導体装置を歩留まり良く製造することができる。しかも、半導体基板から個々の半導体チップ４１に切り出した後に上述の切削加工を実行するため、ＴＴＶを制御する工程を省略することができ、工程数削減に寄与する。   As described above, according to the first modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It is possible to easily and reliably connect the Au bumps 42 in the semiconductor chip 41. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.

［変形例２］
次いで、本実施形態の変形例２について説明する。
図１３Ａ〜図１３Ｃは、変形例２による半導体装置の製造方法を工程順に示す概略断面図である。 [Modification 2]
Next, a second modification of the present embodiment will be described.
13A to 13C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Modification 2 in the order of steps.

先ず、図１３Ａに示すように、第１の実施形態の裏面研削をすることなく、ＬＳＩ素子等が搭載され、高さの異なる（未だ高さにバラツキのある）複数のバンプ、ここではＡｕバンプ４２が形成されてなる半導体基板から、個々の半導体チップ４１を切り出す。   First, as shown in FIG. 13A, a plurality of bumps having different heights (having variations in height) (here, Au bumps) mounted with LSI elements or the like without the back surface grinding of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.

続いて、半導体チップ４１の表層を機械加工、ここでは第１の実施形態と同様にダイヤモンド等からなるバイトを用いて切削加工し、各Ａｕバンプ４２の表面表面が連続して平坦となるように平坦化処理する。これにより、各Ａｕバンプ４２の高さが均一化されるとともに、上面が鏡面状に平坦化される。
続いて、図１３Ｂに示すように、平坦化処理された半導体チップ４１を２つ一組で一対の半導体チップ４１とし、一方の半導体チップ４１の表面にＡｕバンプ４２を完全に埋め込む厚みに、絶縁性の樹脂に導電性微粒子４５を含有する樹脂層４４を形成する。 Subsequently, the surface layer of the semiconductor chip 41 is machined, here, as in the first embodiment, cutting is performed using a cutting tool made of diamond or the like so that the surface of each Au bump 42 is continuously flat. Perform flattening. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.
Subsequently, as shown in FIG. 13B, the planarized semiconductor chips 41 are paired into a pair of semiconductor chips 41, and the insulating bumps are formed so that the Au bumps 42 are completely embedded in the surface of one of the semiconductor chips 41. The resin layer 44 containing the conductive fine particles 45 is formed on the conductive resin.

続いて、一対の半導体チップ４１を対向させ、Ａｕバンプ４２の平坦化された上面同士で両者を電気的に接続する。具体的には、一対の半導体チップ４１を上面同士で対向するように配置し、室温〜３５０℃、ここでは１７０℃程度で圧着させる。ここで、熱圧着により対向するＡｕバンプ４２同士が導電性微粒子４５を介して接触し、電気的に接続される。各上面は共に高精度に平坦化されているため、従来のように高温・高圧等を要することなく、一対の半導体チップ４１を容易に接続することができる。更に、樹脂層４４の樹脂が一対の半導体チップ４１の密着性及び電気的接続を確実にするとともに、電極４２等を保護するアンダーフィルとして寄与する。   Subsequently, the pair of semiconductor chips 41 are opposed to each other, and the planarized upper surfaces of the Au bumps 42 are electrically connected to each other. Specifically, the pair of semiconductor chips 41 are disposed so as to face each other on the upper surface, and are bonded at room temperature to 350 ° C., here about 170 ° C. Here, the opposing Au bumps 42 are brought into contact with each other through the conductive fine particles 45 by thermocompression bonding, and are electrically connected. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art. Further, the resin of the resin layer 44 ensures adhesion and electrical connection between the pair of semiconductor chips 41 and contributes as an underfill for protecting the electrodes 42 and the like.

このように、本変形例２によれば、ＣＭＰに替わり、半導体チップ４１上に形成された微細なＡｕバンプ４２の表面を、ディッシング等の不都合を発生させることなく安価に高速で平坦化し、一対の半導体チップ４１におけるＡｕバンプ４２の接続を容易且つ確実に行うことが可能となる。これにより、Ａｕバンプ４２同士の高温・高圧等の条件を要しない接続が可能となり、信頼性の高い半導体装置を歩留まり良く製造することができる。しかも、半導体基板から個々の半導体チップ４１に切り出した後に上述の切削加工を実行するため、ＴＴＶを制御する工程を省略することができ、工程数削減に寄与する。   Thus, according to the second modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It becomes possible to connect the Au bumps 42 in the semiconductor chip 41 easily and reliably. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.

［第４の実施形態］
次に、第４の実施形態について説明する。第１の実施形態では、半導体基板に外部接続用のバンプを形成する場合について例示したが、本実施形態ではワイヤボンディング法を用いたスタッドバンプを形成する場合について開示する。
図１４Ａ〜図１４Ｆは、本実施形態による半導体装置の製造方法を工程順に示す概略断面図である。 [Fourth Embodiment]
Next, a fourth embodiment will be described. In the first embodiment, the case where bumps for external connection are formed on the semiconductor substrate is illustrated. However, in the present embodiment, the case where stud bumps using a wire bonding method are formed is disclosed.
14A to 14F are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.

先ず、図１４Ａ及び図１４Ｂに示すように、図１Ａと同様に素子形成部位にＬＳＩ半導体素子と電極パッド等の形成された半導体基板５１の裏面を研削し、半導体基板５１の厚みを一定、具体的にはＴＴＶ（基板の最大厚みと最小厚みとの差）を１μｍ以下に制御する。   First, as shown in FIGS. 14A and 14B, as in FIG. 1A, the back surface of the semiconductor substrate 51 on which the LSI semiconductor elements and electrode pads are formed at the element formation site is ground, and the thickness of the semiconductor substrate 51 is kept constant. Specifically, the TTV (difference between the maximum thickness and the minimum thickness of the substrate) is controlled to 1 μm or less.

ここで、前記研削工程においては、半導体基板５１の裏面を研削した後に、スパッタ法等により半導体基板５１上に金属膜、例えばＡｌ膜を形成し、これをパターニングすることにより、電気的接続箇所となる部位に電極パッド５２を形成しても良い。   Here, in the grinding step, after grinding the back surface of the semiconductor substrate 51, a metal film, for example, an Al film, is formed on the semiconductor substrate 51 by a sputtering method or the like, and this is patterned. The electrode pad 52 may be formed at a portion to be formed.

続いて、図１４Ｃに示すように、金属としてＡｕを用いたワイヤボンディング法により、例えば２０μｍ径のＡｕボンディングワイヤの先端を溶融して形成したボール状の塊を電極パッド５２上に圧着した後、当該ワイヤを引きちぎり（プレカット）、電極パッド５２上にＡｕ突起５３を形成する。このとき、各Ａｕ突起５３の電極パッド５２からの高さをボンディングワイヤ径の２倍以上、ここでは６０μｍ程度となるように規定する。この場合、実際にはＡｕ突起５３の高さにはバラツキがあり、５０μｍ〜６０μｍ程度であれば良い。   Subsequently, as shown in FIG. 14C, after a ball-shaped lump formed by melting the tip of an Au bonding wire having a diameter of 20 μm, for example, is bonded onto the electrode pad 52 by a wire bonding method using Au as a metal, The wire is torn off (pre-cut), and Au protrusions 53 are formed on the electrode pads 52. At this time, the height of each Au protrusion 53 from the electrode pad 52 is defined to be at least twice the diameter of the bonding wire, here about 60 μm. In this case, the height of the Au protrusion 53 actually varies, and it may be about 50 μm to 60 μm.

続いて、図１４Ｄに示すように、ダイヤモンド等からなるバイト１０を用いて切削加工し、各Ａｕ突起５３の上面が連続して平坦となるように平坦化処理し、スタッドバンプ５４を形成する。ここでは、切削位置を電極パッド５２から例えば５０μｍ程度の高さとする。切削条件は切削速度１０ｍ／ｓ、１回当たりの送りを２０μｍ程度とし、最初の切削位置から２μｍずつ追い込んでゆく。これにより、図１４Ｅに示すように、Ａｕ突起５３の上面が鏡面状に平坦化され、スタッドバンプ５４が形成される。   Subsequently, as shown in FIG. 14D, cutting is performed using a cutting tool 10 made of diamond or the like, and a flattening process is performed so that the upper surface of each Au protrusion 53 is continuously flat, thereby forming a stud bump 54. Here, the cutting position is set to a height of, for example, about 50 μm from the electrode pad 52. The cutting conditions are a cutting speed of 10 m / s, a feed per stroke of about 20 μm, and a 2 μm drive from the initial cutting position. As a result, as shown in FIG. 14E, the upper surface of the Au protrusion 53 is flattened into a mirror surface, and the stud bump 54 is formed.

この切削加工による平坦化方法はＣＭＰと比べてスラリーなどが必要なく、切削工具であるバイトはたとえ摩耗を起こして研磨して繰り返し使用できるので、コストが安い。チャックテーブルにチャッキングした半導体基板を高速回転させ、その上でバイトを所定の速度で移動させて、任意の切り込み量を一度に切削するため、半導体基板１枚当たり１〜２分間で終了可能であり、非常にスループットの高い方法である。バイトによる切削加工では、切削条件を適切にすることにより、Ａｕのボンディングワイヤを用いたスタッドバンプの突起なども、突起の先端部で切削した場合でも、突起の傾きや折れなどのない平面出しが可能である。しかしながら、３０Ｈｖ以下の硬度であると、切削時に突起の傾きが生じる恐れがあるため、ワイヤの硬度は３０Ｈｖ以上であることが望ましい。   This flattening method by cutting does not require a slurry or the like as compared with CMP, and the cutting tool, which is a cutting tool, is worn and polished so that it can be used repeatedly, so that the cost is low. The semiconductor substrate chucked on the chuck table is rotated at a high speed, and then the cutting tool is moved at a predetermined speed to cut an arbitrary cutting amount at a time. Therefore, it can be completed in 1 to 2 minutes per semiconductor substrate. There is a very high throughput method. When cutting with a bite, by making the cutting conditions appropriate, even when stud bump projections using Au bonding wire are cut at the tip of the projection, flattening without tilting or bending of the projection can be achieved. Is possible. However, if the hardness is 30 Hv or less, the protrusions may be inclined during cutting. Therefore, the hardness of the wire is preferably 30 Hv or more.

本実施形態では、切削加工の終点として、全てのスタッドバンプについて、切削面の径がワイヤ径と同等以上になった時点とする。通常、スタッドバンプはプレカット後の高さにばらつきが大きく、全てのスタッドバンプで切削面の径がワイヤ径と同等以上になった点を確認するのは困難である。切削方法としては、バイトが最も高いバンプに接触した点から１〜３μm位ずつ追い込んでゆき、全てのバイトの切削面を出すことが適当であるが、毎回拡大されたカメラ画像等で確認するのは非効率的である。   In the present embodiment, the end point of the cutting process is the time when the diameter of the cutting surface is equal to or greater than the wire diameter for all stud bumps. Normally, stud bumps vary greatly in height after pre-cutting, and it is difficult to confirm that the diameter of the cutting surface is equal to or greater than the wire diameter in all stud bumps. As a cutting method, it is appropriate to drive the cutting tool by 1 to 3 μm from the point where the cutting tool comes into contact with the highest bump and bring out the cutting surfaces of all the cutting tools. Is inefficient.

そこで本実施形態では、図１５Ａに示すように、終点検出方法として、レーザ発信器６１及び検出器６２を備える検出装置を用いて、切削加工後のスタッドバンプ５４の上面にレーザビームを操引し、当該上面にて反射したレーザを検出器６２で検出する方法を採用する。   Therefore, in the present embodiment, as shown in FIG. 15A, as a method for detecting the end point, a detection apparatus including a laser transmitter 61 and a detector 62 is used to operate a laser beam on the upper surface of the stud bump 54 after cutting. A method of detecting the laser reflected by the upper surface with the detector 62 is adopted.

そして、図１５Ｂに示すように、検出されたレーザ強度が全てのＡｕ突起５３にて所定の強度に達するまで加工を繰り返す。この検出装置は切削工具の進行方向後方に設置され、切削工具と同期して進行することが望ましい。スタッドバンプ５４の上面（切削面）はほぼ鏡面とされているため、レーザ光などは全反射する。切削工具と同期している場合、切削工具の進行速度に比例して遅延が生ずるため、厳密には全ての反射光が検出されるとは限らないが、切削速度は速くとも１０数ｍ／ｓであるため、ほぼ検出されると見なして良い。   Then, as shown in FIG. 15B, the processing is repeated until the detected laser intensity reaches a predetermined intensity at all the Au protrusions 53. It is desirable that this detection device is installed behind the cutting tool in the traveling direction and proceeds in synchronization with the cutting tool. Since the upper surface (cutting surface) of the stud bump 54 is almost a mirror surface, the laser beam or the like is totally reflected. When synchronized with the cutting tool, a delay is generated in proportion to the traveling speed of the cutting tool. Therefore, strictly speaking, not all reflected light is detected, but the cutting speed is 10 tens m / s at the fastest. Therefore, it can be considered that it is almost detected.

本実施形態では、バイトの後部からバイトの進行と同期して動くレーザ発信器６１及び検出器６２により、平坦化されたＡｕ突起５３の上面から反射されたレーザ光強度を測定しながら追い込んでゆき、例えば４６μｍの高さで全てのＡｕ突起５３の上面が露出されたことを感知し、切削を終了とした。   In the present embodiment, the laser transmitter 61 and the detector 62 moving in synchronization with the progress of the cutting tool from the rear part of the cutting tool are driven while measuring the intensity of the laser beam reflected from the upper surface of the flattened Au protrusion 53. For example, it was detected that the upper surfaces of all the Au protrusions 53 were exposed at a height of 46 μm, and the cutting was finished.

ここで、図１５Ｃに示すように、切削加工が不充分である場合や、切削面の径がワイヤ径以下である場合には、切削面以外の箇所に当たったレーザ光は乱反射し、検出器に検出されない。そのため、図１５Ｄに示すように、検出されたレーザ光強度はボンディングワイヤと同径まで切削された面よりも弱くなる。このようなスタッドバンプが一箇所でも確認された場合には、自動的に更に１μｍ〜２μｍ程度追い込み、最終的に全バンプで一定量以上のレーザ光強度が検出されるまで切削する。これにより、未切削又は切削不足による接続不良を防止することができるとともに、加工時間の大幅な短縮が可能となる。   Here, as shown in FIG. 15C, when the cutting process is insufficient, or when the diameter of the cutting surface is equal to or less than the wire diameter, the laser light hitting a place other than the cutting surface is irregularly reflected, and the detector Not detected. Therefore, as shown in FIG. 15D, the detected laser light intensity is weaker than the surface cut to the same diameter as the bonding wire. When such a stud bump is confirmed even at one place, it is automatically driven further by about 1 μm to 2 μm and finally cut until a laser light intensity of a certain amount or more is detected in all the bumps. Thereby, connection failure due to uncut or insufficient cutting can be prevented, and the processing time can be greatly shortened.

そして、図１４Ｆに示すように、半導体基板５１から各半導体チップ５５を切り出し、例えばフリップチップ法により、半導体チップ５５と回路基板５６とを接続する。具体的には、半導体チップ５５の上面平坦化されたスタッドバンプ５４と、回路基板５６の表面に形成された電極５７とを対向させて接触させ、加圧及び加熱により両者を接合する。なおこの場合、回路基板５６の電極５７もスタッドバンプ５４と同様に、上述した切削加工により平坦化した後、フリップチップ接続するようにしても好適である。   Then, as shown in FIG. 14F, each semiconductor chip 55 is cut out from the semiconductor substrate 51, and the semiconductor chip 55 and the circuit board 56 are connected by, for example, a flip chip method. Specifically, the stud bump 54 whose surface is flattened on the semiconductor chip 55 and the electrode 57 formed on the surface of the circuit board 56 are brought into contact with each other, and both are bonded by pressure and heating. In this case, like the stud bump 54, the electrode 57 of the circuit board 56 is also preferably made to be flip-chip connected after being flattened by the above-described cutting process.

以上説明したように、本実施形態によれば、ＣＭＰに替わり、半導体基板５１上に形成された微細なスタッドバンプ５４の表面を、ディッシング等の不都合を発生させることなく安価に高速で平坦化し、スタッドバンプ５４の接続を容易且つ確実に行うことが可能となる。これにより、バンプ同士の高温・高圧等の条件を要しない接続が可能となり、信頼性の高い半導体装置を歩留まり良く製造することができる。しかも、切削平坦化後におけるスタッドバンプ５４の高さを、ワイヤ径を規定しない場合に比べて１．５倍以上とすることができ、半導体素子への応力を緩和することが可能となり、デバイス寿命を延ばすことが可能となる。更に、切削における平坦面はワイヤ径と同等以上であるため、同じワイヤ径でも２倍以上の接合強度を得ることができる。また、従来と同程度の接合強度で充分な場合には、ワイヤ径を細くすることができるため、バンプピッチを狭めることが可能なうえ、ボンディングワイヤにかかるコストを下げることが可能となる。   As described above, according to the present embodiment, instead of CMP, the surface of the fine stud bump 54 formed on the semiconductor substrate 51 is flattened at a low speed without causing any inconvenience such as dishing, The stud bump 54 can be easily and reliably connected. As a result, the bumps can be connected without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. Moreover, the height of the stud bump 54 after the flattening of the cutting can be made 1.5 times or more compared with the case where the wire diameter is not specified, and the stress on the semiconductor element can be relaxed, and the device life Can be extended. Furthermore, since the flat surface in cutting is equal to or greater than the wire diameter, it is possible to obtain a bonding strength that is twice or more even with the same wire diameter. In addition, when a bonding strength comparable to the conventional one is sufficient, the wire diameter can be reduced, so that the bump pitch can be reduced and the cost for the bonding wire can be reduced.

［第５の実施形態］
次に、第５の実施形態について説明する。ここでは、いわゆるＴＡＢボンディング法による半導体装置を例示する。
図１６及び図１７は、本実施形態による半導体装置の製造方法を示す概略断面図である。 [Fifth Embodiment]
Next, a fifth embodiment will be described. Here, a semiconductor device by a so-called TAB bonding method is illustrated.
16 and 17 are schematic cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

この半導体装置を製造するには、先ず第１の実施形態と同様に、図１及び図２に示す諸工程を経て、素子形成部位にＬＳＩ半導体素子等の形成された半導体基板１の電極７１上に下地金属膜７２を介して、高さが均一であり、各Ａｕ突起２が切削加工されて上面３ａが一様に平坦化されてなるバンプ３を形成する。ここで、半導体基板１のバンプ３の周囲には絶縁性の保護膜７３が形成されている。   In order to manufacture this semiconductor device, first, similarly to the first embodiment, the steps shown in FIGS. 1 and 2 are performed, and then on the electrode 71 of the semiconductor substrate 1 on which an LSI semiconductor element or the like is formed at the element formation site. In addition, the bump 3 is formed through the base metal film 72, the height of which is uniform, and each Au protrusion 2 is cut and the upper surface 3a is uniformly flattened. Here, an insulating protective film 73 is formed around the bump 3 of the semiconductor substrate 1.

続いて、バンプ３の上面にプローブを接触させることにより、半導体基板１の半導体素子等の電気的特性を検査する。ここで、従来では、当該検査の際にはバンプの凹凸や汚染の存するメッキ終端面にプローブを接触させていたため、安定した接触が得られず、プローブの先端が当該凹凸部位で引っ掛り破損するというトラブルもあった。これに対して本実施形態では、上述の切削加工により高度に平坦化及び清浄化されたバンプ３の表面にプローブを接触させるため、極めて安定な状態で検査を行うことができる。   Subsequently, an electrical characteristic of the semiconductor element or the like of the semiconductor substrate 1 is inspected by bringing a probe into contact with the upper surface of the bump 3. Here, conventionally, since the probe is in contact with the bump end surface and the plating end surface where the contamination exists during the inspection, a stable contact cannot be obtained, and the tip of the probe is caught and damaged at the uneven portion. There was also a trouble. On the other hand, in this embodiment, since the probe is brought into contact with the surface of the bump 3 that has been highly planarized and cleaned by the above-described cutting process, the inspection can be performed in an extremely stable state.

続いて、この半導体基板１から個々の半導体チップ２１を切り出した後、図１６に示すように、ＴＡＢボンディング法により半導体チップ２１の接続を行う。
具体的には、銅箔７５からなりＡｕの表面処理が施されてＡｕ膜７６が形成されており、一端に位置する箇所が接続部位に該り、他端に樹脂層７７が設けられてなるＴＡＢリード７４を用意する。そして、半導体チップ２１をボンディングステージ８０上に載置固定して、半導体チップ２１の平坦化及び清浄化されたバンプ３の上面にＴＡＢリード７４の接続部位のＡｕ膜７６を接触させ、ヒータ７８により加熱しながら加圧し、両者を接合する。ここで、加熱温度は２００℃程度の比較的低温で良く、接着荷重も約２０ｇと従来の２／３程度に低減が可能となる。結果として４０μｍピッチ以下の微細ピッチのＴＡＢリードを位置ずれなく接続することが可能となる。 Subsequently, after the individual semiconductor chips 21 are cut out from the semiconductor substrate 1, the semiconductor chips 21 are connected by the TAB bonding method as shown in FIG.
Specifically, the Au film 76 is formed of the copper foil 75 and is subjected to the surface treatment of Au, the portion located at one end corresponds to the connection site, and the resin layer 77 is provided at the other end. A TAB lead 74 is prepared. Then, the semiconductor chip 21 is placed and fixed on the bonding stage 80, and the Au film 76 at the connection portion of the TAB lead 74 is brought into contact with the flattened and cleaned upper surface of the bump 3 by the heater 78. Pressurize while heating to join them together. Here, the heating temperature may be a relatively low temperature of about 200 ° C., and the adhesion load can be reduced to about 2/3 of the conventional one, about 20 g. As a result, it is possible to connect TAB leads having a fine pitch of 40 μm or less without displacement.

しかる後、図１７に示すように、半導体チップ２１をボンディングステージ８０から外し、バンプ３とＴＡＢリード７４との接続部位を含む半導体チップ２１の表面を覆うように封止樹脂７９を形成し、半導体装置を完成させる。   Thereafter, as shown in FIG. 17, the semiconductor chip 21 is removed from the bonding stage 80, and a sealing resin 79 is formed so as to cover the surface of the semiconductor chip 21 including the connection portion between the bump 3 and the TAB lead 74. Complete the device.

なお、本実施形態では、バンプとしてメッキバンプを形成する場合を例示したが、ワイヤボンディング法によるスタッドバンプを形成するようにしても良い。   In the present embodiment, the case where the plating bump is formed as the bump is exemplified, but the stud bump may be formed by a wire bonding method.

以上説明したように、本実施形態によれば、ＣＭＰに替わり、半導体基板１上に形成された微細なバンプ３の表面を、ディッシング等の不都合を発生させることなく安価に高速で平坦化し、バンプ３の接続を容易且つ確実に行うことが可能となる。これにより、バンプとリード端子との高温・高圧等の条件を要しない確実な接続が可能となり、信頼性の高いＴＡＢボンディングタイプの半導体装置を歩留まり良く製造することができる。   As described above, according to the present embodiment, instead of CMP, the surface of the fine bump 3 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. 3 can be connected easily and reliably. As a result, it is possible to reliably connect the bump and the lead terminal without requiring conditions such as high temperature and high pressure, and it is possible to manufacture a highly reliable TAB bonding type semiconductor device with a high yield.

［第６の実施形態］
次に、第６の実施形態について説明する。ここでは、上述した諸実施形態を実行するに際して、一対の基体（ここでは、フリップチップ法による半導体チップ及び回路基板を例示する。）について、上述の切削加工工程及び接合工程を実行するための装置構成を開示する。 [Sixth Embodiment]
Next, a sixth embodiment will be described. Here, when executing the above-described embodiments, an apparatus for executing the above-described cutting process and joining process for a pair of bases (here, a semiconductor chip and a circuit board by a flip chip method are illustrated). The configuration is disclosed.

図１８は、本実施形態による半導体製造装置を示す模式図である。
この半導体製造装置は、表面にバンプの形成された半導体チップを導入するためのチップ導入部８１と、表面に電極の形成された回路基板を導入するための回路基板導入部８２と、上述したバイトを用いた切削加工により半導体チップのバンプ表面を平坦化する工程を実行する切削部８３と、半導体チップと回路基板とを平坦化されたバンプと電極とで接合する工程を実行する接合部８４と、接合され一体化されてなる半導体装置を搬出するための搬出部８５とを備えており、更に、切削部８３及び接合部８４を不活性雰囲気で包含する清浄化保持部８６を有して構成されている。ここで、切削部８３では、半導体チップのみならず回路基板の電極表面も同様に切削加工により平坦化するようにしても良い。 FIG. 18 is a schematic diagram showing the semiconductor manufacturing apparatus according to the present embodiment.
This semiconductor manufacturing apparatus includes a chip introducing portion 81 for introducing a semiconductor chip having bumps formed on the surface, a circuit substrate introducing portion 82 for introducing a circuit substrate having electrodes formed on the surface, and the above-described bite. A cutting portion 83 for performing a step of flattening the bump surface of the semiconductor chip by cutting using a chip, and a bonding portion 84 for performing a step of bonding the semiconductor chip and the circuit board with the flattened bump and electrode. And a carry-out portion 85 for carrying out the joined and integrated semiconductor device, and further includes a cleaning holding portion 86 including the cutting portion 83 and the joint portion 84 in an inert atmosphere. Has been. Here, in the cutting part 83, not only the semiconductor chip but also the electrode surface of the circuit board may be flattened by cutting.

清浄化保持部８６は、平坦化工程と接合工程を共に清浄化雰囲気、具体的には不活性雰囲気内、例えばＡｒやＮ2等の酸素を含まない気相中、又は酸素を含む１ａｔｍ以下の雰囲気中に保持する機能を有している。これにより、接合工程の直前にＡｒプラズマ等を用いた清浄化工程を付加することなく、比較的容易に理想に極めて近い平坦化状態を維持することができ、バンプと電極の確実な接合が可能となる。 The cleaning holding unit 86 performs both the flattening process and the bonding process in a cleaning atmosphere, specifically, in an inert atmosphere, for example, in a gas phase not containing oxygen such as Ar or N 2, or in the oxygen atmosphere containing 1 atm or less. It has the function of keeping in the atmosphere. This makes it possible to maintain a flat state that is very close to the ideal relatively easily without adding a cleaning process using Ar plasma or the like immediately before the bonding process, and enables reliable bonding of bumps and electrodes. It becomes.

なお、本実施形態では、フリップチップ実装を例示したが、本発明はこれに限定されることなく、半導体チップと半導体ウェーハ、半導体チップ同士等の接合に利用しても好適である。   In the present embodiment, the flip chip mounting is exemplified. However, the present invention is not limited to this, and the present invention is also suitable for joining a semiconductor chip and a semiconductor wafer, semiconductor chips, or the like.

本発明によれば、ＣＭＰに替わり、基板上に形成された微細なバンプの表面を安価に高速で平坦化し、バンプ同士の接続を、ディッシング等の不都合を発生させることなく容易且つ確実に行うことが可能となる。   According to the present invention, instead of CMP, the surface of fine bumps formed on a substrate is flattened inexpensively and at high speed, and the bumps are connected easily and reliably without causing problems such as dishing. Is possible.

１，２２，５１ 半導体基板
１ａ 表面
１ｂ 裏面
２，５３ Ａｕ突起
３，３６ バンプ
３ａ 上面
１０ バイト
１１ 基板支持台
１１ａ 支持面
１２ レジストマスク
１２ａ バンプパターン
１３ レーザ光
１４ 赤外レーザ測定器
２１，２３，４１，５５ 半導体チップ
２４ 基板
３１，５７，７１ 電極
３２ ニッケルリンメッキ膜
３３ リン濃縮層
３４，７３ 保護膜
３５ 金メッキ膜
３７ 半田バンプ
４２ Ａｕバンプ
４３，４４，７７ 樹脂層
４５ 導電性微粒子
５２ 電極パッド
５４ スタッドバンプ
５６ 回路基板
７２ 下地金属膜
７４ ＴＡＢリード
７５ 銅箔
７６ Ａｕ膜
７９ 封止樹脂
８０ ボンディングステージ
８１ チップ導入部
８２ 回路基板導入部
８３ 切削部
８４ 接合部
８５ 搬出部
８６ 清浄化保持部 1, 22, 51 Semiconductor substrate 1a Front surface 1b Back surface 2, 53 Au protrusion 3, 36 Bump 3a Upper surface 10 Byte 11 Substrate support base 11a Support surface 12 Resist mask 12a Bump pattern 13 Laser beam 14 Infrared laser measuring instrument 21, 23 41, 55 Semiconductor chip 24 Substrate 31, 57, 71 Electrode 32 Nickel phosphorus plating film 33 Phosphorous enriched layer 34, 73 Protective film 35 Gold plating film 37 Solder bump 42 Au bump 43, 44, 77 Resin layer 45 Conductive fine particle 52 Electrode pad 54 Stud bump 56 Circuit board 72 Underlying metal film 74 TAB lead 75 Copper foil 76 Au film 79 Sealing resin 80 Bonding stage 81 Chip introduction part 82 Circuit board introduction part 83 Cutting part 84 Joint part 85 Unloading part 86 Cleaning holding part 86

Claims (4)

第１の基板の表面に、複数の第１のバンプを形成する工程と、
前記複数の第１のバンプ間に第１の絶縁膜を形成する工程と、
バイトを用いた切削加工により、前記複数の第１のバンプの表面及び前記第１の絶縁膜の表面が連続して平坦となるように平坦化処理する工程と、
第２の基板の表面に、複数の第２のバンプを形成する工程と、
前記複数の第２のバンプ間に第２の絶縁膜を形成する工程と、
バイトを用いた切削加工により、前記複数の第２のバンプの表面及び前記第２の絶縁膜の表面が連続して平坦となるように平坦化処理する工程と、
前記複数の第１のバンプと前記複数の第２のバンプ、及び、前記第１の絶縁膜と前記第２の絶縁膜を対向させて、それぞれを接続する工程と
を含むことを特徴とする半導体装置の製造方法。 Forming a plurality of first bumps on the surface of the first substrate;
Forming a first insulating film between the plurality of first bumps;
A step of performing a flattening process so that the surfaces of the plurality of first bumps and the surface of the first insulating film are continuously flattened by cutting using a cutting tool;
Forming a plurality of second bumps on the surface of the second substrate;
Forming a second insulating film between the plurality of second bumps;
A step of performing a flattening process so that the surface of the plurality of second bumps and the surface of the second insulating film are continuously flattened by cutting using a cutting tool;
A plurality of first bumps, a plurality of second bumps, and a step of making the first insulating film and the second insulating film face each other and connecting them to each other. Device manufacturing method. 前記第１の絶縁膜と前記第２の絶縁膜は樹脂であることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are made of resin. 前記接続する工程は、前記複数の第１のバンプと前記複数の第２のバンプ、及び前記第１の絶縁膜と前記第２の絶縁膜を加熱しながら圧着することを特徴とする請求項１又は２に記載の半導体装置の製造方法。   2. The step of connecting includes pressing the plurality of first bumps, the plurality of second bumps, and the first insulating film and the second insulating film while heating. Or the manufacturing method of the semiconductor device of 2. 第１の基板の表面に、複数の第１のバンプを形成する工程と、
バイトを用いた切削加工により、前記複数の第１のバンプの表面が連続して平坦となるように平坦化処理する工程と、
第２の基板の表面に、複数の第２のバンプを形成する工程と、
バイトを用いた切削加工により、前記複数の第２のバンプの表面が連続して平坦となるように平坦化処理する工程と、
前記第１の基板及び前記複数の第１のハンプ上に、導電性微粒子を含有する絶縁膜を形成する工程と、
前記複数の第１のバンプと前記複数の第２のハンプとを前記導電性微粒子を含有する絶縁膜を介して対向させ、それぞれを接続する工程と
を含むことを特徴とする半導体装置の製造方法。 Forming a plurality of first bumps on the surface of the first substrate;
A step of performing a flattening process so that the surfaces of the plurality of first bumps are continuously flattened by cutting using a cutting tool;
Forming a plurality of second bumps on the surface of the second substrate;
A step of performing a flattening process so that the surfaces of the plurality of second bumps are continuously flattened by cutting using a cutting tool;
Forming an insulating film containing conductive fine particles on the first substrate and the plurality of first humps;
A plurality of first bumps and a plurality of second humps facing each other through an insulating film containing the conductive fine particles, and connecting each of them. .
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