JP2009074823A - Wiring board for electronic component inspection device, and its manufacturing method - Google Patents

Wiring board for electronic component inspection device, and its manufacturing method Download PDF

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JP2009074823A
JP2009074823A JP2007241867A JP2007241867A JP2009074823A JP 2009074823 A JP2009074823 A JP 2009074823A JP 2007241867 A JP2007241867 A JP 2007241867A JP 2007241867 A JP2007241867 A JP 2007241867A JP 2009074823 A JP2009074823 A JP 2009074823A
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ceramic
wiring board
electronic component
wiring
layer
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Takaari Nasu
孝有 奈須
Masanori Kito
正典 鬼頭
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a wiring board used for an electronic component inspection device, which is used for the electronic component inspection device such as a prove card, capable of inspecting accurately and surely an electric characteristic, even in the case of, for example, electronic components formed in great numbers on a large-size Si wafer; and its manufacturing method. <P>SOLUTION: This wiring board 1 for the electronic component inspection device includes a relay substrate 2 having a ceramic layer S having a single layer, whose thermal expansion coefficient in the range of -40 to +150°C is 3.0-4.5×10<SP>-6</SP>/°C, and a plurality of penetration conductors 6 penetrating the interval between the front surface 3 and the rear surface 4 of the ceramic layer S; a multilayer ceramic wiring board 10 arranged on the rear surface 4 side of the relay substrate 2, and including a plurality of ceramic layers s1-s4, wiring layers 13-15 formed between the ceramic layers s1-s4, and via conductors v penetrating the plurality of ceramic layers s1-s4 to conduct the wiring layers 13-15 mutually; and a plurality of connection conductors 18 arranged between the relay substrate 2 and the wiring board 10, for conducting electrically the plurality of penetration conductors 6 on the relay substrate 2 to the wiring layers 13-15 on the multilayer ceramic wiring board 10. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、例えば、プローブカードなどの電子部品検査装置に用いられる配線基板に関し、特に大径のＳｉウェハなどに多数形成された電子部品ごとの電気的特性を正確に検査できる電子部品検査装置に用いられる配線基板およびその製造方法に関する。   The present invention relates to, for example, a wiring board used in an electronic component inspection apparatus such as a probe card, and more particularly to an electronic component inspection apparatus capable of accurately inspecting electrical characteristics of each electronic component formed on a large diameter Si wafer or the like. The present invention relates to a wiring board used and a manufacturing method thereof.

電子部品検査装置の一種であるプローブカードは、多数の微細なプローブをその表面に有し、かかるプローブをＳｉウェハに多数形成された半導体チップなどの電子部品ごとの電極に接触させることで、個々の電子部品の電気的特性を検査することに使用されている。
ところで、Ｓｉウェハは、直径が３００ｍｍあるいはそれ以上に大径化する傾向にある。これに応じて、Ｓｉウェハとプローブカードとの熱膨張率の差に起因して、一部の電子部品において、その電極とプローブとの電気的接続が不十分になるため、かかる電子部品の電気的特性を正確に検査できなくるおそれがある。 A probe card, which is a kind of electronic component inspection device, has a large number of fine probes on its surface, and by bringing such probes into contact with electrodes for each electronic component such as a semiconductor chip formed on a Si wafer. It is used to inspect the electrical characteristics of electronic parts.
By the way, the Si wafer tends to increase in diameter to 300 mm or more. Accordingly, due to the difference in thermal expansion coefficient between the Si wafer and the probe card, the electrical connection between the electrode and the probe becomes insufficient in some electronic components. There is a risk that the physical characteristics cannot be accurately inspected.

このため、例えば、複数の絶縁基板およびこれらの間に配設した配線層を有する測定用配線基板と、その表面に形成した複数のパッドごとの上に設けた複数の測定端子（プローブ）とを備え、上記配線基板の−４０〜＋４００℃における平均熱膨張係数を２×１０−５／℃〜５×１０−６／℃とし、且つ上記温度範囲において、上記配線基板と半導体ウェハとの伸びの差を０．０２％以下としたプローブカードなどが提案されている（例えば、特許文献１参照）。
特開２００６−２８４５４１号公報（第１〜１３頁、図１〜４） For this reason, for example, a measurement wiring substrate having a plurality of insulating substrates and a wiring layer disposed between them, and a plurality of measurement terminals (probes) provided on each of a plurality of pads formed on the surface thereof An average thermal expansion coefficient of the wiring board at −40 to + 400 ° C. is 2 × 10 −5 / ° C. to 5 × 10 −6 / ° C., and the elongation of the wiring board and the semiconductor wafer is increased in the temperature range. A probe card having a difference of 0.02% or less has been proposed (see, for example, Patent Document 1).
JP 2006-284541 A (pages 1 to 13 and FIGS. 1 to 4)

前記特許文献１のプローブカードに用いられる測定用配線基板は、その絶縁基板に少なくともＺｎＯ、ＣａＯ、ＳｒＯ、ＢａＯ、およびＺｒＯ２の一種を含み、その含有量を１５質量％以下とし、且つコーディエライト結晶相を含む焼結体を用いている。
しかし、かかる絶縁基板は、前記材料からなる複数のグリーンシートを積層し、その表面にプローブが取り付けられる複数のパッドを形成した後で焼成されるため、かかる焼成に伴う収縮によって上記パッドの位置がずれてくる。更に、前記測定用配線基板の内部には、その平面方向に沿った複数の配線層、およびこれらの間を接続するビア導体が形成されているため、これらの熱膨張によって、当該測定用配線基板の体積が変化することもある。
上記パッドの位置ずれや配線基板の体積変化の結果により、上記配線基板の表面に形成された複数のプローブの位置がずれ、特に表面の周辺部側に位置するプローブでは、Ｓｉウェハ側の電子部品の電極との電気的接続が不安定になったり、接続不良となって、当該電子部品の検査が不可能となり得る、おそれがあった。 The wiring board for measurement used in the probe card of Patent Document 1 includes at least one kind of ZnO, CaO, SrO, BaO, and ZrO 2 in the insulating substrate, the content is 15% by mass or less, and the cordier A sintered body containing a light crystal phase is used.
However, such an insulating substrate is baked after laminating a plurality of green sheets made of the above materials and forming a plurality of pads to which probes are attached on the surface thereof. It will shift. Furthermore, since a plurality of wiring layers along the plane direction and via conductors connecting between the wiring layers are formed inside the measurement wiring board, the measurement wiring board is caused by their thermal expansion. The volume of may change.
The position of the plurality of probes formed on the surface of the wiring board shifts due to the displacement of the pad and the change in volume of the wiring board. Especially, in the probe located on the peripheral side of the surface, the electronic component on the Si wafer side There is a risk that the electrical connection with the electrode may become unstable or the connection may be poor, making it impossible to inspect the electronic component.

本発明は、背景技術において説明した問題点を解決し、プローブカードなどの電子部品検査装置に用いられ、例えば、大径のＳｉウェハなどに多数形成された電子部品であっても、その電気的特性を正確且つ確実に検査できる電子部品検査装置に用いられる配線基板およびその製造方法を提供する、ことを課題とする。   The present invention solves the problems described in the background art, and is used in an electronic component inspection apparatus such as a probe card. For example, even an electronic component formed on a large diameter Si wafer or the like is electrically It is an object of the present invention to provide a wiring board used in an electronic component inspection apparatus capable of accurately and reliably inspecting characteristics and a method for manufacturing the same.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、プローブを取り付ける低熱膨張係数の中継基板と信号処理を成す配線層を含む多層セラミック配線基板とを別体とし、これらを導体を介して接続する、ことに着想して成されたものである。
即ち、本発明の電子部品検査装置用配線基板（請求項１）は、単層で且つ−４０〜＋１５０℃における熱膨張係数が３．０〜４．５×１０−６／℃のセラミック層、および該セラミック層の表面と裏面との間を貫通する複数の貫通導体を有する中継基板と、かかる中継基板の裏面側に配置され、複数のセラミック層、該セラミック層の間に形成された配線層、および上記複数のセラミック層を貫通して前記配線層の間を導通するビア導体を含む多層セラミック配線基板と、上記中継基板と多層セラミック配線基板との間に配置され、上記中継基板の複数の貫通導体と上記多層セラミック配線基板の配線層とを電気的に導通する複数の接続導体と、を含む、ことを特徴とする。 In order to solve the above problems, the present invention separates a low thermal expansion coefficient relay board to which a probe is attached and a multilayer ceramic wiring board including a wiring layer for signal processing, and connects them via a conductor. Invented.
That is, the wiring board for an electronic component inspection apparatus according to the present invention (Claim 1) is a single layer and a ceramic layer having a thermal expansion coefficient of 3.0 to 4.5 × 10 −6 / ° C. at −40 to + 150 ° C., And a relay substrate having a plurality of through conductors passing between the front surface and the back surface of the ceramic layer, and a plurality of ceramic layers disposed on the back surface side of the relay substrate and formed between the ceramic layers And a multilayer ceramic wiring board including a via conductor that passes through the plurality of ceramic layers and conducts between the wiring layers, and is disposed between the relay board and the multilayer ceramic wiring board. And a plurality of connecting conductors that electrically connect the through conductor and the wiring layer of the multilayer ceramic wiring board.

これによれば、複数の貫通導体を有する前記中継基板を形成する単層の前記セラミック層は、多数の電子部品を含むウェハを形成するＳｉの−４０〜＋１５０℃における熱膨張係数の約３×１０−６／℃と近似している。このため、上記温度範囲における熱的変化を受けても、中継基板の表面に取り付けられる複数のプローブと、Ｓｉウェハに形成された多数の電子部品ごとの電極との電気的接続を確保することが容易となる。更に、前記中継基板と多層セラミック配線基板とは、複数の接続導体を介して接合されため、両者間の熱膨張係数の差による影響を、かかる接続導体によって確実に吸収することが可能となる。このため、各プローブから検出された信号は、複数の接続導体、および多層セラミック配線基板内の配線層を介して、裏面側パッドから外部に出力可能となっている。従って、直径が３００ｍｍあるいはそれ以上の大径であるＳｉウェハなどに多数形成された電子部品であっても、その電気的特性を正確且つ確実に検査できる。
しかも、前記配線層は、多層セラミック基板にのみ形成され、且つ中継基板にないため、検査すべき電子部品に応じて、中継基板に対し形状変更などの設計変更を行うだけで、多層セラミック基板を共通して用いるか、あるい大きな変更なしで容易に且つ短時間で対応が可能となる。
尚、前記中継基板に形成される貫通導体には、かかる中継基板の表面と裏面との間を貫通する貫通孔の全体がほぼ円柱形にして形成されるビア導体の形態、あるいは、上記貫通孔の内壁に沿って形成された全体がほぼ円筒形を呈し且つ内部に樹脂や金属などを充填するスルーホール導体の形態が含まれる。 According to this, the single-layer ceramic layer forming the relay substrate having a plurality of through conductors has a thermal expansion coefficient of about 3 × at −40 to + 150 ° C. of Si forming a wafer including a large number of electronic components. It is approximated to 10 −6 / ° C. For this reason, even if it receives the thermal change in the said temperature range, it can ensure the electrical connection with the several probe attached to the surface of a relay substrate, and the electrode for many electronic components formed in Si wafer. It becomes easy. Furthermore, since the relay substrate and the multilayer ceramic wiring substrate are joined via a plurality of connecting conductors, it is possible to reliably absorb the influence due to the difference in the thermal expansion coefficient between them. For this reason, the signal detected from each probe can be output to the outside from the back side pad via the plurality of connection conductors and the wiring layer in the multilayer ceramic wiring board. Therefore, even if electronic components are formed in large numbers on a Si wafer having a large diameter of 300 mm or more, the electrical characteristics can be accurately and reliably inspected.
Moreover, since the wiring layer is formed only on the multilayer ceramic substrate and not on the relay substrate, the multilayer ceramic substrate can be formed by simply changing the design of the relay substrate according to the electronic component to be inspected. It can be used in common or can be handled easily and in a short time without major changes.
The through conductor formed in the relay substrate may be a via conductor in which the entire through hole penetrating between the front surface and the back surface of the relay substrate is formed in a substantially cylindrical shape, or the through hole described above. The shape of the through-hole conductor formed in a generally cylindrical shape along the inner wall is filled with resin, metal, or the like.

また、本発明には、前記中継基板のセラミック層は、マシナブルセラミック、ＡｌＮ、またはムライトの何れかからなる、電子部品検査装置用配線基板（請求項２）も含まれる。
更に、本発明には、前記マシナブルセラミックは、ＳｉＯ２とＡｌ２Ｏ３との混合物、あるいは、ＡｌＮとＢＮとの混合物である、電子部品検査装置用配線基板（請求項３）も含まれる。
これらによれば、中継基板は、前記温度範囲における熱膨張係数が約４．５×１０−６／℃のマシナブルセラミック、約４．３×１０−６／℃のＡｌＮ、または約４．２×１０−６／℃のムライトからなるセラミック層によって形成されている。そのため、前記温度範囲における熱膨張係数が約３．０×１０−６／℃のＳｉウェハとも、熱膨張係数がほぼ近似しているので、かかるＳｉウェハに形成された多数の電子部品の検査を正確且つ確実に行うことが可能となる。
尚、前記マシナブルセラミックとは、機械加工、特に切削加工が容易に施せるセラミックを指し、例えば、セラミック材料に含有される結晶の著しいへき開を利用したマイカセラミック、あるいは、粒界の選択的破壊を利用したチタン酸アルミニウムセラミックなども含まれる。 The present invention also includes a wiring board for an electronic component inspection apparatus (Claim 2), wherein the ceramic layer of the relay board is made of any one of machinable ceramic, AlN, and mullite.
Furthermore, the present invention includes a wiring board for an electronic component inspection apparatus (Claim 3), wherein the machinable ceramic is a mixture of SiO 2 and Al 2 O 3 or a mixture of AlN and BN. .
According to these, the relay substrate is a machinable ceramic having a thermal expansion coefficient in the temperature range of about 4.5 × 10 −6 / ° C., AlN of about 4.3 × 10 −6 / ° C., or about 4.2. It is formed of a ceramic layer made of mullite at × 10 −6 / ° C. For this reason, since the thermal expansion coefficient of the Si wafer having a thermal expansion coefficient in the temperature range of about 3.0 × 10 −6 / ° C. is approximately similar, many electronic components formed on the Si wafer can be inspected. It becomes possible to carry out accurately and reliably.
The machinable ceramic refers to a ceramic that can be easily machined, in particular, machined. For example, mica ceramic that uses significant cleavage of crystals contained in a ceramic material, or selective destruction of grain boundaries. Also used are aluminum titanate ceramics.

また、本発明には、前記中継基板を形成するセラミック層の厚みは、１ｍｍ以下である、電子部品検査装置用配線基板（請求項４）も含まれる。
これによれば、１ｍｍ以下と薄肉で且つ低熱膨張係数の前記中継基板に対し、複数の接続導体を介して、多層セラミック基板を接合しても、全体の厚みが約５〜６ｍｍと比較的薄い配線基板とすることができ、前記電子部品の検査工程において狭いスペースで済み、且つ取り扱いを容易化することにも寄与し得る。
尚、中継基板を形成する前記セラミック層の平面視における形状は、任意であるが、例えば検査すべき電子部品がＳｉウェハに形成されている場合には、かかるＳｉウェハの平面視における円形の全体をカバーし得る真円形のほか、正六角形、正八角形、あるいは正十二角形などの正多角形を呈する形態としても良い。 The present invention also includes an electronic component inspection device wiring board (Claim 4) in which the thickness of the ceramic layer forming the relay board is 1 mm or less.
According to this, even if a multilayer ceramic substrate is bonded to the relay substrate having a thin wall thickness of 1 mm or less and a low thermal expansion coefficient via a plurality of connecting conductors, the overall thickness is relatively thin, about 5 to 6 mm. The wiring board can be used, and a small space is required in the inspection process of the electronic component, and it can contribute to facilitating handling.
The shape of the ceramic layer forming the relay substrate in a plan view is arbitrary. For example, when an electronic component to be inspected is formed on a Si wafer, the entire circular shape of the Si wafer in a plan view is formed. In addition to a perfect circle that can cover, a regular polygon such as a regular hexagon, a regular octagon, or a regular dodecagon may be employed.

更に、本発明には、前記多層セラミック配線基板を形成する複数のセラミック層は、高温焼成セラミックまたは低温焼成セラミックからなる、電子部品検査装置用配線基板（請求項５）も含まれる。
これによれば、複数の接続導体を介して、前記中継基板の貫通導体および表・裏面の各パッドを介して、電子部品の各電極に電気信号を送信したり、逆に各電子部品から検査信号を受信し、内部の配線層で電圧の増幅や信号電流の整流などを施した後、裏面側パッドから外部回路基板などに出力することが可能となる。
尚、上記高温焼成セラミックは、例えばアルミナからなり、内部および表・裏面にＷまたはＭｏからなる配線層、ビア導体、およびパッドが形成され、一方、上記低温焼成セラミックは、例えばガラス−セラミックからなり、内部および表・裏面にＣｕまたはＡｇからなる配線層、ビア導体、およびパッドが形成される。 Furthermore, the present invention includes an electronic component inspection device wiring board (Claim 5) in which the plurality of ceramic layers forming the multilayer ceramic wiring board are made of a high-temperature fired ceramic or a low-temperature fired ceramic.
According to this, an electrical signal is transmitted to each electrode of the electronic component via the plurality of connecting conductors, the through conductors of the relay board and the pads on the front and back surfaces, or conversely, inspection is performed from each electronic component. After receiving the signal and performing voltage amplification and signal current rectification in the internal wiring layer, the signal can be output from the back surface side pad to an external circuit board or the like.
The high-temperature fired ceramic is made of alumina, for example, and wiring layers, via conductors, and pads made of W or Mo are formed on the inside, front and back surfaces, while the low-temperature fired ceramic is made of glass-ceramic, for example. A wiring layer made of Cu or Ag, a via conductor, and a pad are formed in the inside and front and back surfaces.

加えて、本発明には、前記接続導体は、前記中継基板の裏面に形成され且つ前記貫通導体と接続する裏面側パッド、前記多層セラミック配線基板の表面に形成され且つ前記配線層と導通する表面側パッド、およびこれら２つのパッドを接続するハンダからなる、電子部品検査装置用配線基板（請求項６）も含まれる。
これによれば、低熱膨張の前記中継基板とこれよりも高低熱膨張の多層セラミック配線基板とを、複数の接続導体を介して接合されため、両者間の熱膨張係数の差による影響を、かかる接続導体によって確実に吸収することが可能となる。従って、中継基板側のプローブと電子部品ごとの電極との電気的接続を確保できると共に、得られた信号を多層セラミック配線基板内の配線層で電気的処理などを行って、外部に確実に出力させることが可能となる。
尚、上記ハンダには、例えば、Ｓｎ−Ａｇ−Ｃｕ系合金からなるものが用いられる。 In addition, according to the present invention, the connection conductor is formed on the back surface of the relay substrate and is connected to the through conductor, and is formed on the surface of the multilayer ceramic wiring substrate and is electrically connected to the wiring layer. A wiring board for an electronic component inspection apparatus (Claim 6) comprising a side pad and solder for connecting these two pads is also included.
According to this, the low thermal expansion relay board and the higher and lower thermal expansion multilayer ceramic wiring board are joined via the plurality of connecting conductors, and therefore the influence of the difference in thermal expansion coefficient between the two is applied. It is possible to reliably absorb the connecting conductor. Therefore, the electrical connection between the probe on the relay board side and the electrode for each electronic component can be ensured, and the obtained signal can be reliably output to the outside by performing electrical processing on the wiring layer in the multilayer ceramic wiring board. It becomes possible to make it.
For example, a solder made of a Sn—Ag—Cu alloy is used as the solder.

一方、本発明の電子部品検査装置用配線基板の製造方法（請求項７）は、−４０〜＋１５０℃における熱膨張係数が３．０〜４．５×１０−６／℃のセラミック層となるグリーンシートを焼成して単一のセラミック層を形成し、該セラミック層の表面と裏面との間を貫通する複数の貫通導体を形成し、該貫通導体の両端面が露出する上記セラミック層の表・裏面ごとに複数のパッドを形成した後、複数の上記貫通導体およびパッドを加熱する、ことを含む中継基板を形成する工程と、複数のグリーンシートの表面と裏面との間を貫通する複数のビアホールごとにビア導体を形成し、上記複数のグリーンシートの表面および裏面の少なくとも一方に配線層またはパッドを形成し、かかる複数のグリーンシートを積層および焼成して、多層セラミック配線基板を形成する工程と、かかる多層セラミック配線基板の表面に形成した表面側パッドと、上記中継基板と多層セラミック配線基板との間において、中継基板の裏面に形成した裏面側パッドとを、ハンダを介して接続する工程と、を含む、ことを特徴とする。 On the other hand, the method for manufacturing a wiring board for an electronic component inspection apparatus according to the present invention (Claim 7) provides a ceramic layer having a thermal expansion coefficient of 3.0 to 4.5 × 10 −6 / ° C. at −40 to + 150 ° C. The ceramic sheet is formed by firing a green sheet to form a single ceramic layer, forming a plurality of through conductors penetrating between the front and back surfaces of the ceramic layer, and exposing both end faces of the through conductor. A step of forming a relay substrate including forming a plurality of pads for each back surface and then heating the plurality of through conductors and pads, and a plurality of holes penetrating between the front and back surfaces of the plurality of green sheets. A via conductor is formed for each via hole, a wiring layer or a pad is formed on at least one of the front and back surfaces of the plurality of green sheets, and the plurality of green sheets are laminated and fired to obtain a multilayer ceramic. Forming a wiring board, a surface-side pad formed on the surface of the multilayer ceramic wiring board, and a back-side pad formed on the back surface of the relay board between the relay board and the multilayer ceramic wiring board. And a step of connecting via solder.

これによれば、中継基板を形成する単一のセラミック層は、前記低熱膨張係数のグリーンシートを予め焼成した後、孔明け加工されて、複数の貫通孔を位置精度良く形成され、かかる貫通孔ごとに、ビア導体またはスルーホール導体の形態である貫通導体が形成される。かかる貫通導体と、当該セラミック層の表・裏面ごとに形成した複数のパッドとを加熱（キュア）するので、低熱膨張の中継基板の表面に複数のパッドが高い位置精度で形成される。そのため、かかるバッドごとに取り付けられるプローブと、Ｓｉウェハなどに多数形成された電子部品ごとの電極との電気的接続を、温度変化による影響を最少にして確保できる配線基板を確実に製造することが可能となる。しかも、各プローブから検出された信号は、複数の接続導体、および多層セラミック配線基板内の配線層を介して、裏面側パッドから外部に出力可能とした配線基板を提供可能となる。
また、本発明には、前記中継基板の表面に形成された複数の表面側パッド上に、検査すべき電子部品の電極と接触するプローブを取り付ける工程を更に有する、電子部品検査装置用配線基板の製造方法（請求項８）も含まれる。
これによれば、プローブが中継基板の表面側の各パッドごとに取り付けられるため、例えば、Ｓｉウェハに形成された多数の電子部品ごとの電極との確実な電気的接続が可能となる。従って、精度の高いプローブなどの検査装置を提供可能となる。 According to this, the single ceramic layer forming the relay substrate is pre-fired and then drilled to form a plurality of through holes with high positional accuracy. Each time, a through conductor in the form of a via conductor or a through-hole conductor is formed. Since the through conductor and the plurality of pads formed on the front and back surfaces of the ceramic layer are heated (cured), the plurality of pads are formed with high positional accuracy on the surface of the low thermal expansion relay substrate. Therefore, it is possible to reliably manufacture a wiring board that can secure the electrical connection between the probe attached to each pad and the electrode for each electronic component formed on a large number of Si wafers, etc., while minimizing the influence of temperature changes. It becomes possible. In addition, it is possible to provide a wiring board in which signals detected from each probe can be output to the outside from the back-side pad via a plurality of connection conductors and a wiring layer in the multilayer ceramic wiring board.
Moreover, the present invention further includes a step of attaching a probe that contacts an electrode of an electronic component to be inspected on a plurality of front surface pads formed on the surface of the relay substrate. A manufacturing method (claim 8) is also included.
According to this, since the probe is attached to each pad on the surface side of the relay substrate, for example, reliable electrical connection with electrodes for each of a large number of electronic components formed on the Si wafer is possible. Therefore, it is possible to provide an inspection apparatus such as a probe with high accuracy.

以下において、本発明を実施するための最良の形態について説明する。
図１は、本発明の電子部品検査装置用配線基板（以下、単に検査装置用配線基板という）１の断面およびその使用状態を示す概略図である。
検査装置用配線基板１は、図１に示すように、単一のセラミック層Ｓおよびその表面３と裏面４との間を複数のビア導体６が貫通する中継基板２と、かかる中継基板２の裏面４側に配置され、複数のセラミック層ｓ１〜ｓ４およびこれらの間に形成された配線層１３〜１５を含む多層セラミック基板１０と、これらの間を電気的に接続するハンダ１８を含む接続導体とを備えており、全体の厚みが約５〜６ｍｍである。
中継基板２を形成するセラミック層Ｓは、厚みが１ｍｍ以下のマシナブルセラミック、ＡｌＮ、またはムライトの何れかからなり、−４０〜＋１５０℃における熱膨張係数（以下、単にＣＴＥとする）が３．０〜４．５×１０−６／℃である。
尚、上記温度範囲におけるＡｌＮのＣＴＥは、約４．３×１０−６／℃、ムライトのＣＴＥは、約４．２×１０−６／℃である。また、上記マシナブルセラミックには、ＳｉＯ２とＡｌ２Ｏ３との混合物、あるいは、ＡｌＮとＢＮとの混合物からなり、これらのＣＴＥは、約４．５×１０−６／℃である。 In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a schematic view showing a cross section of a wiring board for an electronic component inspection apparatus (hereinafter, simply referred to as an inspection apparatus wiring board) 1 according to the present invention and a use state thereof.
As shown in FIG. 1, the inspection apparatus wiring board 1 includes a single ceramic layer S and a relay board 2 through which a plurality of via conductors 6 pass between the front surface 3 and the back surface 4, and the relay board 2. A multi-layer ceramic substrate 10 including a plurality of ceramic layers s1 to s4 and wiring layers 13 to 15 formed between the ceramic layers s1 to s4 and a connecting conductor including a solder 18 that electrically connects them. The total thickness is about 5 to 6 mm.
The ceramic layer S forming the relay substrate 2 is made of any one of machinable ceramic having a thickness of 1 mm or less, AlN, or mullite, and has a thermal expansion coefficient (hereinafter simply referred to as CTE) at −40 to + 150 ° C. It is 0-4.5x10 < -6 > / degreeC.
In addition, the CTE of AlN in the above temperature range is about 4.3 × 10 −6 / ° C., and the CTE of mullite is about 4.2 × 10 −6 / ° C. The machinable ceramic is made of a mixture of SiO 2 and Al 2 O 3 or a mixture of AlN and BN, and their CTE is about 4.5 × 10 −6 / ° C.

図１に示すように、中継基板２のセラミック層Ｓの表面３と裏面４との間には、複数の貫通孔５が穿孔され、これらの内部には、ビア導体と同様の貫通導体６が形成されている。尚、該貫通導体６は、各貫通孔５の内壁面に沿ったほぼ円筒形を呈し内部に金属または樹脂が充填されたスルーホール導体の形態としても良い。
各貫通導体６ごとの表面３および裏面４には、当該貫通導体６と接続された表面側パッド７および裏面側パッド８が形成されている。表面側パッド７ごとの上には、検査すべきＳｉウェハ２０に形成された多数の電子部品（図示せず）ごとの電極１９と接触し、これと電気的接続が可能なプローブ９が追って取り付けられる。尚、上記貫通導体６、表面側パッド７、および裏面側パッド８は、例えば、ＡｇまたはＣｕ、あるいはこれらの一方をベースとする合金からなる。 As shown in FIG. 1, a plurality of through holes 5 are drilled between the front surface 3 and the back surface 4 of the ceramic layer S of the relay substrate 2, and through conductors 6 similar to the via conductors are formed inside these. Is formed. The through conductor 6 may have a substantially cylindrical shape along the inner wall surface of each through hole 5 and may be a through hole conductor filled with metal or resin.
A front surface side pad 7 and a rear surface side pad 8 connected to the through conductor 6 are formed on the front surface 3 and the back surface 4 of each through conductor 6. A probe 9 that is in contact with the electrode 19 of each of a large number of electronic components (not shown) formed on the Si wafer 20 to be inspected and is electrically connected thereto is attached on the surface side pad 7 later. It is done. The through conductor 6, the front surface side pad 7, and the back surface side pad 8 are made of, for example, Ag or Cu, or an alloy based on one of them.

図１に示すように、多層セラミック基板１０は、例えば、アルミナ（高温焼成セラミック）またはガラス−セラミック（低温焼成セラミック）からなるセラミック層ｓ１〜ｓ４、これらの間に形成され且つ所要のパターンを有する配線層１３〜１５、セラミック層ｓ１の表面１１に形成された表面側パッド１６、セラミック層ｓ４の裏面１２に形成された裏面側パッド１７、およびこれらの導体間を接続するためセラミック層ｓ１〜ｓ４を貫通する複数のビア導体ｖを備えている。
更に、中継基板２の裏面側パッド８と多層セラミック基板１０の表面側パッド１６との間は、例えば、Ｓｎ−Ａｇ−Ｃｕ系合金からなるハンダ１８により接続されている。かかるハンダ１８、裏面側パッド８、および表面側パッド１６は、本発明の接続導体を形成し、これらを介して、中継基板２の貫通導体６および表面側パッド７と、多層セラミック基板１０の配線層１３〜１５、ビア導体ｖ、および裏面側パッド１７とが電気的に導通可能とされている。 As shown in FIG. 1, the multilayer ceramic substrate 10 has ceramic layers s1 to s4 made of, for example, alumina (high temperature fired ceramic) or glass-ceramic (low temperature fired ceramic), and a required pattern formed therebetween. The wiring layers 13 to 15, the front surface side pad 16 formed on the front surface 11 of the ceramic layer s1, the back surface side pad 17 formed on the rear surface 12 of the ceramic layer s4, and the ceramic layers s1 to s4 for connecting these conductors. And a plurality of via conductors v penetrating through.
Furthermore, the back surface side pad 8 of the relay substrate 2 and the front surface side pad 16 of the multilayer ceramic substrate 10 are connected by, for example, solder 18 made of Sn—Ag—Cu alloy. The solder 18, the back surface side pad 8, and the front surface side pad 16 form the connection conductor of the present invention, and through these, the through conductor 6 and the front surface side pad 7 of the relay substrate 2 and the wiring of the multilayer ceramic substrate 10. The layers 13 to 15, the via conductor v, and the back surface side pad 17 can be electrically connected.

以上のような検査装置用配線基板１によれば、複数の貫通導体６を有する前記中継基板２を形成する単層の前記セラミック層Ｓが、多数の電子部品を含むウェハを形成するＳｉの−４０〜＋１５０℃における熱膨張係数の約３×１０−６／℃と近似しているので、上記温度範囲における熱的変化を受けても、中継基板２の表面側パッド７に取り付けられる複数のプローブ９と、Ｓｉウェハ２０に形成された電子部品ごとの電極１９との電気的接続を確保することが容易となる。更に、前記中継基板２と多層セラミック基板１０とは、ハンダ１８を含む複数の接続導体を介して接合されため、両者間の熱膨張係数の差による影響を、かかる接続導体によって確実に吸収することが可能となる。このため、各プローブ９から検出された信号は、複数の接続導体、多層セラミック基板１内の配線層１３〜１５、およびビア導体ｖを介して、裏面側パッド１７から外部に出力可能となる。従って、直径が３００ｍｍ以上の大径であるＳｉウェハ２０に形成された電子部品であっても、その電気的特性を正確且つ確実に検査することが可能となる。
しかも、前記配線層１３などは、多層セラミック基板１０にのみ形成され、且つ中継基板２にはないため、検査すべき電子部品に応じて、中継基板２に対し形状変更などの設計変更を行うだけで、多層セラミック基板１０をそのまま用いるか、あるい大きな変更なしで容易に且つ短時間で対応することが可能となる。 According to the inspection apparatus wiring board 1 as described above, the single-layer ceramic layer S forming the relay substrate 2 having the plurality of through conductors 6 forms a wafer including a large number of electronic components. Since the thermal expansion coefficient at 40 to + 150 ° C. is approximately 3 × 10 −6 / ° C., a plurality of probes that are attached to the surface side pad 7 of the relay substrate 2 even when subjected to a thermal change in the above temperature range 9 and the electrode 19 of each electronic component formed on the Si wafer 20 can be easily secured. Further, since the relay substrate 2 and the multilayer ceramic substrate 10 are joined via a plurality of connecting conductors including the solder 18, the influence of the difference in thermal expansion coefficient between the two can be reliably absorbed by the connecting conductor. Is possible. For this reason, signals detected from the probes 9 can be output to the outside from the back surface side pad 17 via the plurality of connection conductors, the wiring layers 13 to 15 in the multilayer ceramic substrate 1 and the via conductors v. Therefore, even if the electronic component is formed on the Si wafer 20 having a large diameter of 300 mm or more, the electrical characteristics can be accurately and reliably inspected.
Moreover, since the wiring layer 13 and the like are formed only on the multilayer ceramic substrate 10 and not on the relay substrate 2, only the design change such as a shape change is performed on the relay substrate 2 according to the electronic component to be inspected. Thus, the multilayer ceramic substrate 10 can be used as it is, or can be handled easily and in a short time without any major change.

前記検査装置用配線基板１は、以下のような方法によって製造した。
予め、マシナブルセラミック（ＳｉＯ２とＡｌ２Ｏ３との混合物、または、ＡｌＮとＢＮとの混合物）、ＡｌＮ、あるいはムライトの粉末と、樹脂バインダと、溶剤などを所要量ずつ瓶量・混合してセラミックスラリを作成し、かかるセラミックスラリをドクターブレード法によって、厚みが約１ｍｍのグリーンシートを形成した。
次に、かかるグリーンシートを所定の温度で焼成して、図２の断面図で示すように、表面３および裏面４を有し、厚みｔが１ｍｍ以下で、且つ−４０〜＋１５０℃におけるＣＴＥが３．０〜４．５×１０−６／℃のセラミック層Ｓを得た。 The inspection device wiring board 1 was manufactured by the following method.
In advance, the required amount of machinable ceramic (a mixture of SiO 2 and Al 2 O 3 or a mixture of AlN and BN), AlN or mullite, a resin binder, a solvent, etc. is bottled and mixed in the required amounts. A ceramic slurry was prepared, and a green sheet having a thickness of about 1 mm was formed from the ceramic slurry by a doctor blade method.
Next, the green sheet is fired at a predetermined temperature, and as shown in the cross-sectional view of FIG. 2, the green sheet has a front surface 3 and a back surface 4, a thickness t is 1 mm or less, and CTE at −40 to + 150 ° C. A ceramic layer S of 3.0 to 4.5 × 10 −6 / ° C. was obtained.

次いで、上記セラミック層Ｓに対し、ドリルによる孔明け加工を行って、図３に示すように、その表面３と裏面４との間を貫通する複数の貫通孔５を形成した。
更に、上記セラミック層Ｓの各貫通孔５付近ごとに、無電解Ａｇメッキおよび電解Ａｇメッキ、あるいは無電解Ｃｕメッキおよび電解Ｃｕメッキを施して、図４に示すように、全体がほぼ円筒形のメッキ体６ａを複数個形成した。
次に、上記メッキ体６ａの中空部にＡｇ粉末またはＣｕ粉末を含む導電性ペーストを穴埋め・充填することで、図５に示すように、両端面がセラミック層Ｓの表・裏面３，４から僅かに突出する貫通導体６ｂを形成した。尚、上記メッキ体６ａの中空部には、樹脂を充填しても良い。 Next, the ceramic layer S was drilled with a drill to form a plurality of through holes 5 penetrating between the front surface 3 and the back surface 4 as shown in FIG.
Further, electroless Ag plating and electrolytic Ag plating, or electroless Cu plating and electrolytic Cu plating are applied to the vicinity of each through-hole 5 in the ceramic layer S so that the whole is substantially cylindrical as shown in FIG. A plurality of plated bodies 6a were formed.
Next, the hollow portion of the plated body 6a is filled and filled with a conductive paste containing Ag powder or Cu powder, so that both end surfaces are from the front and back surfaces 3, 4 of the ceramic layer S as shown in FIG. A slightly projecting through conductor 6b was formed. The hollow part of the plated body 6a may be filled with resin.

次いで、かかるセラミック層Ｓの表面３および裏面４を砥石またはベルトサンダーなどにより研磨して、図６に示すように、両端面が表・裏面３，４と面一の貫通導体６を各貫通孔５ごとに形成した。
尚、前記貫通孔５内に、Ａｇ粉末またはＣｕ粉末を含む導電性ペーストを直に印刷・充填して、貫通導体６を形成した後 、 上記同様の研磨を行っても良い。
更に、図７に示すように、セラミック層Ｓの表・裏面３，４で各貫通導体６の端面が露出する位置ごとに対し、Ａｇ粉末またはＣｕ粉末を含む導電性ペーストをスクリーン印刷して、表面側パッド７および裏面側パッド８を形成した。
そして、貫通導体６、表面側パッド７、および裏面側パッド８を所定の温度（約１５０〜２５０℃）で加熱（キュア）して、それぞれ硬化させた。
その結果、前記図１に示した中継基板２が得られた。 Next, the front surface 3 and the back surface 4 of the ceramic layer S are polished with a grindstone or a belt sander, and as shown in FIG. Formed every 5th.
In addition, after the conductive paste containing Ag powder or Cu powder is directly printed and filled in the through hole 5 to form the through conductor 6, the same polishing as described above may be performed.
Furthermore, as shown in FIG. 7, the conductive paste containing Ag powder or Cu powder is screen-printed for each position where the end face of each through conductor 6 is exposed on the front and back surfaces 3 and 4 of the ceramic layer S. The front surface side pad 7 and the back surface side pad 8 were formed.
Then, the through conductor 6, the front surface side pad 7, and the back surface side pad 8 were heated (cured) at a predetermined temperature (about 150 to 250 ° C.) to be cured.
As a result, the relay substrate 2 shown in FIG. 1 was obtained.

一方、アルミナ粉末と、樹脂バインダと、溶剤などを所要量ずつ瓶量・混合してセラミックスラリを作成し、かかるセラミックスラリをドクターブレード法によって、図８に示すように、厚みが約１００〜５００μｍのグリーンシートｇｓ１〜ｇｓ４を形成した。尚、上記アルミナ粉末に替えて、ガラス成分とアルミナ粉末とが重量比でほぼ４：６〜６：４のガラス−セラミック粉末を用いても良い。
次に、グリーンシートｇｓ１〜ｇｓ４における所定の位置に対し、パンチングを施して、図８に示すように、これらを貫通する複数のビアホールｈを形成した。
次いで、上記ビアホールｈごとの内部に、Ｗ粉末またはＭｏ粉末を含む導電性ペーストを印刷・充填して、図９に示すように、ビア導体ｖを形成した。 On the other hand, a ceramic slurry is prepared by mixing and mixing required amounts of alumina powder, resin binder, solvent, and the like, and the ceramic slurry is about 100 to 500 μm in thickness as shown in FIG. 8 by the doctor blade method. Green sheets gs1 to gs4 were formed. In addition, it may replace with the said alumina powder and you may use the glass-ceramic powder whose glass component and alumina powder are about 4: 6-6: 4 by weight ratio.
Next, the predetermined positions in the green sheets gs1 to gs4 were punched to form a plurality of via holes h penetrating them as shown in FIG.
Next, a conductive paste containing W powder or Mo powder was printed and filled inside each via hole h to form a via conductor v as shown in FIG.

更に、グリーンシートｇｓ１〜ｇｓ４の表面および裏面における少なくとも一方に対し、上記同様の導電性ペーストをスクリーン印刷して、図９に示すように、所定パターンの配線層１３〜１５と、表・裏面側パッド１６，１７とを形成した。この際、各ビア導体ｖは、同じグリーンシートｇｓ１〜ｇｓ４の配線層１３〜１５や表・裏面側パッド１６，１７と接続された。
尚、ガラス−セラミック粉末を含むグリーンシートｇｓ１〜ｇｓ４の場合には、Ａｇ粉末またはＣｕ粉末を含む導電性ペーストを用いた。
次に、ビア導体ｖ、配線層１３〜１５、表・裏面側パッド１６，１７が形成されたグリーンシートｇｓ１〜ｇｓ４を、積層および圧着して、図１０に示すように、未焼成の積層体ＳＳを得た。この際、各ビア導体ｖは、隣接するグリーンシートｇｓ２〜ｇｓ４の配線層１３〜１５と接続された。 Further, the conductive paste similar to the above is screen-printed on at least one of the front and back surfaces of the green sheets gs1 to gs4, and as shown in FIG. Pads 16 and 17 were formed. At this time, each via conductor v was connected to the wiring layers 13 to 15 and the front and back side pads 16 and 17 of the same green sheets gs1 to gs4.
In addition, in the case of the green sheets gs1-gs4 containing glass-ceramic powder, the electrically conductive paste containing Ag powder or Cu powder was used.
Next, the green sheets gs1 to gs4 on which the via conductors v, the wiring layers 13 to 15 and the front and back pads 16 and 17 are formed are laminated and pressure-bonded, and as shown in FIG. SS was obtained. At this time, each via conductor v was connected to the wiring layers 13 to 15 of the adjacent green sheets gs2 to gs4.

そして、かかる積層体を所定の温度（約８００〜１０００℃）で焼成した。
その結果、全体の厚みが約３〜５ｍｍである前記図１に示した多層セラミック基板１０が得られた。
次いで、図１１に示すように、多層セラミック基板１０の表面１１側と、中継基板２の裏面４側との間において、前者の表面側パッド１６ごとの上に、Ｓｎ−Ａｇ−Ｃｕ系合金からなるほぼボール形状のハンダ１８（図示せず）を載せた後、その融点よりもやや上の温度帯で加熱した。尚、中継基板２の裏面側パッド８ごとの上に上記ハンダ１８を載せ、且つそれらの上に多層セラミック基板１０の各表面側パッド１６を載置させた後、上記同様に加熱しても良い。 And this laminated body was baked at predetermined | prescribed temperature (about 800-1000 degreeC).
As a result, the multilayer ceramic substrate 10 shown in FIG. 1 having an overall thickness of about 3 to 5 mm was obtained.
Next, as shown in FIG. 11, between the surface 11 side of the multilayer ceramic substrate 10 and the back surface 4 side of the relay substrate 2, the Sn—Ag—Cu-based alloy is formed on each former surface side pad 16. After mounting a substantially ball-shaped solder 18 (not shown), it was heated in a temperature range slightly above its melting point. The solder 18 may be placed on each back surface side pad 8 of the relay substrate 2 and each surface side pad 16 of the multilayer ceramic substrate 10 may be placed thereon, and then heated in the same manner as described above. .

その結果、図１２に示すように、ハンダ１８を介して裏・表面側パッド８，１６が接合され、これらからなる複数の接続導体を介して、中継基板２と多層セラミック基板１０とが接合された本発明の検査装置用配線基板１を得ることができた。同時に、中継基板２の貫通導体６および表面側パッド７と、多層セラミック基板１０の配線層１３〜１５，ビア導体ｖ，および裏面側パッド１７とが電気的に導通可能となった。
そして、中継基板２の各表面側パッド７ごと上に、プローブ９を取り付けることで、電子部品検査装置の要部を形成することができた。尚、多層セラミック基板１０の裏面側パッド１７に対し、更に外部回路基板（図示せず）を接続することで、プローブカードなどの電子部品検査装置を形成することも可能である。 As a result, as shown in FIG. 12, the back and front side pads 8 and 16 are joined via the solder 18, and the relay substrate 2 and the multilayer ceramic substrate 10 are joined via a plurality of connecting conductors composed of these. In addition, the wiring board 1 for an inspection apparatus of the present invention was obtained. At the same time, the through conductor 6 and the front surface side pad 7 of the relay substrate 2 can be electrically connected to the wiring layers 13 to 15, the via conductor v, and the back surface side pad 17 of the multilayer ceramic substrate 10.
And the principal part of the electronic component inspection apparatus was able to be formed by attaching the probe 9 on each surface side pad 7 of the relay substrate 2. Note that an electronic circuit inspection device such as a probe card can be formed by further connecting an external circuit board (not shown) to the back surface side pad 17 of the multilayer ceramic substrate 10.

以上のような検査装置用配線基板１の製造方法によれば、中継基板２を形成する単一のセラミック層Ｓは、前記低熱膨張係数のグリーンシートを予め焼成した後、孔明け加工されて、複数の貫通孔ｈを位置精度良く形成され、かかる貫通孔ｈごとに、ビア導体またはスルーホール導体の形態である貫通導体６が形成されている。かかる貫通導体６と、当該セラミック層Ｓの表・裏面３，４ごとに形成した複数のパッド７，８とを加熱（キュア）するので、低熱膨張の中継基板２の表面３に複数のパッド７を高い位置精度にて形成できる。そのため、かかるバッド７ごとに取り付けられるプローブ９と、Ｓｉウェハ２０に多数形成された電子部品ごとの電極１９との電気的接続を、温度変化による影響を最少にして確保できる検査装置用配線基板１を確実に製造することが可能となる。しかも、各プローブ９から検出された信号は、複数の接続導体１８、および多層セラミック基板１０内の配線層１３〜１５などを介して、その裏面側パッド１７から外部に出力可能とした検査装置用配線基板１を確実に提供することが可能となる。   According to the manufacturing method of the wiring board 1 for an inspection apparatus as described above, the single ceramic layer S forming the relay substrate 2 is pre-fired after the low thermal expansion coefficient green sheet is fired, A plurality of through holes h are formed with high positional accuracy, and a through conductor 6 in the form of a via conductor or a through hole conductor is formed for each through hole h. Since the through conductor 6 and the plurality of pads 7 and 8 formed for the front and back surfaces 3 and 4 of the ceramic layer S are heated (cured), the plurality of pads 7 are formed on the surface 3 of the low thermal expansion relay substrate 2. Can be formed with high positional accuracy. Therefore, the wiring board 1 for an inspection apparatus that can secure the electrical connection between the probe 9 attached to each pad 7 and the electrode 19 for each electronic component formed on the Si wafer 20 with the least influence of temperature change. Can be reliably manufactured. Moreover, the signals detected from each probe 9 can be output to the outside from the back surface side pad 17 through the plurality of connection conductors 18 and the wiring layers 13 to 15 in the multilayer ceramic substrate 10. It is possible to reliably provide the wiring board 1.

本発明は、前記形態に限られるでものはない。
例えば、前記中継基板２におけるセラミック層Ｓの表面３および裏面４には、表面側パッド７，７間、あるいは裏面側パッド８，８間を接続する配線を形成しても良い。
また、前記接続導体のハンダ１８は、Ｓｎ−Ａｇ系、Ｓｎ−Ｃｕ系、Ｓｎ−Ｚｎ系合金からなるものとしても良い。
更に、前記中継基板２と多層セラミック配線基板１０との間には、かかる位置に形成した複数の前記接続導体であるハンダ１８の周囲を包囲するように、封止用の樹脂またはガラスを充填することも可能である。
また、前記多層セラミック配線基板１０のセラミック層ｓ１〜ｓ４は、ムライト、ＡｌＮなどの高温焼成セラミックによって形成しても良い。
加えて、前記多層セラミック配線基板１０は、その裏面１２側に開口するキャビティを形成し、かかるキャビティ内に各種の電子部品を実装することも可能である。 The present invention is not limited to the above embodiment.
For example, the front surface 3 and the back surface 4 of the ceramic layer S in the relay substrate 2 may be formed with wirings connecting the front surface pads 7 and 7 or between the back surface pads 8 and 8.
The connecting conductor solder 18 may be made of Sn—Ag, Sn—Cu, or Sn—Zn alloy.
Further, a resin or glass for sealing is filled between the relay substrate 2 and the multilayer ceramic wiring substrate 10 so as to surround the periphery of the solder 18 that is the plurality of connection conductors formed at such positions. It is also possible.
Further, the ceramic layers s1 to s4 of the multilayer ceramic wiring board 10 may be formed of a high-temperature fired ceramic such as mullite or AlN.
In addition, the multilayer ceramic wiring board 10 can have a cavity opened on the back surface 12 side, and various electronic components can be mounted in the cavity.

本発明の電子部品検査装置用配線基板などを示す断面図。Sectional drawing which shows the wiring board for electronic component inspection apparatuses of this invention. 前記中継基板を得るための一製造工程を示す概略断面図。FIG. 6 is a schematic cross-sectional view showing one manufacturing process for obtaining the relay substrate. 図２に続く製造工程を示す概略断面図。FIG. 3 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 2. 図３に続く製造工程を示す概略断面図。FIG. 4 is a schematic cross-sectional view showing a manufacturing process following FIG. 3. 図４に続く製造工程を示す概略断面図。FIG. 5 is a schematic cross-sectional view showing a manufacturing process following FIG. 4. 図５に続く製造工程を示す概略断面図。FIG. 6 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 5. 図６に続く製造工程を示す概略断面図。FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 6. 前記多層セラミック配線基板の一製造工程を示す概略断面図。FIG. 3 is a schematic cross-sectional view showing one manufacturing process of the multilayer ceramic wiring board. 図８に続く製造工程を示す概略断面図。FIG. 9 is a schematic cross-sectional view showing a manufacturing process following FIG. 8. 図９に続く製造工程を示す概略断面図。FIG. 10 is a schematic cross-sectional view showing a manufacturing process following FIG. 9. 前記検査装置用配線基板を得るための一製造工程を示す概略断面図。FIG. 5 is a schematic cross-sectional view showing one manufacturing process for obtaining the inspection apparatus wiring board. 図１１に続く製造工程を示す概略断面図。FIG. 12 is a schematic cross-sectional view showing a manufacturing process following FIG. 11.

符号の説明Explanation of symbols

１…………………………電子部品検査装置用配線基板
２…………………………中継基板
３，１１…………………表面
４…………………………裏面
６…………………………貫通導体
７，１６…………………表面側パッド
８…………………………裏面側パッド
９…………………………プローブ
１０………………………多層セラミック配線基板
１３〜１５………………配線層
１８………………………ハンダ（接続導体）
１９………………………電極
２０………………………Ｓｉウェハ（電子部品）
ｖ…………………………ビア導体
Ｓ，ｓ１〜ｓ４…………セラミック層
ｇｓ１〜ｇｓ４…………グリーンシート 1 ………………………… Wiring board for electronic component inspection equipment 2 ………………………… Relay board 3, 11 ………………… Surface 4 ………………… ……… Back 6 ………………………… Penetration conductor 7, 16 ………………… Front side pad 8 ………………………… Back side pad 9 …………… …………… Probe 10 ……………………… Multilayer Ceramic Wiring Board 13 ~ 15 ……………… Wiring Layer 18 ……………………… Solder (Connection Conductor)
19 …………………… Electrode 20 ……………………… Si wafer (electronic parts)
v ………………………… Via conductor S, s1-s4 ………… Ceramic layer gs1-gs4 ………… Green sheet

Claims (8)

単層で且つ−４０〜＋１５０℃における熱膨張係数が３．０〜４．５×１０−６／℃のセラミック層、および該セラミック層の表面と裏面との間を貫通する複数の貫通導体を有する中継基板と、
上記中継基板の裏面側に配置され、複数のセラミック層、該セラミック層の間に形成された配線層、および上記複数のセラミック層を貫通して前記配線層の間を導通するビア導体を含む多層セラミック配線基板と、
上記中継基板と多層セラミック配線基板との間に配置され、上記中継基板の複数の貫通導体と上記多層セラミック配線基板の配線層とを電気的に導通する複数の接続導体と、を含む、
ことを特徴とする電子部品検査装置用配線基板。 A ceramic layer having a single layer and a thermal expansion coefficient of 3.0 to 4.5 × 10 −6 / ° C. at −40 to + 150 ° C., and a plurality of through conductors penetrating between the front surface and the back surface of the ceramic layer Having a relay board;
A multilayer including a plurality of ceramic layers, a wiring layer formed between the ceramic layers, and a via conductor that passes through the plurality of ceramic layers and is conducted between the wiring layers, disposed on the back side of the relay substrate. A ceramic wiring board;
A plurality of connecting conductors disposed between the relay board and the multilayer ceramic wiring board and electrically conducting the plurality of through conductors of the relay board and the wiring layer of the multilayer ceramic wiring board;
A wiring board for an electronic component inspection apparatus. 前記中継基板のセラミック層は、マシナブルセラミック、ＡｌＮ、またはムライトの何れかからなる、
ことを特徴とする請求項１に記載の電子部品検査装置用配線基板。 The ceramic layer of the relay substrate is made of either machinable ceramic, AlN, or mullite.
The wiring board for an electronic component inspection apparatus according to claim 1. 前記マシナブルセラミックは、ＳｉＯ２とＡｌ２Ｏ３との混合物、あるいは、ＡｌＮとＢＮとの混合物である、
ことを特徴とする請求項２に記載の電子部品検査装置用配線基板。 The machinable ceramic is a mixture of SiO 2 and Al 2 O 3 or a mixture of AlN and BN.
The wiring board for an electronic component inspection apparatus according to claim 2. 前記中継基板を形成するセラミック層の厚みは、１ｍｍ以下である、
ことを特徴とする請求項１乃至３の何れか一項に記載の電子部品検査装置用配線基板。 The thickness of the ceramic layer forming the relay substrate is 1 mm or less.
The wiring board for an electronic component inspection apparatus according to any one of claims 1 to 3. 前記多層セラミック配線基板を形成する複数のセラミック層は、高温焼成セラミックまたは低温焼成セラミックからなる、
ことを特徴とする請求項１乃至４の何れか一項に記載の電子部品検査装置用配線基板。 The plurality of ceramic layers forming the multilayer ceramic wiring board are made of a high-temperature fired ceramic or a low-temperature fired ceramic.
The wiring board for an electronic component inspection apparatus according to any one of claims 1 to 4, wherein: 前記接続導体は、前記中継基板の裏面に形成され且つ前記貫通導体と接続する裏面側パッド、前記多層セラミック配線基板の表面に形成され且つ前記配線層と導通する表面側パッド、およびこれら２つのパッドを接続するハンダからなる、
ことを特徴とする請求項１乃至５の何れか一項に記載の電子部品検査装置用配線基板。 The connection conductor is formed on the back surface of the relay substrate and connected to the through conductor, the back surface side pad formed on the surface of the multilayer ceramic wiring substrate and connected to the wiring layer, and these two pads Consisting of solder connecting,
The wiring board for an electronic component inspection apparatus according to any one of claims 1 to 5. −４０〜＋１５０℃における熱膨張係数が３．０〜４．５×１０−６／℃のセラミック層となるグリーンシートを焼成して単一のセラミック層を形成し、該セラミック層の表面と裏面との間を貫通する複数の貫通導体を形成し、該貫通導体の両端面が露出する上記セラミック層の表・裏面ごとに複数のパッドを形成した後、複数の上記貫通導体およびパッドを加熱する、ことを含む中継基板を形成する工程と、
複数のグリーンシートの表面と裏面との間を貫通する複数のビアホールごとにビア導体を形成し、上記複数のグリーンシートの表面および裏面の少なくとも一方に配線層またはパッドを形成し、かかる複数のグリーンシートを積層および焼成して、多層セラミック配線基板を形成する工程と、
上記中継基板と多層セラミック配線基板との間において、上記多層セラミック配線基板の表面に形成した表面側パッドと、中継基板の裏面に形成した裏面側パッドとを、ハンダを介して接続する工程と、を含む
ことを特徴とする電子部品検査装置用配線基板の製造方法。 A green sheet serving as a ceramic layer having a thermal expansion coefficient at −40 to + 150 ° C. of 3.0 to 4.5 × 10 −6 / ° C. is fired to form a single ceramic layer, and the front and back surfaces of the ceramic layer And forming a plurality of pads for each of the front and back surfaces of the ceramic layer where both end faces of the through conductor are exposed, and then heating the plurality of through conductors and pads. A step of forming a relay substrate including:
A via conductor is formed for each of a plurality of via holes penetrating between the front and back surfaces of the plurality of green sheets, and a wiring layer or a pad is formed on at least one of the front and back surfaces of the plurality of green sheets. Laminating and firing the sheets to form a multilayer ceramic wiring board;
Between the relay substrate and the multilayer ceramic wiring substrate, connecting a front surface side pad formed on the surface of the multilayer ceramic wiring substrate and a back surface side pad formed on the back surface of the relay substrate via solder; The manufacturing method of the wiring board for electronic component inspection apparatuses characterized by these. 前記中継基板の表面に形成された複数の表面側パッド上に、検査すべき電子部品の電極と接触するプローブを取り付ける工程を更に有する、
ことを特徴とする請求項７に記載の電子部品検査装置用配線基板の製造方法。 A step of attaching a probe in contact with an electrode of an electronic component to be inspected on a plurality of surface side pads formed on the surface of the relay substrate;
The method for manufacturing a wiring board for an electronic component inspection apparatus according to claim 7.
JP2007241867A 2007-09-19 2007-09-19 Wiring board for electronic component inspection device, and its manufacturing method Pending JP2009074823A (en)

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010027075A1 (en) * 2008-09-05 2010-03-11 日本発條株式会社 Wiring board and probe card
KR101018097B1 (en) 2009-04-29 2011-02-25 삼성전기주식회사 Method for Manufacturing of Probe Board
JP2011159826A (en) * 2010-02-01 2011-08-18 Nhk Spring Co Ltd Machinable ceramic circuit board and method for manufacturing the same
JP2012141274A (en) * 2010-12-29 2012-07-26 Samsung Electro-Mechanics Co Ltd Ceramic substrate for probe card and manufacturing method thereof
JP2012141275A (en) * 2010-12-29 2012-07-26 Samsung Electro-Mechanics Co Ltd Ceramic substrate for probe card and manufacturing method thereof
JP2013024622A (en) * 2011-07-19 2013-02-04 Ngk Spark Plug Co Ltd Wiring board for electronic component inspection device and method for manufacturing the same
US9049786B2 (en) 2011-04-01 2015-06-02 Ngk Spark Plug Co., Ltd. Ceramic substrate and method for manufacturing the same
KR20160064072A (en) 2013-09-30 2016-06-07 니폰 덴키 가라스 가부시키가이샤 Ceramic wiring substrate, ceramic green sheet for ceramic wiring substrate, and glass ceramic powder for ceramic wiring substrate
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KR20200051486A (en) 2018-11-05 2020-05-13 니혼도꾸슈도교 가부시키가이샤 Wiring board
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US10834818B2 (en) 2018-11-05 2020-11-10 Ngk Spark Plug Co., Ltd. Wiring board
KR20220044733A (en) 2019-08-06 2022-04-11 니폰 덴키 가라스 가부시키가이샤 Ceramic wiring board, ceramic green sheet for ceramic wiring board and glass ceramic powder for ceramic wiring board
KR20230133865A (en) 2021-01-15 2023-09-19 니폰 덴키 가라스 가부시키가이샤 Ceramic substrate, green sheet for ceramic substrate and composite powder for ceramic substrate

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127122A (en) * 1999-10-29 2001-05-11 Mitsui Kozan Material Kk Component for insulatively fixing probe
JP2002313854A (en) * 2002-04-04 2002-10-25 Matsushita Electric Ind Co Ltd Probe card for full wafer measurement and inspection and its manufacturing method
JP2003203954A (en) * 1999-11-18 2003-07-18 Ibiden Co Ltd Inspection apparatus and probe card
JP2005119941A (en) * 2003-09-25 2005-05-12 Sumitomo Metal Ind Ltd Free-cutting ceramic, its production method, and probe guiding part
JP2006080199A (en) * 2004-09-08 2006-03-23 Ibiden Co Ltd Electric relay plate
JP2006284541A (en) * 2005-04-05 2006-10-19 Kyocera Corp Measuring wiring substrate, probe card, and evaluation device
JP2007173862A (en) * 2003-06-24 2007-07-05 Ngk Spark Plug Co Ltd Structure comprising relay substrate, relay substrate with semiconductor element, substrate with relay substrate, and structure composed of semiconductor element, relay substrate, and substrate

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127122A (en) * 1999-10-29 2001-05-11 Mitsui Kozan Material Kk Component for insulatively fixing probe
JP2003203954A (en) * 1999-11-18 2003-07-18 Ibiden Co Ltd Inspection apparatus and probe card
JP2002313854A (en) * 2002-04-04 2002-10-25 Matsushita Electric Ind Co Ltd Probe card for full wafer measurement and inspection and its manufacturing method
JP2007173862A (en) * 2003-06-24 2007-07-05 Ngk Spark Plug Co Ltd Structure comprising relay substrate, relay substrate with semiconductor element, substrate with relay substrate, and structure composed of semiconductor element, relay substrate, and substrate
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JP2020134396A (en) * 2019-02-22 2020-08-31 日本特殊陶業株式会社 Substrate for electric inspection
KR20220044733A (en) 2019-08-06 2022-04-11 니폰 덴키 가라스 가부시키가이샤 Ceramic wiring board, ceramic green sheet for ceramic wiring board and glass ceramic powder for ceramic wiring board
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