JP2009064825A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2009064825A
JP2009064825A JP2007229194A JP2007229194A JP2009064825A JP 2009064825 A JP2009064825 A JP 2009064825A JP 2007229194 A JP2007229194 A JP 2007229194A JP 2007229194 A JP2007229194 A JP 2007229194A JP 2009064825 A JP2009064825 A JP 2009064825A
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semiconductor device
semiconductor substrate
impurity diffusion
back surface
diffusion region
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Takeshi Fukami
武志 深見
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Toyota Motor Corp
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Priority to PCT/IB2008/002268 priority patent/WO2009031001A2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing the occurrence of punch through caused by a flaw, or the like during a manufacturing process in a vertical semiconductor device. <P>SOLUTION: The semiconductor device 100 that is a vertical IGBT includes a collector electrode 2, a p<SP>+</SP>-type collector layer 4, an n<SP>+</SP>-type buffer layer 6, an n<SP>-</SP>-type drift layer 8, a p-type body region 10, an n<SP>+</SP>-type emitter region 12, a gate electrode 18, and an emitter electrode 14. There is an irregular shape 32 comprising a recess 28 and a projection 30 on the backside of the semiconductor device 100. An interval L2 between the bottom surfaces of the adjacent recesses 28 is not more than 0.7 times larger than the thickness L1 of the buffer layer 6, thus forming the buffer layer 6 successively in depth separated from the bottom surface of the recess by a fixed distance. The buffer layer 6 can be formed at a deep position from a back contact surface, thus suppressing the occurrence of a punch through phenomenon caused by the flaw, or the like during the manufacturing process. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置とその製造方法に関する。特に、半導体基板の表面に表面電極が形成されており、半導体基板の裏面に裏面電極が形成されている縦型の半導体装置とその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a vertical semiconductor device in which a surface electrode is formed on the surface of a semiconductor substrate and a back electrode is formed on the back surface of the semiconductor substrate, and a manufacturing method thereof.

縦型の半導体装置の開発が進められている。半導体装置の製造工程では、製造工程中に、製造装置との接触などによって生じる傷が半導体基板の裏面についてしまうことがある。このような傷が、縦型半導体装置の裏面に形成されている不純物拡散領域を貫通すると、パンチスルー現象が発生する。その結果、縦型半導体装置の耐圧が低下する。   Vertical semiconductor devices are being developed. In the manufacturing process of a semiconductor device, scratches caused by contact with the manufacturing apparatus or the like may occur on the back surface of the semiconductor substrate during the manufacturing process. When such a scratch penetrates the impurity diffusion region formed on the back surface of the vertical semiconductor device, a punch-through phenomenon occurs. As a result, the breakdown voltage of the vertical semiconductor device is reduced.

半導体基板の裏面側に形成されている不純物拡散領域を貫通する傷によるパンチスルー現象の発生を低減する縦型半導体装置の製造方法が提案されている。この製造方法では、表面電極の形成後、製造工程の終盤で半導体基板の裏面側に不純物拡散領域を形成する。不純物拡散領域の形成前に裏面についた傷は不純物拡散領域によってその表面が覆われる。また、裏面に不純物拡散領域を形成した後に半導体基板と製造装置が接触する回数が減るため、裏面に傷がつく可能性が低減される。その結果、裏面についた傷によるパンチスルー現象の発生が低減される。このような半導体装置が特許文献１等に開示されている。   There has been proposed a method for manufacturing a vertical semiconductor device that reduces the occurrence of a punch-through phenomenon due to scratches penetrating an impurity diffusion region formed on the back side of a semiconductor substrate. In this manufacturing method, after the front surface electrode is formed, an impurity diffusion region is formed on the back surface side of the semiconductor substrate at the end of the manufacturing process. The surface of the scratch on the back surface before the impurity diffusion region is formed is covered with the impurity diffusion region. In addition, since the number of times the semiconductor substrate and the manufacturing apparatus are in contact with each other after the impurity diffusion region is formed on the back surface is reduced, the possibility that the back surface is damaged is reduced. As a result, the occurrence of a punch-through phenomenon due to scratches on the back surface is reduced. Such a semiconductor device is disclosed in Patent Document 1 and the like.

特開２００３−５１５９７号公報JP 2003-51597 A

しかしながら、上記の製造方法によっても、半導体基板の裏面に不純物拡散領域を形成した後に、傷がつくことを抑制しきれない。不純物拡散領域を貫通する傷がついてしまえば、パンチスルー現象の発生を抑制することができない。   However, even with the above-described manufacturing method, it is not possible to suppress damage after the impurity diffusion region is formed on the back surface of the semiconductor substrate. If there is a scratch penetrating the impurity diffusion region, the occurrence of the punch-through phenomenon cannot be suppressed.

本発明は、上記の課題を解決する。本発明の半導体装置は、裏面に不純物拡散領域を形成した後に、不純物拡散領域を貫通する傷がつくことを抑制できる技術を提供する。
本発明は、製造工程中についた傷などによってパンチスルー現象が発生することを抑制できる半導体装置を提供することを目的とする。またそのような半導体装置の製造方法を提供することをも目的とする。 The present invention solves the above problems. The semiconductor device of the present invention provides a technique capable of suppressing the scratches penetrating the impurity diffusion region after forming the impurity diffusion region on the back surface.
An object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of a punch-through phenomenon due to scratches or the like attached during a manufacturing process. It is another object of the present invention to provide a method for manufacturing such a semiconductor device.

本発明は、半導体基板の表面に表面電極が形成されており、半導体基板の裏面に裏面電極が形成されている縦型の半導体装置に関する。
本発明の半導体装置は、半導体基板の裏面に、凹部底面が平坦な凹凸形状が形成されている。凸部表面は平坦であってもよいし、平坦でなくてもよい。
本発明の半導体装置では、凹部底面から一定距離だけ隔てた深さの半導体基板内に、不純物拡散領域が形成されている。
本発明の半導体装置は、隣接する凹部底面同士の間隔が、不純物拡散領域の厚みの０．７倍以下であり、隣接する凹部底面同士の間隔において、不純物拡散領域が凹部底面から一定距離だけ隔てた深さにおいて連続している。 The present invention relates to a vertical semiconductor device in which a surface electrode is formed on the surface of a semiconductor substrate and a back electrode is formed on the back surface of the semiconductor substrate.
In the semiconductor device of the present invention, an uneven shape having a flat bottom surface of the recess is formed on the back surface of the semiconductor substrate. The convex surface may be flat or may not be flat.
In the semiconductor device of the present invention, an impurity diffusion region is formed in a semiconductor substrate having a depth separated from the bottom surface of the recess by a certain distance.
In the semiconductor device of the present invention, the interval between the bottom surfaces of the adjacent recesses is 0.7 times or less the thickness of the impurity diffusion region, and the impurity diffusion region is separated from the bottom surface of the recess by a certain distance in the interval between the bottom surfaces of the adjacent recesses. Continuous in depth.

凹部底面から一定距離だけ隔てた深さの半導体基板内には、不純物が縦方向又は横方向へ拡散することによって不純物拡散領域が形成される。本発明者は、隣接する凹部底面同士の間隔が、不純物拡散領域の厚みの０．７倍より大きいと、裏面が凸部になっている部分では凹部底面から一定距離だけ隔てた深さにおいて不純物拡散領域が不連続となるのに対し、隣接する凹部底面同士の間隔が、不純物拡散領域の厚みの０．７倍以下であると、裏面が凸部になっている部分でも凹部底面から一定距離だけ隔てた深さにおいて不純物拡散領域が連続して形成されることを見出した。後者の場合、凹部底面から凸部表面までの距離をＡとし、凹部底面から不純物拡散領域までの距離をＢとしたときに、凸部表面から距離Ａ＋Ｂだけ隔てた深さに不純物拡散領域が形成される。   An impurity diffusion region is formed by diffusing impurities in the vertical direction or the horizontal direction in the semiconductor substrate having a depth separated from the bottom surface of the recess by a certain distance. The present inventor has found that when the distance between the bottom surfaces of adjacent recesses is larger than 0.7 times the thickness of the impurity diffusion region, the impurity is formed at a depth separated by a certain distance from the bottom surface of the recess in the portion where the back surface is a protrusion. While the diffusion region is discontinuous, if the distance between adjacent concave bottom surfaces is 0.7 times or less the thickness of the impurity diffusion region, a certain distance from the concave bottom surface even when the back surface is a convex portion It has been found that impurity diffusion regions are continuously formed at a depth separated by a distance. In the latter case, when the distance from the bottom surface of the concave portion to the surface of the convex portion is A and the distance from the bottom surface of the concave portion to the impurity diffusion region is B, the impurity diffusion region is formed at a depth separated from the surface of the convex portion by the distance A + B. Is done.

仮に凹凸形状が形成されていなければ、裏面から距離Ｂだけ隔てた深さに不純物拡散領域が形成され、深さＢ以上の傷がつけばパンチスルー現象が発生する。それに対し、本発明は凸部表面に傷がついても、その深さがＡ＋Ｂ以上でなければパンチスルー現象は発生しない。Ａの高さを確保することによって、傷によってパンチスルー現象が発生することを防止できる。凹部底面では、深さＢに不純物拡散領域が存在しており、深さＢ以上の傷がつけばパンチスルー現象が発生する可能性がある。しかしながら、凹部底面は窪んでおり、製造装置等と直接接触する可能性が低く、傷がつきにくい。傷がつきやすい凸部では不純物拡散領域が深い位置に存在しているので、傷によってパンチスルー現象が発生する可能性が低く抑えられ、不純物拡散領域が浅い位置に存在する凹部底面には傷がつきにくい。このようにして、本発明の半導体装置では、傷によってパンチスルー現象が発生する可能性を低く抑えることができる。   If the irregular shape is not formed, the impurity diffusion region is formed at a depth separated by a distance B from the back surface, and a punch-through phenomenon occurs if a scratch of depth B or more is formed. On the other hand, in the present invention, even if the surface of the convex portion is scratched, the punch-through phenomenon does not occur unless the depth is A + B or more. By ensuring the height of A, it is possible to prevent the punch-through phenomenon from occurring due to scratches. On the bottom surface of the recess, there is an impurity diffusion region at a depth B, and if there is a scratch of depth B or more, a punch-through phenomenon may occur. However, the bottom surface of the recess is recessed, and the possibility of direct contact with a manufacturing apparatus or the like is low and scratches are difficult to occur. Since the impurity diffusion region exists at a deep position in a convex part that is easily scratched, the possibility of punch-through phenomenon occurring due to the scratch is kept low, and the bottom surface of the concave part where the impurity diffusion region exists at a shallow position is scratched. Hard to stick. In this way, in the semiconductor device of the present invention, the possibility of the punch-through phenomenon occurring due to scratches can be kept low.

本発明の半導体装置は、凹部底面と凸部側面が鈍角をなしており、裏面電極が、半導体基板の裏面全体に形成されていることが好ましい。
凹凸形状が上記の形状になっていると、凸部の側面にも裏面電極を形成することができる。半導体基板の裏面全体に裏面電極を形成することができる。その結果、裏面電極の電極面積が増加し、接触抵抗を低減することができる。パンチスルーの発生を抑制できるとともに、接触抵抗を低減することができる。 In the semiconductor device of the present invention, it is preferable that the bottom surface of the recess and the side surface of the protrusion have an obtuse angle, and the back electrode is formed on the entire back surface of the semiconductor substrate.
When the concavo-convex shape is the above shape, the back electrode can be formed also on the side surface of the convex portion. A back electrode can be formed on the entire back surface of the semiconductor substrate. As a result, the electrode area of the back electrode increases, and the contact resistance can be reduced. The occurrence of punch-through can be suppressed and the contact resistance can be reduced.

本発明は、特に、ＩＧＢＴである半導体装置に適している。
この場合、不純物拡散領域が、コレクタ層とドリフト層を分離するバッファ層を形成している。この場合、バッファ層が、半導体基板の裏面の凹凸形状に関わらず、凹部底面から一定距離だけ隔てた深さを連続して伸びていることが好ましい。
この場合、コレクタ層は、凹部底面から一定距離だけ隔てた深さを不連続に伸びていてもよい。コレクタ層が不連続に形成されていると、コレクタ電極から過剰なキャリアが供給されるのを抑制することができる。その結果、ターンオフ時にキャリアが残留することを抑制することができる。ターンオフに至るまでの時間を短縮することができる。
なお、本明細書でいう不純物拡散領域とは、ドリフト層と同型の不純物をドリフト層よりも高濃度に拡散した領域のことをいう。ＩＧＢＴの場合、本明細書でいう不純物拡散領域とはバッファ層のことをいう。 The present invention is particularly suitable for a semiconductor device that is an IGBT.
In this case, the impurity diffusion region forms a buffer layer that separates the collector layer and the drift layer. In this case, it is preferable that the buffer layer continuously extends a depth separated by a certain distance from the bottom surface of the recess regardless of the uneven shape of the back surface of the semiconductor substrate.
In this case, the collector layer may extend discontinuously at a depth separated from the bottom surface of the recess by a certain distance. When the collector layer is formed discontinuously, supply of excess carriers from the collector electrode can be suppressed. As a result, it is possible to suppress carriers from remaining at the time of turn-off. The time to turn off can be shortened.
Note that the impurity diffusion region in this specification refers to a region in which impurities of the same type as the drift layer are diffused at a higher concentration than the drift layer. In the case of an IGBT, the impurity diffusion region in this specification refers to a buffer layer.

本発明は、半導体装置を製造する方法をも提供する。本発明の半導体装置の製造方法は、半導体基板の表面に表面電極が形成されており、半導体基板の裏面に裏面電極が形成されている縦型の半導体装置を製造する方法である。
本発明の半導体装置の製造方法は、半導体基板の裏面に、凹部底面が平坦な凹凸形状を形成する凹凸形成工程と、少なくとも凹部底面から半導体基板内に、凹部底面から一定距離だけ隔てた深さに不純物が到達するエネルギーで不純物を注入する工程と、半導体基板を熱処理して注入した不純物を拡散する不純物拡散工程を備えている。本発明の製造方法では、凹凸形成工程で形成する隣接する凹部底面同士の間隔を、不純物拡散工程で得られる不純物拡散領域の厚みの０．７倍以下にしておく。 The present invention also provides a method of manufacturing a semiconductor device. The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a vertical semiconductor device in which a surface electrode is formed on the surface of a semiconductor substrate and a back electrode is formed on the back surface of the semiconductor substrate.
The method for manufacturing a semiconductor device according to the present invention includes an unevenness forming step of forming an uneven shape with a flat bottom surface on a back surface of a semiconductor substrate, and a depth at least a distance from the bottom surface of the recess into the semiconductor substrate. And a step of implanting the impurity with energy that the impurity reaches, and an impurity diffusion step of diffusing the implanted impurity by heat-treating the semiconductor substrate. In the manufacturing method of the present invention, the interval between the adjacent concave bottom surfaces formed in the unevenness forming step is set to 0.7 times or less the thickness of the impurity diffusion region obtained in the impurity diffusion step.

本方法では、半導体基板の裏面に凹凸形状を形成する（凹凸形成工程）。凹凸形状は、凸部を形成したい部分にフォトレジストを成膜して、エッチングすることによって形成することができる。このとき、凹部底面が平坦となるようにエッチングして凹凸形状を形成する。エッチング深さは限定されない。凹部の深さを任意の深さに設定することができる。なお、凹部底面の幅は限定されない。
凹凸形成工程では、隣接する凹部底面同士の間隔を、後記する不純物拡散工程で得られる不純物拡散領域の厚みの０．７倍以下となるように形成する。
本方法では、少なくとも凹部底面から半導体基板内に、凹部底面から一定距離だけ隔てた深さに不純物が到達するエネルギーで不純物を注入する。凸部表面からも半導体基板内に不純物を注入してもよいし、凸部表面には不純物を注入しなくてもよい。
本方法では、半導体基板を熱処理して注入した不純物を拡散する（不純物拡散工程）。隣接する凹部底面同士の間隔が不純物拡散領域の厚みの０．７倍以下となる関係で形成されていると、凹部底面から一定距離だけ隔てた深さにおいて不純物拡散領域が連続的に形成される。 In this method, an uneven shape is formed on the back surface of the semiconductor substrate (an unevenness forming step). The concavo-convex shape can be formed by forming a photoresist on a portion where the convex portion is to be formed and etching the photoresist. At this time, the concave and convex shape is formed by etching so that the bottom surface of the concave portion becomes flat. The etching depth is not limited. The depth of the recess can be set to an arbitrary depth. In addition, the width | variety of a recessed part bottom face is not limited.
In the concavo-convex forming step, the gap between adjacent concave bottom surfaces is formed to be 0.7 times or less the thickness of the impurity diffusion region obtained in the impurity diffusion step described later.
In this method, the impurity is implanted into the semiconductor substrate at least from the bottom surface of the recess with the energy that the impurity reaches a depth separated from the bottom surface of the recess by a certain distance. Impurities may be implanted into the semiconductor substrate also from the convex surface, or impurities may not be implanted into the convex surface.
In this method, the semiconductor substrate is heat-treated to diffuse the implanted impurities (impurity diffusion step). If the distance between adjacent concave bottom surfaces is 0.7 times or less the thickness of the impurity diffusion region, the impurity diffusion regions are continuously formed at a depth separated from the concave bottom surface by a certain distance. .

上記の方法によると、凹部底面を深い位置に形成することができるため、不純物拡散領域もまた裏面接触面から深い位置に形成することができる。そのため、不純物拡散領域を貫通する傷がつきにくい。製造工程中につく傷などによるパンチスルーの発生を抑制できる半導体装置を製造することができる。   According to the above method, since the bottom surface of the recess can be formed at a deep position, the impurity diffusion region can also be formed at a deep position from the back contact surface. Therefore, scratches penetrating the impurity diffusion region are difficult to be attached. It is possible to manufacture a semiconductor device that can suppress the occurrence of punch-through due to scratches or the like that occur during the manufacturing process.

本製造方法では、不純物拡散領域の形成後に、裏面電極を形成してもよい。例えばＩＧＢＴを製造する場合は、コレクタ電極などを形成してもよい。コレクタ電極は凹部底面のみに形成してもよいし、凹部底面と凸部表面の両方に形成してもよい。必要なら凸部側面にまで形成してもよい。
本製造法方法では、裏面電極形成後に、半導体基板をダイシングして個々の半導体装置に切り分けてもよい。そしてダイシング後に、個々の半導体装置を実装基板に取り付けてもよい。 In this manufacturing method, the back electrode may be formed after the impurity diffusion region is formed. For example, when manufacturing an IGBT, a collector electrode or the like may be formed. The collector electrode may be formed only on the bottom surface of the recess, or may be formed on both the bottom surface of the recess and the surface of the projection. If necessary, it may be formed on the side surface of the convex portion.
In this manufacturing method, after the back surface electrode is formed, the semiconductor substrate may be diced into individual semiconductor devices. Then, after dicing, individual semiconductor devices may be attached to the mounting substrate.

本発明によると、縦型の半導体装置において、製造工程中あるいは製造後につく傷などによってパンチスルー現象が発生することを抑制することができる。また、そのような縦型の半導体装置を製造することができる。   According to the present invention, in a vertical semiconductor device, it is possible to suppress the occurrence of a punch-through phenomenon due to scratches that occur during or after the manufacturing process. In addition, such a vertical semiconductor device can be manufactured.

下記に説明する実施例の好ましい特徴を列記する。
（第１特徴） 凹凸形状を直線状に形成する。
（第２特徴） 凹凸形状を格子状に形成する。 Preferred features of the embodiments described below are listed.
(First feature) The uneven shape is formed in a straight line.
(2nd characteristic) The uneven | corrugated shape is formed in a grid | lattice form.

（第１実施例）
図１に、本発明の第１実施例である半導体装置１００の断面図を示す。半導体装置１００は縦型のＩＧＢＴである。
半導体装置１００は、金属のコレクタ電極２と、コレクタ電極２の上面に接触しているｐ+型のコレクタ層４と、コレクタ層４の上面に接触しているｎ+型のバッファ層６と、バッファ層６の上面に接触しているｎ−型のドリフト層８と、ドリフト層８の表面の一部に形成されているｐ−型のボディ領域１０と、ボディ領域１０の表面の一部に形成されているｎ+型のエミッタ領域１２と、ドリフト層８とエミッタ領域１２を分離している範囲のボディ領域１０にトレンチゲート絶縁膜２０を介して対向しているゲート電極１８と、エミッタ領域１２に接しているとともにゲート絶縁膜１６によってゲート電極１８から絶縁されているエミッタ電極１４を備えている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 is a vertical IGBT.
The semiconductor device 100 includes a metal collector electrode 2, a p + type collector layer 4 in contact with the upper surface of the collector electrode 2, an n + type buffer layer 6 in contact with the upper surface of the collector layer 4, N − type drift layer 8 in contact with the upper surface of buffer layer 6, p − type body region 10 formed on part of the surface of drift layer 8, and part of the surface of body region 10 An n + -type emitter region 12 formed, a gate electrode 18 facing the body region 10 in a range separating the drift layer 8 and the emitter region 12 with a trench gate insulating film 20 therebetween, and an emitter region 12 and an emitter electrode 14 insulated from the gate electrode 18 by the gate insulating film 16.

半導体装置１００の終端領域には、ボディ領域１０の外周を一巡するｐ+型のガードリング２２ａ、２２ｂ、２２ｃと、最外周のガードリング２２ｃの外周に形成されているｎ+型のチャネルストッパ領域２４と、終端領域のドリフト層８の表面に形成されている層間絶縁膜２４を備えている。図中では３本のガードリング２２ａ、２２ｂ、２２ｃのみが図示されているが、その本数はもっと多くてもよい。
半導体装置１００はさらに、裏面に凹部２８と凸部３０からなる凹凸形状３２を備えている。なお、参照符号Ｌ１は、不純物拡散領域（バッファ層６）の厚みを示す。参照符号Ｌ２は、隣接する凹部２８の底面同士の間隔を示す。凸部３０はコレクタ層４の結晶構造に連結している結晶構造の半導体基板で形成されている。 In the termination region of the semiconductor device 100, p + type guard rings 22a, 22b, 22c that circulate around the outer periphery of the body region 10 and an n + type channel stopper region formed on the outer periphery of the outermost guard ring 22c. 24 and an interlayer insulating film 24 formed on the surface of the drift layer 8 in the termination region. In the figure, only three guard rings 22a, 22b, and 22c are shown, but the number may be larger.
The semiconductor device 100 further includes a concavo-convex shape 32 including a concave portion 28 and a convex portion 30 on the back surface. Reference symbol L1 indicates the thickness of the impurity diffusion region (buffer layer 6). Reference symbol L <b> 2 indicates the interval between the bottom surfaces of the adjacent recesses 28. The convex portion 30 is formed of a semiconductor substrate having a crystal structure connected to the crystal structure of the collector layer 4.

図２に、半導体装置１００の裏面側を拡大した断面図を示す。隣接する凹部２８の底面同士の間隔Ｌ２は、不純物拡散領域（バッファ層６）の厚みＬ１の０．７倍以下である。そのため、バッファ層６は、凹部２８の底面から一定距離Ｌ３だけ隔てた深さにおいて連続して形成されている。半導体装置１００は、バッファ層６の切れ目からパンチスルーが発生することはない。なお、参照符号Ｌ４は、凹部２８の底面から凸部３０の表面までの距離を示す。   FIG. 2 shows an enlarged cross-sectional view of the back side of the semiconductor device 100. The distance L2 between the bottom surfaces of the adjacent recesses 28 is 0.7 times or less the thickness L1 of the impurity diffusion region (buffer layer 6). Therefore, the buffer layer 6 is continuously formed at a depth separated from the bottom surface of the recess 28 by a certain distance L3. In the semiconductor device 100, punch-through does not occur from the break of the buffer layer 6. Reference symbol L4 indicates the distance from the bottom surface of the recess 28 to the surface of the protrusion 30.

図１、図２に示すように、半導体装置１００の裏面には、不純物拡散領域（バッファ層６）が半導体基板の裏面接触面（凸部３０の表面）から深い位置に形成されている。Ｌ３＋Ｌ４の深さの傷はつきにくいため、凸部３０に傷がついたとしても、その傷がバッファ層６を貫通する可能性は低い。また、凹部２８は窪んでいるため、傷がつきにくい。半導体装置１００の製造工程中に半導体基板の裏面に傷がついたとしても、その傷がバッファ層６を貫通する可能性は低い。その結果、製造工程中についた傷などによるパンチスルー現象の発生が抑制される。   As shown in FIGS. 1 and 2, an impurity diffusion region (buffer layer 6) is formed on the back surface of the semiconductor device 100 at a deep position from the back surface contact surface (surface of the convex portion 30) of the semiconductor substrate. Since the scratch of the depth of L3 + L4 is hard to be attached, even when the convex portion 30 is damaged, the possibility that the scratch penetrates the buffer layer 6 is low. Moreover, since the recessed part 28 is depressed, it is hard to be damaged. Even if the back surface of the semiconductor substrate is damaged during the manufacturing process of the semiconductor device 100, the possibility that the scratch penetrates the buffer layer 6 is low. As a result, the occurrence of a punch-through phenomenon due to scratches or the like in the manufacturing process is suppressed.

図３〜図８に、半導体装置１００を製造する方法を示す。
図３に示すように、ｎ−型の半導体基板７０の裏面に、フォトレジスト３４によるパターンを成膜する。フォトレジスト３４は、凹凸形状３２の凹部３０を形成する部分が開孔しているパターンで成膜する。このとき、凹部底面同士の間隔Ｌ２が、後記する工程で形成する不純物拡散領域（バッファ層６）の厚みＬ１の０．７倍以下となるように、フォトレジスト３４のパターンを調整する。
次に、図４に示すように、フォトレジスト３４を形成した半導体基板７０の裏面をエッチングする。エッチング深さは、バッファ層６を形成したい深さで任意に設定することができる。エッチング後、フォトレジスト３４を除去する。半導体基板７０の裏面に凹凸形状３２が形成される。
次に、図５に示すように、凹部３０の底面から不純物３８、３６を注入する。バッファ層６を形成するための不純物としてｎ型の不純物３８（例えばリンなど）を注入する。コレクタ層４を形成するための不純物としてｐ型の不純物３６（例えばボロンなど）を注入する。なお、図５に示すように、凸部２８の表面には不純物３８、３６を注入してもよいし、凸部２８の表面に注入しなくてもよい。 3 to 8 show a method for manufacturing the semiconductor device 100.
As shown in FIG. 3, a pattern made of a photoresist 34 is formed on the back surface of the n − type semiconductor substrate 70. The photoresist 34 is formed in a pattern in which a portion where the concave portion 30 of the concave and convex shape 32 is formed is opened. At this time, the pattern of the photoresist 34 is adjusted so that the distance L2 between the bottom surfaces of the recesses is 0.7 times or less the thickness L1 of the impurity diffusion region (buffer layer 6) formed in the process described later.
Next, as shown in FIG. 4, the back surface of the semiconductor substrate 70 on which the photoresist 34 is formed is etched. The etching depth can be arbitrarily set at a depth at which the buffer layer 6 is desired to be formed. After the etching, the photoresist 34 is removed. An uneven shape 32 is formed on the back surface of the semiconductor substrate 70.
Next, as shown in FIG. 5, impurities 38 and 36 are implanted from the bottom surface of the recess 30. An n-type impurity 38 (for example, phosphorus) is implanted as an impurity for forming the buffer layer 6. A p-type impurity 36 (for example, boron) is implanted as an impurity for forming the collector layer 4. As shown in FIG. 5, impurities 38 and 36 may be implanted into the surface of the convex portion 28 or may not be implanted into the surface of the convex portion 28.

次に、図６に示すように、半導体基板７０を熱処理して不純物３６、３８を熱拡散させる。凹部底面同士の間隔Ｌ２が、不純物拡散領域（バッファ層）の厚みＬ１の０．７倍以下であるため、裏面が凸部２８になっている部分の半導体基板７０内でも、熱拡散時にバッファ層６が横方向につながる。熱拡散後にバッファ層６が凹部３０の底面から一定距離だけ隔てた深さＬ３において連続的に形成される。半導体基板７０の熱処理することによって、バッファ層６とともにコレクタ層４も形成される。コレクタ層４は不連続に形成されてもよい。
なお、凸部２８の表面に不純物３８，３６を注入した場合、図６に示すように、凸部２８にバッファ層６ａとコレクタ層４ａが形成される。このように凸部２８に、バッファ層６ａとコレクタ層４ａが形成されてもよい。バッファ層６ａとコレクタ層４ａを貫通する傷がついても問題はない。
次に、図７に示すように、半導体基板７０の裏面にフォトレジスト５４によるパターンを成膜する。フォトレジスト５４は、凹凸形状３２の凹部３０が開孔しているパターンで成膜する。なお、半導体装置１００は凸部２８にバッファ層６ａとコレクタ層４ａが形成されていない（凸部２８に不純物３８，３６を注入していない）ため、図７以降の図では凸部２８にバッファ層６ａとコレクタ層４ａを図示していない。
次に、図８に示すように、半導体基板７０の裏面にコレクタ電極２を成膜して、その後、フォトレジスト５４を除去する。コレクタ電極２は、凹部３０の底面に形成される。
次に、半導体基板７０をダイシングして個々の半導体装置に切り分ける。
上記の方法によって、半導体装置１００を製造することができる。 Next, as shown in FIG. 6, the semiconductor substrate 70 is heat-treated to thermally diffuse the impurities 36 and 38. Since the distance L2 between the bottom surfaces of the recesses is 0.7 times or less of the thickness L1 of the impurity diffusion region (buffer layer), the buffer layer is also formed during the thermal diffusion even in the semiconductor substrate 70 in the portion where the back surface is the projection 28. 6 is connected in the horizontal direction. After thermal diffusion, the buffer layer 6 is continuously formed at a depth L3 that is separated from the bottom surface of the recess 30 by a certain distance. The heat treatment of the semiconductor substrate 70 forms the collector layer 4 together with the buffer layer 6. The collector layer 4 may be formed discontinuously.
When the impurities 38 and 36 are implanted into the surface of the convex portion 28, the buffer layer 6a and the collector layer 4a are formed on the convex portion 28 as shown in FIG. Thus, the buffer layer 6 a and the collector layer 4 a may be formed on the convex portion 28. There is no problem even if there is a scratch penetrating the buffer layer 6a and the collector layer 4a.
Next, as shown in FIG. 7, a pattern made of a photoresist 54 is formed on the back surface of the semiconductor substrate 70. The photoresist 54 is formed in a pattern in which the concave portion 30 having the concave and convex shape 32 is opened. In the semiconductor device 100, the buffer layer 6a and the collector layer 4a are not formed on the convex portion 28 (impurities 38 and 36 are not implanted into the convex portion 28). Layer 6a and collector layer 4a are not shown.
Next, as shown in FIG. 8, the collector electrode 2 is formed on the back surface of the semiconductor substrate 70, and then the photoresist 54 is removed. The collector electrode 2 is formed on the bottom surface of the recess 30.
Next, the semiconductor substrate 70 is diced into individual semiconductor devices.
The semiconductor device 100 can be manufactured by the above method.

図９に、半導体装置１００の実装基板４２との接合時の断面図を示す。図５に示すように、半導体装置１００と実装基板４２との接合時に、はんだ４０が裏面の凹部の底面に入り込む。凹部の底面に形成されているコレクタ電極２とコンタクトをとることができる。   FIG. 9 shows a cross-sectional view of the semiconductor device 100 when bonded to the mounting substrate 42. As shown in FIG. 5, when joining the semiconductor device 100 and the mounting substrate 42, the solder 40 enters the bottom surface of the recess on the back surface. A contact can be made with the collector electrode 2 formed on the bottom surface of the recess.

図１０に、半導体装置１００を裏面から見た上視図を示す。半導体装置１００の裏面には、凹部２８と凸部３０が直線状に形成されている。   FIG. 10 shows a top view of the semiconductor device 100 as seen from the back side. On the back surface of the semiconductor device 100, a recess 28 and a protrusion 30 are formed in a straight line.

（第２実施例）
図１１に、本発明の第２実施例である半導体装置２００を裏面から見た上視図を示す。
半導体装置２００の裏面には、凹部４８と凸部５０が格子状に形成されている。 (Second embodiment)
FIG. 11 is a top view of the semiconductor device 200 according to the second embodiment of the present invention as viewed from the back side.
On the back surface of the semiconductor device 200, concave portions 48 and convex portions 50 are formed in a lattice shape.

（第３実施例）
図１２に、本発明の第３実施例である半導体装置３００を裏面から見た上視図を示す。
半導体装置３００の裏面には、凹部５８、６８と凸部６０が直線状に形成されている。なお、図１１では、明瞭化のため凸部６０にハッチングを施している。凹部５８の底面の幅と凹部６８の底面の幅は異なる。凹凸形状がこのように不等ピッチの直線状に形成されていてもよい。 (Third embodiment)
FIG. 12 is a top view of the semiconductor device 300 according to the third embodiment of the present invention as viewed from the back side.
Concave portions 58 and 68 and a convex portion 60 are linearly formed on the back surface of the semiconductor device 300. In FIG. 11, the convex portion 60 is hatched for clarity. The width of the bottom surface of the recess 58 and the width of the bottom surface of the recess 68 are different. The concavo-convex shape may thus be formed in a straight line having an unequal pitch.

（第４実施例）
図１３に、本発明の第４実施例である半導体装置４００の裏面構造を拡大した図を示す。
半導体装置４００の裏面に形成されている凹凸形状は、凹部底面４６と凸部側面４４が鈍角をなしている。隣接する凹部底面同士の間隔Ｌ５は、不純物拡散領域の厚みＬ１の０．７倍以下であるように形成されている。コレクタ電極５２は、半導体装置４００の裏面全体に形成されている。そのため、半導体装置４００は、コレクタ電極５２の接触抵抗が小さい。 (Fourth embodiment)
FIG. 13 is an enlarged view of the back surface structure of the semiconductor device 400 according to the fourth embodiment of the present invention.
In the uneven shape formed on the back surface of the semiconductor device 400, the concave bottom surface 46 and the convex side surface 44 form an obtuse angle. An interval L5 between adjacent concave bottom surfaces is formed to be 0.7 times or less the thickness L1 of the impurity diffusion region. The collector electrode 52 is formed on the entire back surface of the semiconductor device 400. Therefore, the semiconductor device 400 has a small contact resistance of the collector electrode 52.

以上、本発明の実施例について詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
例えば、実施例では縦型のＩＧＢＴについて記載したが、他の縦型の半導体装置であってもよい。
本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, although the vertical IGBT has been described in the embodiments, other vertical semiconductor devices may be used.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

本発明の第１実施例である半導体装置１００の断面図を示す。1 is a sectional view of a semiconductor device 100 according to a first embodiment of the present invention. 半導体装置１００の裏面側を拡大した断面図を示す。FIG. 3 shows an enlarged cross-sectional view of the back side of the semiconductor device 100. 半導体装置１００の製造方法の工程を示す。The process of the manufacturing method of the semiconductor device 100 is shown. 半導体装置１００の製造方法の工程を示す。The process of the manufacturing method of the semiconductor device 100 is shown. 半導体装置１００の製造方法の工程を示す。The process of the manufacturing method of the semiconductor device 100 is shown. 半導体装置１００の製造方法の工程を示す。The process of the manufacturing method of the semiconductor device 100 is shown. 半導体装置１００の製造方法の工程を示す。The process of the manufacturing method of the semiconductor device 100 is shown. 半導体装置１００の製造方法の工程を示す。The process of the manufacturing method of the semiconductor device 100 is shown. 半導体装置１００の実装基板との接合時の断面図を示す。Sectional drawing at the time of joining with the mounting substrate of the semiconductor device 100 is shown. 半導体装置１００を裏面から見た上視図を示す。The top view which looked at the semiconductor device 100 from the back surface is shown. 本発明の第２実施例である半導体装置２００の裏面からの上視図を示す。The top view from the back surface of the semiconductor device 200 which is 2nd Example of this invention is shown. 本発明の第３実施例である半導体装置３００の裏面からの上視図を示す。The top view from the back surface of the semiconductor device 300 which is 3rd Example of this invention is shown. 本発明の第４実施例である半導体装置４００の裏面側を拡大した断面図を示す。Sectional drawing which expanded the back surface side of the semiconductor device 400 which is 4th Example of this invention is shown.

符号の説明Explanation of symbols

２、５２：コレクタ電極
４：コレクタ層
６：バッファ層
８：ドリフト層
１０：ボディ領域
１２：エミッタ領域
１４：エミッタ電極
１６：ゲート絶縁膜
１８：ゲート電極
２０：トレンチゲート絶縁膜
２２：ガードリング
２４：層間絶縁膜
２６：チャネルストッパ領域
２８、４８、５８、６８：凹部
３０、５０、６０：凸部
３２：凹凸形状
３４、５４：フォトレジスト
３６：ｐ型不純物（コレクタ層不純物）
３８：ｎ型不純物（バッファ層不純物）
４０：はんだ
４２：実装基板
４４：凸部側面
４６：凹部底面
７０：半導体基板
Ｌ１：不純物拡散領域（バッファ層）の厚み
Ｌ２：凹部底面同士の間隔
Ｌ３：凹部底面から不純物拡散領域までの距離
Ｌ４：凹部底面から凸部表面までの距離
Ｌ５：（半導体装置４００の）凹部底面同士の間隔 2, 52: collector electrode 4: collector layer 6: buffer layer 8: drift layer 10: body region 12: emitter region 14: emitter electrode 16: gate insulating film 18: gate electrode 20: trench gate insulating film 22: guard ring 24 : Interlayer insulating film 26: Channel stopper regions 28, 48, 58, 68: Concave portions 30, 50, 60: Convex portion 32: Concave and convex shape 34, 54: Photoresist 36: p-type impurity (collector layer impurity)
38: n-type impurity (buffer layer impurity)
40: Solder 42: Mounting substrate 44: Convex side surface 46: Concave bottom 70: Semiconductor substrate L1: Thickness of impurity diffusion region (buffer layer) L2: Distance between concave bottoms L3: Distance L4 from concave bottom to impurity diffusion region : Distance from the bottom surface of the concave portion to the surface of the convex portion L5: Distance between the bottom surfaces of the concave portions (of the semiconductor device 400)

Claims (4)

半導体基板の表面に表面電極が形成されており、半導体基板の裏面に裏面電極が形成されている縦型の半導体装置であり、
半導体基板の裏面に、凹部底面が平坦な凹凸形状が形成されており、
凹部底面から一定距離だけ隔てた深さの半導体基板内に不純物拡散領域が形成されており、
隣接する凹部底面同士の間隔が、前記不純物拡散領域の厚みの０．７倍以下であり、
隣接する凹部底面同士の間隔において、前記不純物拡散領域が前記深さにおいて連続していることを特徴とする半導体装置。 A front surface electrode is formed on the front surface of the semiconductor substrate, and a back surface electrode is formed on the back surface of the semiconductor substrate.
On the back surface of the semiconductor substrate, a concave-convex shape with a flat bottom surface is formed,
An impurity diffusion region is formed in the semiconductor substrate at a depth separated from the bottom surface of the recess by a certain distance,
The interval between adjacent concave bottom surfaces is 0.7 times or less the thickness of the impurity diffusion region,
2. The semiconductor device according to claim 1, wherein the impurity diffusion region is continuous at the depth in an interval between adjacent concave bottom surfaces. 前記凹部底面と凸部側面が鈍角をなしており、
前記裏面電極が、半導体基板の裏面全体に形成されていることを特徴とする請求項１の半導体装置。 The concave bottom surface and the convex side surface form an obtuse angle,
2. The semiconductor device according to claim 1, wherein the back electrode is formed on the entire back surface of the semiconductor substrate. 前記半導体装置は、ＩＧＢＴであり、
前記不純物拡散領域が、コレクタ層とドリフト層を分離するバッファ層を形成しており、
前記バッファ層が、半導体基板の裏面の凹凸形状に関わらず、凹部底面から一定距離だけ隔てた深さを連続して伸びていることを特徴とする請求項１又は２の半導体装置。 The semiconductor device is an IGBT,
The impurity diffusion region forms a buffer layer separating the collector layer and the drift layer;
3. The semiconductor device according to claim 1, wherein the buffer layer continuously extends a depth separated from the bottom surface of the recess by a predetermined distance regardless of the uneven shape of the back surface of the semiconductor substrate. 半導体基板の表面に表面電極が形成されており、半導体基板の裏面に裏面電極が形成されている縦型の半導体装置を製造する方法であり、
半導体基板の裏面に、凹部底面が平坦な凹凸形状を形成する凹凸形成工程と、
少なくとも凹部底面から半導体基板内に、凹部底面から一定距離だけ隔てた深さに不純物が到達するエネルギーで不純物を注入する工程と、
半導体基板を熱処理して注入した不純物を拡散する不純物拡散工程を備えており、
前記凹凸形成工程で、隣接する凹部底面同士の間隔を、前記不純物拡散工程で得られる不純物拡散領域の厚みの０．７倍以下にしておくことを特徴とする半導体装置の製造方法。 A method of manufacturing a vertical semiconductor device in which a surface electrode is formed on the surface of a semiconductor substrate and a back electrode is formed on the back surface of the semiconductor substrate,
An unevenness forming step for forming an uneven shape with a flat bottom surface on the back surface of the semiconductor substrate;
Injecting impurities with energy that reaches at a depth separated from the bottom surface of the recess by a certain distance into the semiconductor substrate at least from the bottom surface of the recess;
An impurity diffusion step of diffusing the implanted impurity by heat-treating the semiconductor substrate;
A method of manufacturing a semiconductor device, wherein in the unevenness forming step, an interval between adjacent concave bottom surfaces is set to 0.7 times or less of a thickness of an impurity diffusion region obtained in the impurity diffusion step.
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