JP2009049173A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2009049173A
JP2009049173A JP2007213594A JP2007213594A JP2009049173A JP 2009049173 A JP2009049173 A JP 2009049173A JP 2007213594 A JP2007213594 A JP 2007213594A JP 2007213594 A JP2007213594 A JP 2007213594A JP 2009049173 A JP2009049173 A JP 2009049173A
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Japan
Prior art keywords
post
connection terminal
semiconductor device
package
lead frame
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JP2007213594A
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Japanese (ja)
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Kiyoshi Matsunaga
清 松永
Shuji Mori
修治 森
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Mitsui High Tec Inc
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Mitsui High Tec Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method forming a post at the semiconductor device assembling step. <P>SOLUTION: A metallic mold 30 with a protrusion in a position corresponding to a connection terminal 14 is superposed on a lead frame material 20 and a sealing resin 12 is poured into the mold to seal with the resin. A metal paste 24 such as solder is poured into a hole 23 formed after removing the metallic mold 30 and the resin is cured at a fusing temperature of the metal paste 24 to form the post 17 on the connection terminal 14. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に、半導体装置を積層したＰｏＰパッケージの下層となる半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device that is a lower layer of a PoP package in which semiconductor devices are stacked and a manufacturing method thereof.

半導体装置の実装形態の一つとして、３次元方向に積層したＰｏＰ(Package on Package)パッケージが知られており、複数の半導体装置を平面方向に配置する場合に比べて、小さな面積で高密度実装を図ることが可能なことから、例えば、携帯電話機などの小型電子機器において非常に有効な実装方法となっている（例えば、特許文献１参照）。   As one of the mounting forms of semiconductor devices, a PoP (Package on Package) package that is stacked in a three-dimensional direction is known. Compared with the case where a plurality of semiconductor devices are arranged in a planar direction, high-density mounting with a small area is possible. Therefore, for example, it is a very effective mounting method in a small electronic device such as a mobile phone (see, for example, Patent Document 1).

ＰｏＰパッケージでは、上方の半導体装置（上層パッケージ）と下方の半導体装置（下層パッケージ）との立体的な配線手段が大きな課題であり、例えば、図４に示すように、半導体素子１０及びワイヤ１１の部分のみを封止樹脂１２で樹脂封止することにより、下層パッケージ２の基板（リードフレーム）１３上に接続端子１４を露出させ、下層パッケージと上層パッケージを接続する半田ボール１５で、封止樹脂の高さを避けるようにスタンドオフを稼ぐことによって、立体配線を成立させる方法がある。   In the PoP package, a three-dimensional wiring means between the upper semiconductor device (upper layer package) and the lower semiconductor device (lower layer package) is a big problem. For example, as shown in FIG. By sealing only the portion with the sealing resin 12, the connection terminals 14 are exposed on the substrate (lead frame) 13 of the lower layer package 2, and the sealing resin is connected with the solder balls 15 connecting the lower layer package and the upper layer package. There is a method of establishing a three-dimensional wiring by earning a standoff so as to avoid the height.

また、下層パッケージとして、ＱＦＮ(Quad Flat Non-leaded package)やＳＯＮ(Small Outline Non-leaded Package)など、基板上が全体的に封止樹脂で覆われたリードフレームベースの半導体装置を用いる場合は、基板表面の接続端子を封止樹脂表面まで伸張させるポストが必要となる。   In addition, when using a lead frame-based semiconductor device that is entirely covered with a sealing resin, such as QFN (Quad Flat Non-leaded package) or SON (Small Outline Non-leaded Package) as the lower layer package A post for extending the connection terminal on the surface of the substrate to the surface of the sealing resin is required.

ポストを形成する方法としては、例えば、端子形状のリードフレーム１００、１０１を接続端子１４上に複数枚積層し（図５(ａ)参照）、接着・接合することによってポスト１７を形成する方法（図５(ｂ)参照）や、基板（リードフレーム）１３の接続端子１４上に複数層のスタッドバンプ１０２を形成し（図６(ａ)参照）、レベリング装置１０３で研磨などの処理を施してポストを形成する方法（図６(ｂ)参照）などがある。
特開2002-76175号公報 As a method of forming the post, for example, a method of forming the post 17 by laminating a plurality of terminal-shaped lead frames 100 and 101 on the connection terminal 14 (see FIG. 5A) (see FIG. 5A). 5 (b)) or a plurality of stud bumps 102 are formed on the connection terminals 14 of the substrate (lead frame) 13 (see FIG. 6 (a)), and the leveling device 103 performs a process such as polishing. There is a method of forming a post (see FIG. 6B).
JP 2002-76175 A

しかし、端子形状のリードフレームを積層する方法では、複数枚のリードフレームが必要となるため、コストの上昇に繋がっていた。また、スタッドバンプを形成する方法では、製造タクトが非常に長くなり、レベリングのための後処理も必要になっていた。   However, the method of laminating terminal-shaped lead frames requires a plurality of lead frames, leading to an increase in cost. Further, in the method of forming the stud bump, the manufacturing tact time becomes very long, and post-processing for leveling is also required.

さらに、これらの方法では、リードフレームの製作工程でポストを形成するため、ＰｏＰパッケージ専用のリードフレームを用いて半導体装置を組み立てることとなり、一般的な半導体パッケージで利用される汎用型のリードフレームを用いて、ＰｏＰパッケージを製造することができなかった。   Furthermore, in these methods, since the post is formed in the lead frame manufacturing process, the semiconductor device is assembled using a lead frame dedicated to the PoP package, and a general-purpose lead frame used in a general semiconductor package is formed. It was not possible to produce a PoP package.

加えて、接続端子上に積層したリードフレームを加熱・接着してポストを形成する際の加熱処理によるリードフレーム（基板）の変色や、レベリング処理時の荷重によるリードフレーム（基板）の変形など、基板となるリードフレームが損傷する恐れがあった。   In addition, lead frame (substrate) discoloration due to heat treatment when the post frame is formed by heating and bonding the lead frame laminated on the connection terminal, deformation of the lead frame (substrate) due to load during leveling processing, etc. There was a risk of damage to the lead frame as the substrate.

そこで、本発明では、半導体装置の組立工程でポストを形成することが可能な半導体装置、及びその製造方法を提供することを目的とする。   Accordingly, an object of the present invention is to provide a semiconductor device capable of forming a post in a semiconductor device assembly process, and a manufacturing method thereof.

本発明における半導体装置は、半導体素子と、前記半導体素子と電気的に接続するボンディングパッドと、少なくとも前記半導体素子及び前記ボンディングパッドを封止する封止樹脂と、前記封止樹脂上に積層される半導体装置と接続する接続端子と、前記接続端子上の前記封止樹脂に形成された孔に導電性ペーストを充填して形成されたポストとを具備することを特徴とする。   A semiconductor device according to the present invention is laminated on a semiconductor element, a bonding pad that is electrically connected to the semiconductor element, a sealing resin that seals at least the semiconductor element and the bonding pad, and the sealing resin. It comprises a connection terminal connected to a semiconductor device, and a post formed by filling a hole formed in the sealing resin on the connection terminal with a conductive paste.

次に、本発明における半導体装置製造方法は、板状のリードフレーム材の表面側に選択的にハーフエッチングを施し、素子搭載部を形成すると共に、少なくともボンディング端子及び接続端子を突出させる第１のエッチング工程と、前記素子搭載部に半導体素子を載置し、該半導体素子と前記ボンディング端子を電気的に接続すると共に、突出部を備えたモールド金型の該突出部を前記接続端子上に位置させて樹脂封止を行う封止工程と、前記リードフレーム材の裏面側から選択的にエッチングを施して前記ボンディング端子及び接続端子を形成する第２のエッチング工程と、前記突出部によって前記接続端子上に形成された孔に導電性ペーストを充填するポスト形成工程とを具備することを特徴とする。   Next, in the semiconductor device manufacturing method according to the present invention, first half etching is selectively performed on the surface side of the plate-like lead frame material to form an element mounting portion, and at least a bonding terminal and a connection terminal are projected. Etching step, placing a semiconductor element on the element mounting portion, electrically connecting the semiconductor element and the bonding terminal, and positioning the protruding portion of the mold having the protruding portion on the connecting terminal A sealing step of performing resin sealing, a second etching step of selectively etching from the back side of the lead frame material to form the bonding terminal and the connection terminal, and the connection terminal by the protruding portion. And a post forming step of filling the hole formed above with a conductive paste.

また、前記ポスト形成工程は、前記孔に対応する位置を抜いた印刷マスクを設置して前記導電性ペーストを充填し、前記印刷マスクを除去した後、前記導電性ペーストを硬化させることが望ましい。   In the post-forming step, it is preferable that a printing mask with a position corresponding to the hole is provided, the conductive paste is filled, the printing mask is removed, and then the conductive paste is cured.

本発明では、ＰｏＰパッケージのコストを抑えることができる。   In the present invention, the cost of the PoP package can be reduced.

以下、本発明を実施するための最良の形態について、添付図面を参照して詳細に説明する。なお、以下に示す本発明を実施するための形態は、本発明の具体的態様の一例であり、当該形態に限定されるものではない。   The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In addition, the form for implementing this invention shown below is an example of the specific aspect of this invention, and is not limited to the said form.

図１は、本実施例におけるポストを備えた半導体装置（下層パッケージ）の一例を示す図である。同図に示すように下層パッケージ２は、素子搭載部１８に搭載された半導体素子１０と、ボンディング端子１９を具備し、ワイヤ１１を介して電気的に接続され、封止樹脂１２で封止されている。また、上層パッケージと接続するための接続端子１４上には、封止樹脂１２の表面に一部が露出したポスト１７が設けられている。   FIG. 1 is a diagram illustrating an example of a semiconductor device (lower layer package) provided with posts according to the present embodiment. As shown in the figure, the lower package 2 includes a semiconductor element 10 mounted on the element mounting portion 18 and a bonding terminal 19, and is electrically connected via a wire 11 and sealed with a sealing resin 12. ing. Further, on the connection terminal 14 for connection with the upper package, a post 17 partially exposed on the surface of the sealing resin 12 is provided.

次に図２を用いて、本実施例における半導体装置（下層パッケージ）の製造方法の一例について説明する。   Next, an example of a method for manufacturing the semiconductor device (lower layer package) in this embodiment will be described with reference to FIG.

まず、銅あるいは銅合金などの導電性材料からなる板状のリードフレーム材２０を用意し、接続端子１４、ボンディング端子１９、及び素子搭載部１８の裏面２２に下地ニッケルめっき、及び金めっきを施す。   First, a plate-like lead frame material 20 made of a conductive material such as copper or copper alloy is prepared, and base nickel plating and gold plating are applied to the connection terminals 14, the bonding terminals 19, and the back surface 22 of the element mounting portion 18. .

次に、金めっきをレジスト膜としてハーフエッチング（ファーストエッチング）を行って、接続端子１４、及びボンディング端子１９を表面側に突出させると共に、素子搭載部１８を形成する。そして、素子搭載部１８に半導体素子１０を固着し、ワイヤ１１を介して半導体素子１０の電極パッドとボンディング端子１９を接続する（図２(ａ)参照）。   Next, half etching (first etching) is performed using gold plating as a resist film to project the connection terminals 14 and the bonding terminals 19 to the surface side, and the element mounting portion 18 is formed. Then, the semiconductor element 10 is fixed to the element mounting portion 18, and the electrode pad of the semiconductor element 10 and the bonding terminal 19 are connected via the wire 11 (see FIG. 2A).

ここで、接続端子１４に対応する位置に突起を持つモールド金型３０をリードフレーム材２０に重ね合わせ、封止樹脂１２を流し込んで樹脂封止を行い（図２(ｂ)参照）、モールド金型３０を取り外すことによって、接続端子１４上に孔２３を形成する（図２(ｃ)参照）。この結果、封止樹脂１２の上面には、接続端子１４と同数の孔２３が形成され、孔２３を覗くと、接続端子１４である金めっきが確認できる。   Here, a mold die 30 having a protrusion at a position corresponding to the connection terminal 14 is overlaid on the lead frame material 20, and sealing resin 12 is poured into the resin mold (see FIG. 2 (b)). By removing the mold 30, a hole 23 is formed on the connection terminal 14 (see FIG. 2C). As a result, the same number of holes 23 as the connection terminals 14 are formed on the upper surface of the sealing resin 12, and when the holes 23 are viewed, the gold plating that is the connection terminals 14 can be confirmed.

そして、リードフレーム材３０を裏面からエッチング（セカンドエッチング）し、隣接する接続端子１４やボンディング端子１９の間を絶縁するとともに、接続端子１４の位置を抜いた印刷マスク３１を封止樹脂１２上に設置して、ハンダ等の金属ペースト２４を印刷することによって、孔２３に金属ペースト２４を注入し（図２(ｄ)）、印刷マスク３１を除去した後、金属ペースト２４の溶融温度でキュアすることにより、接続端子１４上にポスト１７を形成する（図２(e)）。   Then, the lead frame material 30 is etched from the back surface (second etching) to insulate between the adjacent connection terminals 14 and bonding terminals 19, and a printing mask 31 from which the positions of the connection terminals 14 are removed is formed on the sealing resin 12. By installing the metal paste 24 such as solder and printing it, the metal paste 24 is injected into the holes 23 (FIG. 2D), and after the print mask 31 is removed, the metal paste 24 is cured at the melting temperature. Thus, the post 17 is formed on the connection terminal 14 (FIG. 2E).

なお、印刷マスク３１の厚さを調節することにより、封止樹脂１２から突出するポスト１７の高さ(スタンドオフ)を制御することができる。   The height (standoff) of the post 17 protruding from the sealing resin 12 can be controlled by adjusting the thickness of the print mask 31.

図３は、下層パッケージ２上に上層パッケージ１を積層（実装）する積層方法の一例を示す図である。   FIG. 3 is a diagram illustrating an example of a stacking method for stacking (mounting) the upper layer package 1 on the lower layer package 2.

まず、上層パッケージ１の接続端子１５と下層パッケージ２のポスト１７が接触するように、上層パッケージ１と下層パッケージ２を重ね合わせ（図３(ａ)参照）、ポスト１７の溶融温度に加熱することにより、下層パッケージ２上に上層パッケージ１を実装する（図３(ｂ)参照）。   First, the upper layer package 1 and the lower layer package 2 are overlapped so that the connection terminal 15 of the upper layer package 1 and the post 17 of the lower layer package 2 are in contact (see FIG. 3A), and heated to the melting temperature of the post 17. Thus, the upper package 1 is mounted on the lower package 2 (see FIG. 3B).

なお、下層パッケージ２上に上層パッケージ１を実装する方法は、両パッケージを重ね合わせ、ポストの融点温度まで加熱する方法に限られるものではなく、例えば、接続端子１５とポスト１７の間に、融点低い導電性のペーストなどを設置し、当該ペーストをキュアすることによって、下層パッケージ２上に上層パッケージ１を実装するなど、任意の方法を用いることが可能であり、図２(ｄ)で印刷マスク３１を除去した後、上層パッケージ１と下層パッケージ２を積層してキュアを実行することにより、下層パッケージ２上に上層パッケージ１を実装してもよい。   The method of mounting the upper package 1 on the lower package 2 is not limited to the method of superimposing both packages and heating them to the melting point temperature of the post. For example, the melting point between the connection terminal 15 and the post 17 is not limited. Arbitrary methods such as mounting the upper layer package 1 on the lower layer package 2 can be used by installing a low conductive paste and curing the paste, and the printing mask in FIG. After removing 31, the upper layer package 1 may be mounted on the lower layer package 2 by stacking the upper layer package 1 and the lower layer package 2 and performing a cure.

このように本発明では、リードフレームによるＰｏＰパッケージを実現することができるため、高放熱性、高電気特性を確保することができる。   Thus, according to the present invention, a PoP package using a lead frame can be realized, so that high heat dissipation and high electrical characteristics can be ensured.

また、下層パッケージを１枚のリードフレームで構成し、さらにハンダ等の低コスト材料を使用することができるため、通常のパッケージと同等にコストを抑えることができる。   Further, since the lower layer package can be constituted by a single lead frame, and a low-cost material such as solder can be used, the cost can be reduced to the same level as a normal package.

さらに、リードフレーム製造工程ではなく、半導体装置（下層パッケージ）の組立工程の途中でポストを形成するため、リードフレームに対するダメージ(高温による変色、荷重による変形）が無く、パッケージ品質・信頼性の向上を図ることができる。   In addition, since the post is formed during the assembly process of the semiconductor device (lower package) rather than the lead frame manufacturing process, there is no damage to the lead frame (discoloration due to high temperature, deformation due to load), and package quality and reliability are improved. Can be achieved.

加えて、上層パッケージの積層と、両パッケージ間のスタンドオフの形成を同時に実行することができるため、実装作業性を向上させることができる。   In addition, since the stacking of the upper package and the formation of the standoff between the two packages can be performed simultaneously, the mounting workability can be improved.

なお、本発明の実施例では、エッチングのレジスト膜として金めっきを使用したが、これに替えてスズめっき、パラジウムめっきを使用してもよい。   In the embodiment of the present invention, gold plating is used as the etching resist film, but tin plating or palladium plating may be used instead.

本実施例における半導体装置を下層パッケージとして用いたＰｏＰパッケージの一例を示す図である。It is a figure which shows an example of the PoP package which used the semiconductor device in a present Example as a lower layer package. 本実施例における下層パッケージの製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the lower layer package in a present Example. 本実施例における下層パッケージ上に上層パッケージを実装する積層方法の一例を示す図である。It is a figure which shows an example of the lamination | stacking method which mounts an upper layer package on the lower layer package in a present Example. 従来のＰｏＰパッケージの一例を示す図である。It is a figure which shows an example of the conventional PoP package. リードフレームを積層してポストを形成する方法の一例を示す図である。It is a figure which shows an example of the method of laminating | leading a lead frame and forming a post. スタッドバンプを形成してポストとする方法の一例を示す図である。It is a figure which shows an example of the method of forming a stud bump and setting it as a post.

符号の説明Explanation of symbols

１…上層パッケージ
２…下層パッケージ
１０…半導体素子
１１…ワイヤ
１２…封止樹脂
１３…基板
１４、１５…接続端子
１７…ポスト
１８…素子搭載部
１９…ボンディング端子
２０…リードフレーム材
２２…素子搭載部裏面
２３…孔
２４…金属ペースト
３０…モールド金型
３１…印刷マスク
１００、１０１…リードフレーム
１０２…スタッドバンプ
１０３…レベリング装置 DESCRIPTION OF SYMBOLS 1 ... Upper layer package 2 ... Lower layer package 10 ... Semiconductor element 11 ... Wire 12 ... Sealing resin 13 ... Substrate 14, 15 ... Connection terminal 17 ... Post 18 ... Element mounting part 19 ... Bonding terminal 20 ... Lead frame material 22 ... Element mounting Part back surface 23 ... hole 24 ... metal paste 30 ... mold die 31 ... print mask 100, 101 ... lead frame 102 ... stud bump 103 ... leveling device

Claims (3)

半導体素子と、
前記半導体素子と電気的に接続するボンディングパッドと、
少なくとも前記半導体素子及び前記ボンディングパッドを封止する封止樹脂と、
前記封止樹脂上に積層される半導体装置と接続する接続端子と、
前記接続端子上の前記封止樹脂に形成された孔に導電性ペーストを充填して形成されたポストと
を具備することを特徴とする半導体装置。 A semiconductor element;
A bonding pad electrically connected to the semiconductor element;
Sealing resin for sealing at least the semiconductor element and the bonding pad;
A connection terminal connected to a semiconductor device laminated on the sealing resin;
A semiconductor device comprising: a post formed by filling a hole formed in the sealing resin on the connection terminal with a conductive paste. 板状のリードフレーム材の表面側に選択的にハーフエッチングを施し、素子搭載部を形成すると共に、少なくともボンディング端子及び接続端子を突出させる第１のエッチング工程と、
前記素子搭載部に半導体素子を載置し、該半導体素子と前記ボンディング端子を電気的に接続すると共に、突出部を備えたモールド金型の該突出部を前記接続端子上に位置させて樹脂封止を行う封止工程と、
前記リードフレーム材の裏面側から選択的にエッチングを施して前記ボンディング端子及び接続端子を形成する第２のエッチング工程と、
前記突出部によって前記接続端子上に形成された孔に導電性ペーストを充填するポスト形成工程と
を具備することを特徴とする半導体装置製造方法。 A first etching step of selectively half-etching the surface side of the plate-like lead frame material to form an element mounting portion and projecting at least a bonding terminal and a connection terminal;
A semiconductor element is mounted on the element mounting portion, the semiconductor element and the bonding terminal are electrically connected, and the protruding portion of the mold having the protruding portion is positioned on the connecting terminal to be sealed with resin. A sealing step for stopping,
A second etching step of selectively etching from the back side of the lead frame material to form the bonding terminal and the connection terminal;
And a post-forming step of filling a hole formed on the connection terminal by the protruding portion with a conductive paste. 前記ポスト形成工程は、前記孔に対応する位置を抜いた印刷マスクを設置して前記導電性ペーストを充填し、前記印刷マスクを除去した後、前記導電性ペーストを硬化させることを特徴とする請求項２記載の半導体装置製造方法。   The post-forming step is characterized in that a printing mask having a position corresponding to the hole is provided, the conductive paste is filled, the printing mask is removed, and then the conductive paste is cured. Item 3. A semiconductor device manufacturing method according to Item 2.
JP2007213594A 2007-08-20 2007-08-20 Semiconductor device and its manufacturing method Pending JP2009049173A (en)

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JP2012209343A (en) * 2011-03-29 2012-10-25 Dainippon Printing Co Ltd Semiconductor device and method of manufacturing semiconductor device
JP2012209314A (en) * 2011-03-29 2012-10-25 Dainippon Printing Co Ltd Semiconductor device and method for manufacturing the same
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JP2012209314A (en) * 2011-03-29 2012-10-25 Dainippon Printing Co Ltd Semiconductor device and method for manufacturing the same
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US11935819B2 (en) 2021-03-15 2024-03-19 Murata Manufacturing Co., Ltd. Circuit module having a plurality of lead frames connected to a substrate by metal posts

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