JP2009027101A - Multilayer ceramic capacitor - Google Patents

Multilayer ceramic capacitor Download PDF

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JP2009027101A
JP2009027101A JP2007191523A JP2007191523A JP2009027101A JP 2009027101 A JP2009027101 A JP 2009027101A JP 2007191523 A JP2007191523 A JP 2007191523A JP 2007191523 A JP2007191523 A JP 2007191523A JP 2009027101 A JP2009027101 A JP 2009027101A
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capacitor
external terminal
multilayer ceramic
face
circuit board
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JP2009027101A5 (en
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Nobuhito Enomoto
伸人 榎本
Takashi Tomita
隆 富田
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Taiyo Yuden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To suppress transmission to a circuit board of electrostrictive vibration of a multilayer ceramic capacitor including a ferroelectric layer. <P>SOLUTION: An inner electrode layer 13 in a first group is drawn out to only one of a pair of end faces facing each other of a capacitor body 11 through a plurality of drawing parts 13b1, 13b2, 13b3, and 13b4; and an inner electrode layer 14 in a second group is drawn out to only the other end face through a plurality of drawing parts 14b1, 14b2, 14b3, and 14b4. A plurality of external terminal electrodes are provided on the pair of end faces facing each other of the capacitor body so as to correspond to the plurality of drawing parts, respectively. Therefore, the electrostrictive vibration in regions facing each other with a ceramic ferroelectric layer therebetween is weakened by distribution to the plurality of external terminal electrodes. Accordingly, transmission of the electrostrictive vibration to the circuit board can be suppressed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、積層セラミックコンデンサに関し、さらに詳細には、セラミック強誘電体層を備える積層セラミックコンデンサに関する。 The present invention relates to a multilayer ceramic capacitor, and more particularly to a multilayer ceramic capacitor including a ceramic ferroelectric layer.

セラミック強誘電体層を備える積層セラミックコンデンサは、小型で大きな静電容量を取得できることから、近年、その需要が増加している。図９及び図１０に示すように、特許文献１には、対向する外部端子電極１１６Ａ，１１６Ｂ同士を結ぶ長さ方向の寸法（Ｌ寸法）に比べてこれと直交する幅方向の寸法（Ｗ寸法）を大きくした所謂Ｌ−Ｗ逆転タイプの積層セラミックコンデンサの一例が開示されている。該積層セラミックコンデンサ１１０は、略直方体状のコンデンサ本体１１１と、該コンデンサ本体１１１の互いに対向する一対の端面およびその近傍にそれぞれ形成された第１の外部端子電極１１６Ａと第２の外部端子電極１１６Ｂとを備える。コンデンサ本体１１１は、例えばＢａＴｉＯ３等を主成分とするセラミック強誘電体層１１２Ａ，１１２Ｂと、内部電極層１１３，１１４とが交互に且つ積層体軸方向に複数積層されるとともに、前記セラミック強誘電体層１１２Ａ，１１２Ｂの上方および下方に配置されたカバー層１１２，１１２を備える。前記内部電極層１１３，１１４は一層置きに第１のグループと第２の部ループとに分かれて属し、前記第１のグループに属する内部電極層１１３の端部は前記コンデンサ本体１１１の前記第１の外部端子電極１１６Ａ側の端面に露出して該第１の外部端子電極１１６Ａに接続され、前記第２のグループに属する内部電極層１１４の端部は前記コンデンサ本体１１１の前記第２の外部端子電極１１６Ｂ側の端面に露出して該第２の外部端子電極１１６Ｂに接続されている。セラミック強誘電体層１１２Ａは、一方の主面上にＮｉ，Ｃｕ等からなる内部電極層１１３を備える。前記内部電極層１１３は、前記コンデンサ本体１１１の互いに対向する一対の端面のうちの一方の端面に一端側が露出するように形成されている。また、セラミック強誘電体層１１２Ｂは、同様に内部電極層１１４を備える。前記内部電極層１１４は、前記コンデンサ本体１１１の互いに対向する一対の側面のうちの他方の側面に一端側が露出するように形成されている。そして、前記外部端子電極１１６Ａは、前記コンデンサ本体１１１の前記第１のグループに属する内部電極層１１３にそれぞれ接続されている。同様に、前記外部端子電極１１６Ｂは、前記コンデンサ本体１１１の前記第２のグループに属する内部電極層１１４にそれぞれ接続されている。前記内部電極層１１３と内部電極層１１４とは、前記セラミック強誘電体層１１２Ａ、１１２Ｂを挟んで互いに対向し、一つのコンデンサユニットを構成している。 In recent years, the demand for a multilayer ceramic capacitor having a ceramic ferroelectric layer has been increasing because it is small and can acquire a large capacitance. As shown in FIG. 9 and FIG. 10, Patent Document 1 discloses a width direction dimension (W dimension) orthogonal to the length direction dimension (L dimension) connecting the opposing external terminal electrodes 116 </ b> A and 116 </ b> B. An example of a so-called LW reversal type multilayer ceramic capacitor with a large ()) is disclosed. The multilayer ceramic capacitor 110 includes a substantially rectangular parallelepiped capacitor body 111, a first external terminal electrode 116A and a second external terminal electrode 116B formed on and near a pair of opposed end surfaces of the capacitor body 111, respectively. With. The capacitor body 111 includes, for example, a plurality of ceramic ferroelectric layers 112A and 112B mainly composed of BaTiO 3 and the like, and internal electrode layers 113 and 114 that are alternately laminated in the laminated body axial direction. Cover layers 112, 112 are provided above and below body layers 112A, 112B. The internal electrode layers 113 and 114 are divided into a first group and a second partial loop every other layer, and the end portions of the internal electrode layers 113 belonging to the first group belong to the first body of the capacitor body 111. Of the internal electrode layer 114 belonging to the second group is exposed to the end face of the external terminal electrode 116A side and connected to the first external terminal electrode 116A. It is exposed at the end face on the electrode 116B side and connected to the second external terminal electrode 116B. The ceramic ferroelectric layer 112A includes an internal electrode layer 113 made of Ni, Cu or the like on one main surface. The internal electrode layer 113 is formed so that one end side is exposed at one end face of the pair of end faces facing each other of the capacitor body 111. Similarly, the ceramic ferroelectric layer 112B includes an internal electrode layer 114. The internal electrode layer 114 is formed such that one end side is exposed on the other side surface of the pair of side surfaces facing each other of the capacitor body 111. The external terminal electrodes 116A are connected to the internal electrode layers 113 belonging to the first group of the capacitor body 111, respectively. Similarly, the external terminal electrodes 116B are connected to the internal electrode layers 114 belonging to the second group of the capacitor body 111, respectively. The internal electrode layer 113 and the internal electrode layer 114 are opposed to each other with the ceramic ferroelectric layers 112A and 112B interposed therebetween, and constitute one capacitor unit.

前記積層セラミックコンデンサ１１０は、図示省略した回路基板の回路配線に接続されたランド電極上に半田付け等の手段により搭載される。前記回路配線を介して前記積層セラミックコンデンサ１１０の前記コンデンサユニットに交流電圧が印加されると、前記複数のセラミック強誘電体層１１２Ａ，１１２Ｂは、厚さ方向と面方向とに交互に膨張と収縮とを繰り返し、所謂電歪振動を生じる。 The multilayer ceramic capacitor 110 is mounted on a land electrode connected to circuit wiring of a circuit board (not shown) by means such as soldering. When an AC voltage is applied to the capacitor unit of the multilayer ceramic capacitor 110 via the circuit wiring, the ceramic ferroelectric layers 112A and 112B expand and contract alternately in the thickness direction and the plane direction. And so-called electrostrictive vibration is generated.

前記のように積層セラミックコンデンサ１１０に電歪振動が生じると、前記積層セラミックコンデンサ１１０の前記各外部端子電極１１６Ａ，１１６Ｂと前記各ランド電極との前記半田付け箇所を介して前記回路基板に振動が伝達され、例えばうなり音等の雑音を生じやすかった。 When the electrostrictive vibration is generated in the multilayer ceramic capacitor 110 as described above, the circuit board is vibrated through the soldered portions of the external terminal electrodes 116A and 116B of the multilayer ceramic capacitor 110 and the land electrodes. For example, it was easy to generate noise such as a roaring sound.

上記積層セラミックコンデンサ１１０における上記の課題を解決する目的で、例えば、図１１に示すように、特許文献２には、積層セラミックコンデンサ２１０が提案されている。積層セラミックコンデンサ２１０は、上記と同様の内部構造を有するコンデンサ本体２１１と、該コンデンサ本体２１１の互いに対向する一対の端面に形成された外部電極２１６Ａ，２１６Ｂと、該外部電極２１６Ａ，２１６Ｂにそれぞれ半田２１７を介して接続された複数の端子エレメント２１５Ａ，２１５Ｂとを有する。前記積層セラミックコンデンサ２１０は、図示省略した回路基板にその厚さ方向に貫通するように形成された複数の端子挿通孔に前記各端子エレメント２１５Ａ，２１５Ｂが挿入され、回路配線に接続されたスルーホールランドに半田付け等により導電接続される。 In order to solve the above problems in the multilayer ceramic capacitor 110, for example, as shown in FIG. 11, a multilayer ceramic capacitor 210 is proposed in Patent Document 2. The multilayer ceramic capacitor 210 is soldered to a capacitor body 211 having the same internal structure as described above, external electrodes 216A and 216B formed on a pair of opposing end surfaces of the capacitor body 211, and the external electrodes 216A and 216B. A plurality of terminal elements 215A and 215B connected via 217; The multilayer ceramic capacitor 210 is a through hole in which the terminal elements 215A and 215B are inserted into a plurality of terminal insertion holes formed so as to penetrate through a circuit board (not shown) in the thickness direction and connected to circuit wiring. The land is conductively connected by soldering or the like.

前記回路配線を介して前記積層セラミックコンデンサ２１０に交流電圧が印加されると、前記と同様に電歪振動を生じる。前記のように積層セラミックコンデンサ２１０に電歪振動が生じると、前記積層セラミックコンデンサ２１０の前記各外部電極２１６Ａ，２１６Ｂに半田２１７を介して接続された複数の端子エレメント２１５Ａ，２１５Ｂと前記各スルーホールランドランドとの前記各半田付け箇所を介して前記回路基板に振動が伝達されるが、このとき、前記複数の端子エレメント２１５Ａ，２１５Ｂにより電歪振動が分割、減衰される。 When an AC voltage is applied to the multilayer ceramic capacitor 210 via the circuit wiring, electrostrictive vibration is generated as described above. When electrostrictive vibration occurs in the multilayer ceramic capacitor 210 as described above, the plurality of terminal elements 215A, 215B connected to the external electrodes 216A, 216B of the multilayer ceramic capacitor 210 via the solder 217 and the through holes. Vibrations are transmitted to the circuit board through the soldered portions with the land lands. At this time, the electrostrictive vibrations are divided and attenuated by the plurality of terminal elements 215A and 215B.

また、上記特許文献２には、図１２に示すように、他の例の積層セラミックコンデンサ２２０が提案されている。積層セラミックコンデンサ２２０は、上記と同様の内部構造を有するコンデンサ本体２２１と、該コンデンサ本体２２１の互いに対向する一対の側面に形成された外部電極２２６Ａ，２２６Ｂと、該外部電極２２６Ａ，２２６Ｂにそれぞれ半田２２７を介して接続された櫛歯状の端子エレメント２２５Ａ，２２５Ｂとを有する。前記積層セラミックコンデンサ２２０は、図示省略した回路基板の回路配線に接続されたランド電極上に前記櫛歯状の端子エレメント２２５Ａ，２２５Ｂが搭載され、半田付け等により導電接続される。 Moreover, as shown in FIG. 12, another example of the multilayer ceramic capacitor 220 is proposed in Patent Document 2 described above. The multilayer ceramic capacitor 220 is soldered to a capacitor body 221 having the same internal structure as described above, external electrodes 226A and 226B formed on a pair of opposite side surfaces of the capacitor body 221 and the external electrodes 226A and 226B. 225, comb-shaped terminal elements 225A and 225B connected via 227. The multilayer ceramic capacitor 220 has the comb-like terminal elements 225A and 225B mounted on land electrodes connected to circuit wiring of a circuit board (not shown), and is conductively connected by soldering or the like.

前記回路配線を介して前記積層セラミックコンデンサ２２０に交流電圧が印加されると、前記と同様に電歪振動を生じる。前記のように積層セラミックコンデンサ２２０に電歪振動が生じると、前記積層セラミックコンデンサ２２０の前記各外部電極２２６Ａ，２２６Ｂに半田２２７を介して接続された一対の端子エレメント２２５Ａ，２２５Ｂと前記各ランド電極との前記各半田付け箇所を介して前記回路基板に振動が伝達されるが、このとき、前記一対の櫛歯状の端子エレメント２２５Ａ，２２５Ｂにより電歪振動が分割、減衰される。
実開平６−７２２８号公報 特開２０００−１８２８８７号公報 When an AC voltage is applied to the multilayer ceramic capacitor 220 through the circuit wiring, electrostrictive vibration is generated as described above. When electrostrictive vibration occurs in the multilayer ceramic capacitor 220 as described above, the pair of terminal elements 225A and 225B connected to the external electrodes 226A and 226B of the multilayer ceramic capacitor 220 via the solder 227 and the land electrodes, respectively. The vibration is transmitted to the circuit board via the soldering points, and at this time, the electrostrictive vibration is divided and attenuated by the pair of comb-like terminal elements 225A and 225B.
Japanese Utility Model Publication No. 6-7228 JP 2000-182887 A

近年、携帯型電子機器等、小型・薄型の電子機器のニーズが高まり、これらの電子機器に搭載される回路基板も薄型化されることが多くなっている。ところが、上記特許文献２に記載の積層セラミックコンデンサにおいては、前記複数の端子エレメント２１５Ａ，２１５Ｂ、もしくは前記一対の櫛歯状の端子エレメント２２５Ａ，２２５Ｂを介して回路基板上のランド電極と導電接続されるので、コンデンサ実装回路基板の薄型化が困難であるという課題があった。また、複数の端子エレメント２１５Ａ，２１５Ｂを有するものにおいては、回路基板に前記複数の端子エレメント２１５Ａ，２１５Ｂをそれぞれ挿通するための端子挿通孔およびスルーホールランドをそれぞれ複数設けなければならず、回路基板上の回路配線が複雑化するという課題があった。 In recent years, needs for small and thin electronic devices such as portable electronic devices are increasing, and circuit boards mounted on these electronic devices are often thinned. However, in the multilayer ceramic capacitor described in Patent Document 2, the plurality of terminal elements 215A and 215B or the pair of comb-shaped terminal elements 225A and 225B are conductively connected to the land electrode on the circuit board. Therefore, there is a problem that it is difficult to reduce the thickness of the capacitor-mounted circuit board. In the case of having a plurality of terminal elements 215A and 215B, a plurality of terminal insertion holes and through-hole lands for inserting the plurality of terminal elements 215A and 215B must be provided in the circuit board. There was a problem that the upper circuit wiring was complicated.

本発明の目的は、回路基板への電歪振動の伝達を抑制することが可能な積層セラミックコンデンサを提供することにある。また、本発明は、上記積層セラミックコンデンサが搭載されたコンデンサ実装回路基板を提供するものである。 An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing transmission of electrostrictive vibration to a circuit board. The present invention also provides a capacitor-mounted circuit board on which the multilayer ceramic capacitor is mounted.

前記目的を達成するため、本発明の積層セラミックコンデンサは、（１）略直方体形状のコンデンサ本体と該コンデンサ本体の互いに対向する一対の端面およびその近傍にそれぞれ形成された第１の外部端子電極と第２の外部端子電極とを備え、前記コンデンサ本体は矩形の強誘電体層と内部電極層とが交互に且つ積層軸方向に複数積層されてなり、前記内部電極層は一層置きに第１のグループと第２のグループとに分かれて属し、前記第１のグループに属する内部電極層の端部は前記コンデンサ本体の前記第１の外部端子電極側の端面に露出して該第１の外部端子電極に接続され、前記第２のグループに属する内部電極層の端部は前記コンデンサ本体の前記第２の外部端子電極側の端面に露出して該第２の外部端子電極に接続された積層セラミックコンデンサである。そして、前記第１の外部端子電極は、前記コンデンサ本体の一方の端面に該端面の幅方向に互いに離間して複数設けられるとともに、前記第２の外部端子電極は、前記コン
デンサ本体の他方の端面に該端面の幅方向に互いに離間して複数設けられている。さらに、前記第１のグループに属する内部電極層は、前記強誘電体層の一方の主面の略中央に配置され前記強誘電体層を挟んで互いに対向する静電容量形成部と、該静電容量形成部から前記一対の端面のうちの一方の端面側のみに突出された複数の引き出し部とを有し、該引き出し部の先端が、対応する前記第１の外部端子電極にそれぞれ接続されている。また、前記第２のグループに属する内部電極層は、前記静電容量形成部と、該静電容量形成部から前記一対の端面のうちの他方の端面側のみに突出された複数の引き出し部とを有し、該引き出し部の先端が、対応する前記第２の外部端子電極にそれぞれ接続されている。（・・・以下第１の課題解決手段と称する。） In order to achieve the above object, a multilayer ceramic capacitor of the present invention includes: (1) a substantially rectangular parallelepiped capacitor body, a pair of opposing end surfaces of the capacitor body, and first external terminal electrodes formed on and near each other. A second external terminal electrode, wherein the capacitor body is formed by alternately laminating a plurality of rectangular ferroelectric layers and internal electrode layers in the stacking axis direction. The end portion of the internal electrode layer belonging to the first group is divided into a group and a second group, and the end portion of the capacitor body is exposed at the end face on the first external terminal electrode side of the capacitor body. An end portion of the internal electrode layer belonging to the second group connected to the electrode is exposed at an end surface of the capacitor body on the second external terminal electrode side and connected to the second external terminal electrode. It is a ceramic capacitor. A plurality of the first external terminal electrodes are provided on one end face of the capacitor body so as to be spaced apart from each other in the width direction of the end face, and the second external terminal electrode is provided on the other end face of the capacitor body. Are provided apart from each other in the width direction of the end face. Further, the internal electrode layer belonging to the first group is disposed at substantially the center of one main surface of the ferroelectric layer and is opposed to each other across the ferroelectric layer, and the static electricity forming portion. A plurality of lead portions protruding only from one end face side of the pair of end faces from the capacitance forming portion, and tips of the lead portions are respectively connected to the corresponding first external terminal electrodes. ing. The internal electrode layer belonging to the second group includes the capacitance forming portion, and a plurality of lead portions protruding from the capacitance forming portion only to the other end face side of the pair of end faces. And the leading ends of the lead portions are connected to the corresponding second external terminal electrodes, respectively. (... hereinafter referred to as first problem solving means)

また、上記積層セラミックコンデンサの主要な形態の一つは、上記第１の課題解決手段に加えてさらに、（２）前記複数の外部端子電極は、前記互いに対向する一対の端面のそれぞれにおいて、該端面の幅方向の中心に近い外部端子電極ほど幅寸法が大きいものである。（・・・以下第２の課題解決手段と称する。） One of the main forms of the multilayer ceramic capacitor is that, in addition to the first problem solving means, (2) the plurality of external terminal electrodes are formed on each of the pair of end faces facing each other. The external terminal electrode closer to the center of the end face in the width direction has a larger width dimension. (... hereinafter referred to as second problem solving means)

また、本発明のコンデンサ実装回路基板は、回路基板上に上記第１の課題解決手段に記載の積層セラミックコンデンサが搭載されたものである。そして、前記積層セラミックコンデンサの一方の端面の前記第１のグループに属する内部電極層に接続された複数の第１の外部端子電極が前記回路基板上の一対のランド電極のうちの一方のランド電極に共に導電接続されており、前記コンデンサの他方の端面の前記第２のグループに属する内部電極層に接続された複数の第２の外部端子電極が前記回路基板上の一対のランド電極のうちの他方のランド電極に共に導電接続されているものである。（・・・以下第３の課題解決手段と称する。） A capacitor-mounted circuit board according to the present invention is obtained by mounting the multilayer ceramic capacitor described in the first problem solving means on a circuit board. A plurality of first external terminal electrodes connected to the internal electrode layer belonging to the first group on one end face of the multilayer ceramic capacitor are one land electrode of a pair of land electrodes on the circuit board. And a plurality of second external terminal electrodes connected to the internal electrode layer belonging to the second group on the other end face of the capacitor, of the pair of land electrodes on the circuit board. The other land electrode is conductively connected together. (... hereinafter referred to as third problem solving means)

上記第１の課題解決手段による作用は次の通りである。すなわち、本発明の積層セラミックコンデンサは、前記第１の外部端子電極が、前記コンデンサ本体の一方の端面に該端面の幅方向に互いに離間して複数設けられるとともに、前記第２の外部端子電極が、前記コンデンサ本体の他方の端面に該端面の幅方向に互いに離間して複数設けられており、前記第１のグループに属する内部電極層は、前記強誘電体層の一方の主面の略中央に配置され前記強誘電体層を挟んで互いに対向する静電容量形成部と、該静電容量形成部から前記一対の端面のうちの一方の端面側のみに突出された複数の引き出し部とを有し、該引き出し部の先端が、対応する前記第１の外部端子電極にそれぞれ接続されており、前記第２のグループに属する内部電極層は、前記静電容量形成部と、該静電容量形成部から前記一対の端面のうちの他方の端面側のみに突出された複数の引き出し部とを有し、該引き出し部の先端が、対応する前記第２の外部端子電極にそれぞれ接続されている。このため、前記積層セラミックコンデンサの対向する外部端子電極間に交流電圧が印加されると、前記第１のグループに属する内部電極層と第２のグループに属する内部電極層とにより挟まれる前記複数のセラミック強誘電体層１２Ａ，１２Ｂは、厚さ方向と面方向とに交互に膨張と収縮とを繰り返し、所謂電歪振動を生じ、長さ方向の寸法（Ｌ寸法）より幅方向の寸法（Ｗ寸法）が大きい場合に、該積層セラミックコンデンサ１０の幅方向の変位が大きい電歪振動を生じる。そして、前記で発生した振動は、それぞれの外部端子電極に分散されて伝達される。即ち、この伝達は、前記第１のグループに属する内部電極層の複数の引き出し部に接続され前記コンデンサ本体の互いに対向する一対の端面のうちの一方の端面に形成された複数の第１の外部端子電極、および前記第２のグループに属する内部電極層の複数の引出部に接続され前記コンデンサ本体の互いに対向する一対の端面のうちの他方の端面に形成された複数の第２の外部端子電極に分散されるので、弱められた後に回路基板に伝達される。 The operation of the first problem solving means is as follows. That is, in the multilayer ceramic capacitor according to the present invention, a plurality of the first external terminal electrodes are provided on one end face of the capacitor main body so as to be spaced apart from each other in the width direction of the end face, and the second external terminal electrode is provided. And a plurality of internal electrode layers belonging to the first group are arranged at substantially the center of one main surface of the ferroelectric layer, and are provided on the other end surface of the capacitor body so as to be spaced apart from each other in the width direction of the end surface. And a plurality of lead portions that protrude from the capacitance forming portion only to one end face side of the pair of end faces. And the leading end of the lead portion is connected to the corresponding first external terminal electrode, and the internal electrode layer belonging to the second group includes the capacitance forming portion and the capacitance From the formation part Of a plurality of lead portions that protrude only on the other end face side of the end face, the tip of the lead portions, to the corresponding second external terminal electrodes are connected respectively. For this reason, when an AC voltage is applied between the opposing external terminal electrodes of the multilayer ceramic capacitor, the plurality of the sandwiched between the internal electrode layer belonging to the first group and the internal electrode layer belonging to the second group The ceramic ferroelectric layers 12A and 12B repeat expansion and contraction alternately in the thickness direction and the surface direction, so-called electrostrictive vibration is generated, and the width direction dimension (W dimension) is longer than the length direction dimension (L dimension). When the dimension) is large, electrostrictive vibration with large displacement in the width direction of the multilayer ceramic capacitor 10 occurs. The vibration generated as described above is distributed and transmitted to each external terminal electrode. That is, this transmission is connected to a plurality of lead portions of the internal electrode layer belonging to the first group, and is connected to a plurality of first external surfaces formed on one end face of the capacitor body facing each other. A plurality of second external terminal electrodes formed on the other end face of the capacitor body and connected to the plurality of lead portions of the terminal electrode and the internal electrode layer belonging to the second group. Therefore, the signal is transmitted to the circuit board after being weakened.

上記第２の課題解決手段による作用は次の通りである。すなわち、上記第１の課題解決手段に加えてさらに、（２）前記複数の外部端子電極は、前記互いに対向する一対の端面のそれぞれにおいて、該端面の幅方向の中心に近い外部端子電極ほど幅寸法が大きい。このため、積層セラミックコンデンサの幅方向の変位が小さくなる前記端面の幅方向の中心に近い幅広の外部電極で重点的に回路基板に拘束され、これに比べて振動時の変位が大きい前記端面の幅方向の両端近傍では回路基板に拘束される度合いが弱まる。これにより、回路基板への振動の伝達が抑制される。 The operation of the second problem solving means is as follows. That is, in addition to the first problem solving means, (2) the plurality of external terminal electrodes are arranged such that the width of the external terminal electrodes closer to the center in the width direction of each of the pair of opposing end faces is closer to the width. The dimensions are large. For this reason, the multilayer ceramic capacitor is constrained to the circuit board mainly by the wide external electrode near the center in the width direction of the end face where the displacement in the width direction becomes small. In the vicinity of both ends in the width direction, the degree of restraint by the circuit board is weakened. Thereby, transmission of vibration to the circuit board is suppressed.

また、上記第３の課題解決手段による作用は次の通りである。すなわち、本発明のコンデンサ実装回路基板は、前記積層セラミックコンデンサの一方の端面の前記第１のグループに属する内部電極層に接続された複数の第１の外部端子電極が前記回路基板上の一対のランド電極のうちの一方のランド電極に共に導電接続されている。また、前記コンデンサの他方の端面の前記第２のグループに属する内部電極層に接続された複数の第２の外部端子電極が前記回路基板上の一対のランド電極のうちの他方のランド電極に共に導電接続されている。このため、回路基板構造を複雑化することなく、一般のチップ状電子部品と同様に実装することができる。 The operation of the third problem solving means is as follows. That is, the capacitor-mounted circuit board of the present invention includes a plurality of first external terminal electrodes connected to the internal electrode layer belonging to the first group on one end face of the multilayer ceramic capacitor. Both of the land electrodes are conductively connected together. A plurality of second external terminal electrodes connected to the internal electrode layer belonging to the second group on the other end face of the capacitor are both connected to the other land electrode of the pair of land electrodes on the circuit board. Conductive connection. Therefore, it can be mounted in the same manner as a general chip electronic component without complicating the circuit board structure.

本発明の積層セラミックコンデンサによれば、コンデンサ実装回路基板の低背化や積層セラミックコンデンサのトータル容量を犠牲にすることなく、前記積層セラミックコンデンサから該積層セラミックコンデンサを実装する回路基板への前記積層セラミックコンデンサの電歪現象による振動が伝達されることを抑制することができる。 According to the multilayer ceramic capacitor of the present invention, the multilayer ceramic capacitor can be stacked on the circuit board on which the multilayer ceramic capacitor is mounted without sacrificing a reduction in the height of the capacitor-mounted circuit board or the total capacity of the multilayer ceramic capacitor. Transmission of vibration due to the electrostriction phenomenon of the ceramic capacitor can be suppressed.

また、本発明のコンデンサ実装回路基板によれば、前記積層セラミックコンデンサからコンデンサ実装回路基板への積層セラミックコンデンサの電歪現象による振動が伝達されることを抑制することができる。本発明の前記目的とそれ以外の目的、構成特徴、作用効果は、以下の説明と添付図面によって明らかとなろう。 In addition, according to the capacitor-mounted circuit board of the present invention, it is possible to suppress vibration due to the electrostriction phenomenon of the multilayer ceramic capacitor from the multilayer ceramic capacitor to the capacitor-mounted circuit board. The above object and other objects, structural features, and operational effects of the present invention will become apparent from the following description and the accompanying drawings.

以下、本発明の積層セラミックコンデンサの第１の実施形態について、図１〜図４を参照して説明する。図１は第１の実施形態の積層セラミックコンデンサ１０の全体構造を示す外観斜視図であり、図２は、該積層セラミックコンデンサ１０のコンデンサ本体１１の内部構造を示す分解斜視図である。また、図３は、本実施形態の積層セラミックコンデンサ１０を回路基板２１上へ搭載する方法を示す部分拡大斜視図である。図４は、前記積層セラミックコンデンサ１０を実装した本発明のコンデンサ実装回路基板２０を示す部分拡大斜視図である。 Hereinafter, a first embodiment of a multilayer ceramic capacitor of the present invention will be described with reference to FIGS. FIG. 1 is an external perspective view showing the overall structure of the multilayer ceramic capacitor 10 of the first embodiment, and FIG. 2 is an exploded perspective view showing the internal structure of the capacitor body 11 of the multilayer ceramic capacitor 10. FIG. 3 is a partially enlarged perspective view showing a method for mounting the multilayer ceramic capacitor 10 of the present embodiment on the circuit board 21. FIG. 4 is a partially enlarged perspective view showing the capacitor-mounted circuit board 20 of the present invention on which the multilayer ceramic capacitor 10 is mounted.

図１および図２に示すように、本実施形態の積層セラミックコンデンサ１０は、略直方体形状のコンデンサ本体１１と該コンデンサ本体１１の互いに対向する一対の端面およびその近傍にそれぞれ形成された第１の外部端子電極１６Ａと第２の外部端子電極１６Ｂとを備えている。そして、前記コンデンサ本体１１は矩形の強誘電体層１２Ａ，１２Ｂと内部電極層１３，１４とが交互に且つ積層軸方向に複数積層されてなる。また、前記内部電極層１３，１４は一層置きに第１のグループと第２のグループとに分かれて属し、前記第１のグループに属する内部電極層１３の端部は前記コンデンサ本体１１の前記第１の外部端子電極１６Ａ側の端面に露出して該第１の外部端子電極１６Ａに接続され、前記第２のグループに属する内部電極層１４の端部は前記コンデンサ本体１１の前記第２の外部端子電極１６Ｂ側の端面に露出して該第２の外部端子電極１６Ｂに接続されている。そして、前記第１の外部端子電極１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４は、前記コンデンサ本体１１の一方の端面に該端面の幅方向に互いに離間して複数設けられるとともに、前記第２の外部端子電極１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４は、前記コンデンサ本体１１の他方の端面に該端面の幅方向に互いに離間して複数設けられている。さらに、前記第１のグループに属する内部電極層１３は、前記強誘電体層１２Ａの一方の主面の略中央に配置され前記強誘電体層１２Ａを挟んで互いに対向する静電容量形成部１３ａと、該静電容量形成部１３ａから前記一対の端面のうちの一方の端面側のみに突出された複数の引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４とを有する。そして、該引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４の先端が、対応する前記第１の外部端子電極１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４にそれぞれ接続されている。同様に、前記第２のグループに属する内部電極層１４は、前記静電容量形成部１４ａと、該静電容量形成部１４ａから前記一対の端面のうちの他方の端面側のみに突出された複数の引き出し部１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４とを有する。そして、該引き出し部１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４の先端が、対応する前記第２の外部端子電極１６Ｂ１．１６Ｂ２．１６Ｂ３，１６Ｂ４にそれぞれ接続されている。 As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 10 of the present embodiment includes a capacitor body 11 having a substantially rectangular parallelepiped shape, a first pair of end surfaces of the capacitor body 11 facing each other, and the vicinity thereof. An external terminal electrode 16A and a second external terminal electrode 16B are provided. The capacitor body 11 includes a plurality of rectangular ferroelectric layers 12A and 12B and internal electrode layers 13 and 14 stacked alternately in the stacking axis direction. The internal electrode layers 13 and 14 are divided into a first group and a second group every other layer, and the end portions of the internal electrode layers 13 belonging to the first group are the first and second groups of the capacitor body 11. The end of the internal electrode layer 14 belonging to the second group is exposed to the end face of the first external terminal electrode 16A and connected to the first external terminal electrode 16A. It is exposed at the end face on the terminal electrode 16B side and is connected to the second external terminal electrode 16B. A plurality of the first external terminal electrodes 16A1, 16A2, 16A3, and 16A4 are provided on one end face of the capacitor body 11 so as to be spaced apart from each other in the width direction of the end face, and the second external terminal electrode 16B1. , 16B2, 16B3, and 16B4 are provided on the other end face of the capacitor body 11 so as to be spaced apart from each other in the width direction of the end face. Further, the internal electrode layer 13 belonging to the first group is disposed at the approximate center of one main surface of the ferroelectric layer 12A and is opposed to each other with the ferroelectric layer 12A interposed therebetween. And a plurality of lead portions 13b1, 13b2, 13b3, 13b4 projecting from the capacitance forming portion 13a only to one end face side of the pair of end faces. The leading ends of the lead portions 13b1, 13b2, 13b3, 13b4 are connected to the corresponding first external terminal electrodes 16A1, 16A2, 16A3, 16A4, respectively. Similarly, the internal electrode layer 14 belonging to the second group includes a plurality of capacitance forming portions 14a protruding from the capacitance forming portion 14a only to the other end face side of the pair of end faces. Led-out portions 14b1, 14b2, 14b3, 14b4. The leading ends of the lead portions 14b1, 14b2, 14b3, 14b4 are connected to the corresponding second external terminal electrodes 16B1.16B2.16B3, 16B4, respectively.

次に、本実施形態の積層セラミックコンデンサ１０を実装するための回路基板２１について、図３を用いて説明する。 回路基板２１は、一方の主面に、第１の配線２５Ａおよび該第１の配線２５Ａに接続された第１のランド電極２６Ａと、第２の配線２５Ｂおよび該第２の配線２５Ｂに接続された第２のランド電極２６Ｂと、を有する。 前記一対のランド電極２６Ａ，２６Ｂ上には、所定の開口を備えたメタルマスク等を用いて予め半田ペースト等が孔版印刷され、予備はんだ層２７’が形成されている。 Next, a circuit board 21 for mounting the multilayer ceramic capacitor 10 of the present embodiment will be described with reference to FIG. The circuit board 21 is connected to one main surface of the first wiring 25A, the first land electrode 26A connected to the first wiring 25A, the second wiring 25B, and the second wiring 25B. And a second land electrode 26B. On the pair of land electrodes 26A, 26B, a solder paste or the like is stencil printed in advance using a metal mask or the like having a predetermined opening to form a preliminary solder layer 27 '.

次に、本発明のコンデンサ実装回路基板の第１の実施形態について、図４を参照して説明する。図４は、本発明の第１の実施形態のコンデンサ実装回路基板２０を示す要部の拡大斜視図である。 Next, a first embodiment of the capacitor-mounted circuit board of the present invention will be described with reference to FIG. FIG. 4 is an enlarged perspective view of a main part showing the capacitor-mounted circuit board 20 according to the first embodiment of the present invention.

図４に示すように、本実施形態のコンデンサ実装回路基板２０は、回路基板２１上に前記第１の実施形態の積層セラミックコンデンサ１０が搭載されたコンデンサ実装回路基板２０である。そして、前記積層セラミックコンデンサ１０の一方の端面の前記第１のグループに属する内部電極層１３に接続された複数の第１の外部端子電極１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４が前記回路基板２１上の一対のランド電極２６Ａ，２６Ｂのうちの一方のランド電極２６Ａに共に半田２７により導電接続されている。同様に、前記コンデンサ１０の他方の端面の前記第２のグループに属する内部電極層１４に接続された複数の第２の外部端子電極１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４が前記回路基板２１上の一対のランド電極２６Ａ，２６Ｂのうちの他方のランド電極２６Ｂに共に導電接続されている。 As shown in FIG. 4, the capacitor-mounted circuit board 20 of the present embodiment is a capacitor-mounted circuit board 20 in which the multilayer ceramic capacitor 10 of the first embodiment is mounted on a circuit board 21. A plurality of first external terminal electrodes 16A1, 16A2, 16A3, 16A4 connected to the internal electrode layer 13 belonging to the first group on one end face of the multilayer ceramic capacitor 10 are a pair on the circuit board 21. Both of the land electrodes 26A and 26B are conductively connected by solder 27 to one land electrode 26A. Similarly, a plurality of second external terminal electrodes 16B1, 16B2, 16B3, and 16B4 connected to the internal electrode layer 14 belonging to the second group on the other end face of the capacitor 10 are paired on the circuit board 21. Both of the land electrodes 26A and 26B are conductively connected to the other land electrode 26B.

次に、本実施形態の積層セラミックコンデンサ１０の製造プロセスの一例について、説明する。 まず、本実施形態の積層セラミックコンデンサ１０のコンデンサ本体１１を準備する。コンデンサ本体１１は、各種の公知の手法から任意に選択して用いることができる。 例えば、チタン酸バリウムを主成分とする強誘電体セラミックの材料粉末とＰＶＢ（ポリビニルブチラール）等の有機バインダ及びエタノール等の有機溶媒を所定の比率で混合してセラミックスラリーを準備し、ドクターブレード法等の公知のシート化手段により所定の厚さに成形した後、所定の寸法にカットして、複数のセラミックグリーンシートを得る。セラミック強誘電体層１２Ａとなるべきセラミックグリーンシートの表面に、静電容量形成部１３ａと引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４とからなる第１のグループに属する内部電極層１３となるべき内部電極パターンをＮｉ電極材料ペースト、Ｃｕ電極材料ペースト等の電極材料ペーストをスクリーン印刷等により印刷形成する。同様に、セラミック強誘電体層１２Ｂとなるべきセラミックグリーンシートの表面に、静電容量形成部１４ａと引き出し部１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４とからなる第２のグループに属する内部電極層１４となるべき内部電極パターンを電極材料ペーストをスクリーン印刷等により印刷形成する。これらのセラミックグリーンシートを交互に積層するとともに、積
層軸方向の一方の端部側および他方の端部側に、電極材料ペーストを印刷しないカバー層１２，１２となるべきセラミックグリーンシートをそれぞれ積層して積層体を形成する。次に、得られた積層体を前記引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４，および引き出し部１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４の先端がそれぞれ端面となるべき断面に露出するように図示省略したカットラインに沿って押し切り等により切断して積層体チップを得る。次に、得られた積層体チップの角部及び稜線部分に回転バレルやサンドブラスト法等を用いて面取りを行う。次に、得られた積層体チップを脱脂したのち、還元性雰囲気中で所定の温度プロファイルで焼成し、さらに中性もしくは酸化性雰囲気中で再酸化熱処理して、互いに対向する一対の端面のうちの一方の端面に引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４の各先端が、また、他方の端面に引き出し部１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４の各先端がそれぞれ露出されたコンデンサ本体１１を得る。 Next, an example of a manufacturing process for the multilayer ceramic capacitor 10 of the present embodiment will be described. First, the capacitor body 11 of the multilayer ceramic capacitor 10 of this embodiment is prepared. The capacitor body 11 can be arbitrarily selected from various known methods. For example, a ceramic slurry is prepared by mixing a ferroelectric ceramic material powder mainly composed of barium titanate, an organic binder such as PVB (polyvinyl butyral) and an organic solvent such as ethanol in a predetermined ratio, and a doctor blade method. After forming into a predetermined thickness by a known sheet forming means such as the above, a plurality of ceramic green sheets are obtained by cutting into a predetermined dimension. On the surface of the ceramic green sheet to be the ceramic ferroelectric layer 12A, the internal electrode to be the internal electrode layer 13 belonging to the first group consisting of the capacitance forming portion 13a and the lead portions 13b1, 13b2, 13b3, 13b4 The pattern is formed by printing an electrode material paste such as a Ni electrode material paste or a Cu electrode material paste by screen printing or the like. Similarly, on the surface of the ceramic green sheet to be the ceramic ferroelectric layer 12B, the internal electrode layer 14 belonging to the second group consisting of the capacitance forming portion 14a and the lead portions 14b1, 14b2, 14b3, 14b4 is formed. The internal electrode pattern to be formed is formed by printing an electrode material paste by screen printing or the like. These ceramic green sheets are alternately laminated, and ceramic green sheets to be the cover layers 12 and 12 on which the electrode material paste is not printed are laminated on one end side and the other end side in the lamination axis direction. To form a laminate. Next, the obtained laminate is cut to a cut line (not shown) so that the leading ends of the leading portions 13b1, 13b2, 13b3, 13b4 and the leading portions 14b1, 14b2, 14b3, and 14b4 are exposed on the cross-sections that should be end surfaces. Then, the laminate chip is obtained by cutting along a press cut or the like. Next, chamfering is performed on corners and ridges of the obtained laminated chip using a rotating barrel, a sandblasting method, or the like. Next, after degreasing the obtained laminated chip, it is fired at a predetermined temperature profile in a reducing atmosphere, and further subjected to re-oxidation heat treatment in a neutral or oxidizing atmosphere, and a pair of end faces facing each other. The capacitor body 11 is obtained in which the leading ends of the lead portions 13b1, 13b2, 13b3, and 13b4 are exposed on one end surface of the capacitor, and the leading ends of the lead portions 14b1, 14b2, 14b3, and 14b4 are exposed on the other end surface.

次に、該コンデンサ本体１１の互いに対向する一対の側面にＣｕ電極材料等の外部電極材料ペーストをスクリーン印刷法や転写法等により塗布し、所定の雰囲気及び温度プロファイルで焼付けして、前記第１のグループに属する内部電極層１３の引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４に接続された外部端子電極１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４、および前記第２のグループに属する内部電極層１４の引き出し部１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４に接続された外部端子電極１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４を形成して、積層セラミックコンデンサ１０を得る。なお、本発明は、前記内部電極層１３、１４、および前記外部端子電極１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４，１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４として、Ｐｄ電極ペースト、Ａｇ−Ｐｄ電極ペースト等を用いても良く、これらペーストを用いるときは大気雰囲気で焼成しても良い。 Next, an external electrode material paste such as a Cu electrode material is applied to a pair of side surfaces facing each other of the capacitor body 11 by a screen printing method, a transfer method or the like, and baked in a predetermined atmosphere and temperature profile. External terminal electrodes 16A1, 16A2, 16A3, and 16A4 connected to the lead portions 13b1, 13b2, 13b3, and 13b4 of the internal electrode layer 13 belonging to the second group, and the lead portions 14b1 of the internal electrode layer 14 that belong to the second group. The external terminal electrodes 16B1, 16B2, 16B3, and 16B4 connected to 14b2, 14b3, and 14b4 are formed to obtain the multilayer ceramic capacitor 10. In the present invention, a Pd electrode paste, an Ag-Pd electrode paste, or the like may be used as the internal electrode layers 13 and 14 and the external terminal electrodes 16A1, 16A2, 16A3, 16A4, 16B1, 16B2, 16B3, and 16B4. Well, when these pastes are used, they may be fired in an air atmosphere.

次に、上記セラミック強誘電体層１２，１２Ａ，１２Ｂの好ましい実施形態は次の通りである。すなわち、上記強誘電体層１２，１２Ａ，１２Ｂとしては、チタン酸バリウム等を主成分とする強誘電体セラミックからなるものが好ましい。前記強誘電体セラミックの材料粉末と有機バインダとを含有するセラミックスラリーから、ドクターブレード法等によりセラミックグリーンシートを作成し、必要により積層したのち、前記強誘電体セラミックの焼結する温度で焼成して得られる。 また、上記セラミック強誘電体層１２，１２Ａ，１２Ｂは、これに限定するものではなく、他の公知の強誘電体セラミックを用いることができる。 Next, a preferred embodiment of the ceramic ferroelectric layers 12, 12A, 12B is as follows. That is, the ferroelectric layers 12, 12A, 12B are preferably made of a ferroelectric ceramic mainly composed of barium titanate or the like. From a ceramic slurry containing the ferroelectric ceramic material powder and an organic binder, a ceramic green sheet is prepared by a doctor blade method or the like, laminated as necessary, and then fired at a temperature at which the ferroelectric ceramic is sintered. Obtained. The ceramic ferroelectric layers 12, 12A, 12B are not limited to this, and other known ferroelectric ceramics can be used.

次に、上記内部電極層１３，１４の好ましい実施形態は次の通りである。すなわち、上記内部電極層１３，１４としては、Ｎｉ，Ｃｕ、等の金属もしくは前記金属の少なくとも一方を含む合金であってもよい。また、内部電極層１３，１４には、前記セラミック強誘電体層１２，１２Ａ，１２Ｂとの密着性を向上させる目的で前記強誘電体セラミックの粉末を微量添加したものであってもよい。上記内部電極層１３は、前記略長方形状のセラミック強誘電体層１２Ａの一方の主面のそれぞれ略中央に配置され前記強誘電体層１２Ａを挟んで互いに対向する略矩形状の静電容量形成部１３ａと、該静電容量形成部１３ａから前記一対の端面のうちの一方の端面側のみに突出された複数の引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４とを有し、該引き出し部１３ｂ1，１３ｂ２，１３ｂ３，１３ｂ４の先端が、対応する前記第１の外部端子電極１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４にそれぞれ接続されていることが好ましい。同様に、上記内部電極層１４は、前記略長方形状のセラミック強誘電体層１２Ｂの一方の主面のそれぞれ略中央に配置され前記強誘電体層１２Ｂを挟んで対向する略矩形状の静電容量形成部１４ａと、概静電容量形成部１４ａから前記一対の端面のうちの他方の端面側のみに突出された複数の引き出し部１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４の先端が、対応する前記第２の外部端子電極１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４にそれぞれ接続されていることが好ましい。 Next, a preferred embodiment of the internal electrode layers 13 and 14 is as follows. That is, the internal electrode layers 13 and 14 may be a metal such as Ni or Cu or an alloy containing at least one of the metals. The internal electrode layers 13 and 14 may be obtained by adding a small amount of the ferroelectric ceramic powder for the purpose of improving adhesion to the ceramic ferroelectric layers 12, 12 </ b> A and 12 </ b> B. The internal electrode layer 13 is disposed in the approximate center of one main surface of the substantially rectangular ceramic ferroelectric layer 12A, and has a substantially rectangular capacitance formation facing each other across the ferroelectric layer 12A. Part 13a and a plurality of lead parts 13b1, 13b2, 13b3, 13b4 projecting from the capacitance forming part 13a only to one end face side of the pair of end faces, and the lead parts 13b1, 13b2 , 13b3, 13b4 are preferably connected to the corresponding first external terminal electrodes 16A1, 16A2, 16A3, 16A4, respectively. Similarly, the internal electrode layer 14 is disposed in the approximate center of one main surface of the substantially rectangular ceramic ferroelectric layer 12B, and is opposed to the substantially rectangular electrostatic capacitor that is opposed to the ferroelectric layer 12B. The leading ends of the capacitance forming portion 14a and the plurality of lead portions 14b1, 14b2, 14b3, and 14b4 protruding from the approximate capacitance forming portion 14a only to the other end face side of the pair of end faces correspond to the second ones. Are preferably connected to the external terminal electrodes 16B1, 16B2, 16B3, and 16B4, respectively.

次に、上記コンデンサ本体１１の好ましい実施形態は次の通りである。すなわち、上記コンデンサ本体１１としては、略直方体状のものが好ましいが、これに限定するものではなく、例えば、高さ寸法が幅寸法及び長さ寸法に比べて小さい平板状であってもよい。 Next, a preferred embodiment of the capacitor body 11 is as follows. That is, the capacitor body 11 is preferably a substantially rectangular parallelepiped, but is not limited thereto, and may be, for example, a flat plate whose height is smaller than the width and length.

次に、上記複数の外部端子電極１６Ａ、１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４，１６Ｂ、１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４の好ましい実施形態は次の通りである。すなわち、上記複数の外部端子電極１６Ａ、１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４，１６Ｂ、１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４としては、前記コンデンサ本体１１の前記互いに対向する一対の端面に、前記第１のグループに属する内部電極層１３の複数の引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４、および前記第２のグループに属する内部電極層１４の複数の引き出し部１４ｂ1、１４ｂ２，１４ｂ３，１４ｂ４にそれぞれ対応するように設けられていることが好ましい。上記外部端子電極１６Ａ、１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４，１６Ｂ、１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４の形成方法としては、Ｎｉ，Ｃｕ等の電極材料ペーストの塗布焼付、Ａｇ粉末を含む導電性樹脂ペーストの塗布硬化、電極材料のスパッタリング等により形成されることが好ましい。また、上記外部端子電極の表面に、必要により、Ｎｉメッキ、Ｃｕメッキ、ハンダメッキ等を形成することが好ましい。 Next, preferred embodiments of the plurality of external terminal electrodes 16A, 16A1, 16A2, 16A3, 16A4, 16B, 16B1, 16B2, 16B3, and 16B4 are as follows. That is, the plurality of external terminal electrodes 16A, 16A1, 16A2, 16A3, 16A4, 16B, 16B1, 16B2, 16B3, and 16B4 are arranged on the pair of end faces facing each other of the capacitor body 11 in the first group. The plurality of lead portions 13b1, 13b2, 13b3, and 13b4 of the internal electrode layer 13 belonging to and the plurality of lead portions 14b1, 14b2, 14b3, and 14b4 of the internal electrode layer 14 belonging to the second group are provided. It is preferable. The external terminal electrodes 16A, 16A1, 16A2, 16A3, 16A4, 16B, 16B1, 16B2, 16B3, and 16B4 can be formed by applying and baking an electrode material paste such as Ni or Cu, or using a conductive resin paste containing Ag powder. It is preferably formed by coating and curing, sputtering of an electrode material, or the like. Further, it is preferable to form Ni plating, Cu plating, solder plating or the like on the surface of the external terminal electrode, if necessary.

（実施例）次に、本発明の第１の実施形態の積層セラミックコンデンサ１０の実施例について説明する。積層セラミックコンデンサ１０の外形寸法は、幅３．２ｍｍ、長さ１．６ｍｍ、高さ１．１５ｍｍである。上記セラミック強誘電体層１２，１２Ａ，１２Ｂの材質は、チタン酸バリウムを主成分とする強誘電体セラミックであり、寸法は、幅３．２ｍｍ、長さ１．６ｍｍ、厚さ１２μｍである。また、上記内部電極層１３，１４の材質は、Ｎｉであり、該内部電極層１３，１４の静電容量形成部１３ａ，１４ａの寸法は、幅２．８ｍｍ、長さ１．１ｍｍ、厚さ１．５μｍである。また、上記内部電極層１３，１４の上記引き出し部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４，１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４の材質は、上記静電容量形成部と同様にＮｉであり、寸法は、幅０．２３ｍｍ、長さ０．１５ｍｍであり、前記静電容量形成部１３ａ，１４ａの幅方向の一方の長辺のみにそれぞれ４箇所ずつ設けられている。また、上記外部端子電極１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４，１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４の材質は、Ｎｉであり、寸法は、幅０．４６ｍｍ、前記コンデンサ本体の上下両主面の回りこみ部分の長さ０．２８ｍｍ、厚さ１０μｍであり、前記コンデンサ本体１１の互いに対向する一対の端面およびその近傍にそれぞれ４箇所ずつ設けられている。 (Example) Next, an example of the multilayer ceramic capacitor 10 of the first embodiment of the present invention will be described. The outer dimensions of the multilayer ceramic capacitor 10 are a width of 3.2 mm, a length of 1.6 mm, and a height of 1.15 mm. The material of the ceramic ferroelectric layers 12, 12A, 12B is a ferroelectric ceramic mainly composed of barium titanate, and the dimensions are 3.2 mm in width, 1.6 mm in length, and 12 μm in thickness. The material of the internal electrode layers 13 and 14 is Ni. The dimensions of the capacitance forming portions 13a and 14a of the internal electrode layers 13 and 14 are 2.8 mm in width, 1.1 mm in length, and thickness. 1.5 μm. Further, the material of the lead portions 13b1, 13b2, 13b3, 13b4, 14b1, 14b2, 14b3, and 14b4 of the internal electrode layers 13 and 14 is Ni as in the capacitance forming portion, and the dimension is 0 width. .23 mm and a length of 0.15 mm, and four locations are provided only on one long side in the width direction of the capacitance forming portions 13a and 14a. The external terminal electrodes 16A1, 16A2, 16A3, 16A4, 16B1, 16B2, 16B3, and 16B4 are made of Ni, and have a width of 0.46 mm. The length is 0.28 mm and the thickness is 10 μm, and four positions are provided on each of the pair of opposing end surfaces of the capacitor body 11 and in the vicinity thereof.

上記実施例の積層セラミックコンデンサ１０について、一対の回路配線及び一対のランド電極が形成された幅１０２ｍｍ、長さ４１ｍｍ、厚さ１．５ｍｍのガラスーエポキシ樹脂系回路基板の前記ランド電極上に市販の鉛フリー半田にて２８０℃でリフロー半田付け実装した。得られたコンデンサ実装回路基板２０の前記一対の回路配線にＤＣ２０Ｖ−ＡＣ５Ｖｐｐを印加した時の音鳴きを、雑音測定装置にて人の可聴帯域である１００〜２００００Ｈｚの範囲で測定し、５００Ｈｚにおける値を図９に示す従来のＬ−Ｗ逆転構造の積層セラミックコンデンサ１１０が搭載されたコンデンサ実装回路基板と比較した。その結果、本実施例のコンデンサ実装回路基板２０の音鳴きは、２２ｄＢとなり、同一寸法の前記従来のＬ−Ｗ逆転タイプの積層セラミックコンデンサ１１０が搭載されたコンデンサ実装回路基板の音鳴き２６ｄＢと比較して低減されていた。また、絶縁抵抗計にて２５ＶＤＣを印加してから６０秒後の絶縁抵抗（ＩＲ）を測定し、Ｃ・ＩＲ積を求めた結果、６９１１ＭΩ・μＦとなり、同一形状の４連アレイ品における６０４９ＭΩ・μＦより高いことが確認された。 The multilayer ceramic capacitor 10 of the above embodiment is commercially available on the land electrode of a glass-epoxy resin circuit board having a width of 102 mm, a length of 41 mm, and a thickness of 1.5 mm on which a pair of circuit wires and a pair of land electrodes are formed. Reflow soldering mounting was performed at 280 ° C. with lead-free solder. The noise when DC20V-AC5Vpp is applied to the pair of circuit wirings of the obtained capacitor-mounted circuit board 20 is measured in a range of 100 to 20000 Hz which is a human audible band with a noise measuring device, and the value at 500 Hz. Was compared with the capacitor-mounted circuit board on which the multilayer ceramic capacitor 110 having the conventional LW reverse structure shown in FIG. 9 is mounted. As a result, the sound of the capacitor-mounted circuit board 20 of this example is 22 dB, which is compared with the sound of 26 dB of the capacitor-mounted circuit board on which the conventional LW reverse type multilayer ceramic capacitor 110 having the same dimensions is mounted. Was reduced. Moreover, the insulation resistance (IR) 60 seconds after applying 25 VDC with an insulation resistance meter was measured, and the C · IR product was obtained. As a result, it was 6911 MΩ · μF, and 6049 MΩ · It was confirmed to be higher than μF.

次に、本発明の積層セラミックコンデンサの第２の実施形態について、図５〜図８を参照して説明する。図５は第２の実施形態の積層セラミックコンデンサ３０の全体構造を示す外観斜視図であり、図６は、該積層セラミックコンデンサ３０のコンデンサ本体３１の内部構造を示す分解斜視図である。また、図７は、本実施形態の積層セラミックコンデンサ３０を回路基板４１上へ搭載する方法を示す部分拡大斜視図である。図８は、前記積層セラミックコンデンサ３０を実装した本発明の第２の実施形態のコンデンサ実装回路基板４０を示す部分拡大斜視図である。 Next, a second embodiment of the multilayer ceramic capacitor of the present invention will be described with reference to FIGS. FIG. 5 is an external perspective view showing the overall structure of the multilayer ceramic capacitor 30 of the second embodiment, and FIG. 6 is an exploded perspective view showing the internal structure of the capacitor body 31 of the multilayer ceramic capacitor 30. FIG. 7 is a partially enlarged perspective view showing a method for mounting the multilayer ceramic capacitor 30 of the present embodiment on the circuit board 41. FIG. 8 is a partially enlarged perspective view showing a capacitor-mounted circuit board 40 according to the second embodiment of the present invention on which the multilayer ceramic capacitor 30 is mounted.

図５および図６に示すように、本実施形態の積層セラミックコンデンサ３０は、略直方体形状のコンデンサ本体３１と該コンデンサ本体３１の互いに対向する一対の端面およびその近傍にそれぞれ形成された第１の外部端子電極３６Ａと第２の外部端子電極３６Ｂとを備えている。そして、前記コンデンサ本体３１は矩形の強誘電体層３２Ａ，３２Ｂと内部電極層３３，３４とが交互に且つ積層軸方向に複数積層されてなる。また、前記内部電極層３３，３４は一層置きに第１のグループと第２のグループとに分かれて属し、前記第１のグループに属する内部電極層３３の端部は前記コンデンサ本体３１の前記第１の外部端子電極３６Ａ側の端面に露出して該第１の外部端子電極３６Ａに接続され、前記第２のグループに属する内部電極層３４の端部は前記コンデンサ本体３１の前記第２の外部端子電極３６Ｂ側の端面に露出して該第２の外部端子電極３６Ｂに接続されている。そして、前記第１の外部端子電極３６Ａ１，３６Ａ２，３６Ａ３，３６Ａ４，３６Ａ５は、前記コンデンサ本体３１の一方の端面に該端面の幅方向に互いに離間して複数設けられるとともに、前記第２の外部端子電極３６Ｂ１，３６Ｂ２，３６Ｂ３，３６Ｂ４，３６Ｂ５は、前記コンデンサ本体３１の他方の端面に該端面の幅方向に互いに離間して複数設けられている。さらに、前記第１のグループに属する内部電極層３３は、前記強誘電体層３２Ａの一方の主面の略中央に配置され前記強誘電体層３２Ａを挟んで互いに対向する静電容量形成部３３ａと、該静電容量形成部３３ａから前記一対の端面のうちの一方の端面側のみに突出された複数の引き出し部３３ｂ１，３３ｂ２，３３ｂ３，３３ｂ４，３３ｂ５とを有する。そして、該引き出し部３３ｂ１，３３ｂ２，３３ｂ３，３３ｂ４，３３ｂ５の先端が、対応する前記第１の外部端子電極３６Ａ１，３６Ａ２，３６Ａ３，３６Ａ４，３６Ａ５にそれぞれ接続されている。同様に、前記第２のグループに属する内部電極層３４は、前記静電容量形成部３４ａと、該静電容量形成部３４ａから前記一対の端面のうちの他方の端面側のみに突出された複数の引き出し部３４ｂ１，３４ｂ２，３４ｂ３，３４ｂ４，３４ｂ５とを有する。そして、該引き出し部３４ｂ１，３４ｂ２，３４ｂ３，３４ｂ４，３４ｂ５の先端が、対応する前記第２の外部端子電極３６Ｂ１．３６Ｂ２．３６Ｂ３，３６Ｂ４，３６Ｂ５にそれぞれ接続されている。 As shown in FIGS. 5 and 6, the multilayer ceramic capacitor 30 of the present embodiment includes a capacitor body 31 having a substantially rectangular parallelepiped shape, a first pair of end faces facing each other and the vicinity of the capacitor body 31. An external terminal electrode 36A and a second external terminal electrode 36B are provided. The capacitor body 31 is formed by laminating a plurality of rectangular ferroelectric layers 32A and 32B and internal electrode layers 33 and 34 alternately in the stacking axis direction. The internal electrode layers 33 and 34 are divided into a first group and a second group every other layer, and the end portions of the internal electrode layers 33 belonging to the first group belong to the first body of the capacitor body 31. The end of the internal electrode layer 34 belonging to the second group is exposed to the end face of the first external terminal electrode 36A and connected to the first external terminal electrode 36A, and is connected to the second external terminal electrode 36A. It is exposed at the end face on the terminal electrode 36B side and is connected to the second external terminal electrode 36B. A plurality of the first external terminal electrodes 36A1, 36A2, 36A3, 36A4, 36A5 are provided on one end face of the capacitor body 31 so as to be spaced apart from each other in the width direction of the end face, and the second external terminal A plurality of electrodes 36B1, 36B2, 36B3, 36B4, and 36B5 are provided on the other end face of the capacitor body 31 so as to be separated from each other in the width direction of the end face. Further, the internal electrode layer 33 belonging to the first group is disposed at the approximate center of one main surface of the ferroelectric layer 32A and is opposed to each other with the ferroelectric layer 32A interposed therebetween. And a plurality of lead portions 33b1, 33b2, 33b3, 33b4, 33b5 projecting from the capacitance forming portion 33a only to one end surface side of the pair of end surfaces. The leading ends of the lead portions 33b1, 33b2, 33b3, 33b4, 33b5 are connected to the corresponding first external terminal electrodes 36A1, 36A2, 36A3, 36A4, 36A5, respectively. Similarly, the internal electrode layer 34 belonging to the second group includes a plurality of capacitance forming portions 34a that protrude from the capacitance forming portion 34a only to the other end face side of the pair of end faces. The lead portions 34b1, 34b2, 34b3, 34b4, 34b5. The leading ends of the lead portions 34b1, 34b2, 34b3, 34b4, 34b5 are connected to the corresponding second external terminal electrodes 36B1.36B2.36B3, 36B4, 36B5, respectively.

本実施形態の積層セラミックコンデンサ３０が先の第１の実施形態の積層セラミックコンデンサ１０と異なる点は、本実施形態の積層セラミックコンデンサ３０は、上記第１の課題解決手段に加えてさらに、（２）前記複数の外部端子電極３６Ａ１，３６Ａ２，３６Ａ３，３６Ａ４，３６Ａ５，３６Ｂ１，３６Ｂ２，３６Ｂ３，３６Ｂ４，３６Ｂ５が、前記互いに対向する一対の端面のそれぞれにおいて、該端面の幅方向の中心に近い外部端子電極ほど幅寸法が大きいものである。具体的には、前記一方の端面に形成された複数（例えば５つ）の第１の外部端子電極３６Ａ１，３６Ａ２，３６Ａ３，３６Ａ４，３６Ａ５のうち、前記端面の幅方向の中心に最も近い外部端子電極３６Ａ３の幅寸法が最も大きく、次いで、外部端子電極３６Ａ２，３６Ａ４の幅寸法が
大きく、前記端面の幅方向の中心から最も遠い外部端子電極３６Ａ１，３６Ａ５の幅寸法が最も小さい。他方の端面に形成された複数の第２の外部端子電極３６Ｂ１，３６Ｂ２，３６Ｂ３，３６Ｂ４，３６Ｂ５についても同様である。このため、積層セラミックコンデンサ３０の幅方向の変位が小さくなる前記端面の幅方向の中心に近い幅広の外部端子電極３６Ａ３，３６Ｂ３で重点的に回路基板に拘束され、これに比べて振動時の変位が大きい前記端面の幅方向の両端近傍の外部端子電極３６Ａ１，３６Ａ５，３６Ｂ１，３６Ｂ５では回路基板４１に拘束される度合いが弱まる。これにより、回路基板４１への振動の伝達が抑制される。 The multilayer ceramic capacitor 30 of the present embodiment is different from the multilayer ceramic capacitor 10 of the first embodiment in that the multilayer ceramic capacitor 30 of the present embodiment further includes (2 ) The plurality of external terminal electrodes 36A1, 36A2, 36A3, 36A4, 36A5, 36B1, 36B2, 36B3, 36B4, and 36B5 are external terminals that are close to the center in the width direction of the pair of end surfaces facing each other. The width dimension of the electrode is larger. Specifically, of the plurality of (for example, five) first external terminal electrodes 36A1, 36A2, 36A3, 36A4, and 36A5 formed on the one end surface, the external terminal closest to the center in the width direction of the end surface The width dimension of the electrode 36A3 is the largest, then the width dimension of the external terminal electrodes 36A2 and 36A4 is large, and the width dimension of the external terminal electrodes 36A1 and 36A5 farthest from the center in the width direction of the end face is the smallest. The same applies to the plurality of second external terminal electrodes 36B1, 36B2, 36B3, 36B4, and 36B5 formed on the other end face. For this reason, the displacement in the width direction of the multilayer ceramic capacitor 30 is constrained to the circuit board mainly by the wide external terminal electrodes 36A3 and 36B3 close to the center in the width direction of the end face. In the external terminal electrodes 36A1, 36A5, 36B1, and 36B5 in the vicinity of both ends in the width direction of the end face having a large width, the degree of restraint by the circuit board 41 is weakened. Thereby, transmission of vibration to the circuit board 41 is suppressed.

次に、本実施形態の積層セラミックコンデンサ３０を実装するための回路基板４１について、図７を用いて説明する。 回路基板４１は、一方の主面に、第１の配線４５Ａおよび該第１の配線４５Ａに接続された第１のランド電極４６Ａと、第２の配線４５Ｂおよび該第２の配線４５Ｂに接続された第２のランド電極４６Ｂと、を有する。 前記一対のランド電極４６Ａ，４６Ｂ上には、所定の開口を備えたメタルマスク等を用いて予め半田ペースト等が孔版印刷され、予備はんだ層４７が形成されている。 Next, a circuit board 41 for mounting the multilayer ceramic capacitor 30 of the present embodiment will be described with reference to FIG. The circuit board 41 is connected to one main surface of the first wiring 45A and the first land electrode 46A connected to the first wiring 45A, the second wiring 45B, and the second wiring 45B. And a second land electrode 46B. On the pair of land electrodes 46A, 46B, a solder paste or the like is stencil-printed in advance using a metal mask or the like having a predetermined opening, and a preliminary solder layer 47 is formed.

次に、本発明のコンデンサ実装回路基板の第２の実施形態について、図８を参照して説明する。図８は、本発明の第２の実施形態のコンデンサ実装回路基板４０を示す要部の拡大斜視図である。 Next, a second embodiment of the capacitor-mounted circuit board of the present invention will be described with reference to FIG. FIG. 8 is an enlarged perspective view of a main part showing a capacitor-mounted circuit board 40 according to the second embodiment of the present invention.

図８に示すように、本実施形態のコンデンサ実装回路基板４０は、回路基板４１上に前記第２の実施形態の積層セラミックコンデンサ３０が搭載されたコンデンサ実装回路基板４０である。そして、前記積層セラミックコンデンサ３０の一方の端面の前記第１のグループに属する内部電極層３３に接続された複数の第１の外部端子電極３６Ａ１，３６Ａ２，３６Ａ３，３６Ａ４，３６Ａ５が前記回路基板４１上の一対のランド電極４６Ａ，４６Ｂのうちの一方のランド電極４６Ａに共に半田等により導電接続されている。また、前記コンデンサ３０の他方の端面の前記第２のグループに属する内部電極層３４に接続された複数の第２の外部端子電極３６Ｂ１，３６Ｂ２，３６Ｂ３，３６Ｂ４および３６Ｂ５が前記回路基板４１上の一対のランド電極４６Ａ，４６Ｂのうちの他方のランド電極４６Ｂに共に導電接続されている。 その他の構成、およびその作用効果は、先の第１の実施形態と同様であるため、説明を省略する。 As shown in FIG. 8, the capacitor-mounted circuit board 40 of the present embodiment is a capacitor-mounted circuit board 40 in which the multilayer ceramic capacitor 30 of the second embodiment is mounted on a circuit board 41. A plurality of first external terminal electrodes 36A1, 36A2, 36A3, 36A4, 36A5 connected to the internal electrode layer 33 belonging to the first group on one end face of the multilayer ceramic capacitor 30 are formed on the circuit board 41. The one land electrode 46A of the pair of land electrodes 46A and 46B is conductively connected together by solder or the like. A plurality of second external terminal electrodes 36 B 1, 36 B 2, 36 B 3, 36 B 4 and 36 B 5 connected to the internal electrode layer 34 belonging to the second group on the other end face of the capacitor 30 are paired on the circuit board 41. The other land electrode 46B is electrically conductively connected to the other land electrode 46B. Since other configurations and the operation and effects thereof are the same as those of the first embodiment, description thereof is omitted.

本発明によれば、セラミック強誘電体層を備えた積層セラミックコンデンサ及び該コンデンサを搭載したコンデンサ実装回路基板に好適である。 The present invention is suitable for a multilayer ceramic capacitor having a ceramic ferroelectric layer and a capacitor-mounted circuit board on which the capacitor is mounted.

本発明の積層セラミックコンデンサの第１の実施形態の全体構造を示す外観斜視図である。1 is an external perspective view showing an overall structure of a first embodiment of a multilayer ceramic capacitor of the present invention. 前記第１の実施形態の積層セラミックコンデンサのコンデンサ本体の内部構造を示す分解斜視図である。It is a disassembled perspective view which shows the internal structure of the capacitor | condenser main body of the multilayer ceramic capacitor of the said 1st Embodiment. 前記第１の実施形態の積層セラミックコンデンサを回路基板に実装する方法を示す要部の外観斜視図である。It is an external appearance perspective view of the principal part which shows the method of mounting the multilayer ceramic capacitor of the said 1st Embodiment on a circuit board. 本発明のコンデンサ実装回路基板の第１の実施形態を示す要部の斜視図である。It is a perspective view of the principal part which shows 1st Embodiment of the capacitor | condenser mounting circuit board of this invention. 本発明の積層セラミックコンデンサの第２の実施形態の全体構造を示す外観斜視図である。It is an external appearance perspective view which shows the whole structure of 2nd Embodiment of the multilayer ceramic capacitor of this invention. 前記第２の実施形態の積層セラミックコンデンサのコンデンサ本体の内部構造を示す分解斜視図である。It is a disassembled perspective view which shows the internal structure of the capacitor | condenser main body of the multilayer ceramic capacitor of the said 2nd Embodiment. 前記第２の実施形態の積層セラミックコンデンサを回路基板に実装する方法を示す要部の外観斜視図である。It is an external appearance perspective view of the principal part which shows the method of mounting the multilayer ceramic capacitor of the said 2nd Embodiment on a circuit board. 本発明のコンデンサ実装回路基板の第２の実施形態を示す要部の斜視図である。It is a perspective view of the principal part which shows 2nd Embodiment of the capacitor | condenser mounting circuit board of this invention. 背景技術の積層セラミックコンデンサの一例の外観斜視図である。It is an external appearance perspective view of an example of the multilayer ceramic capacitor of background art. 前記背景技術の積層セラミックコンデンサのコンデンサ本体の内部構造を示す分解斜視図である。It is a disassembled perspective view which shows the internal structure of the capacitor | condenser main body of the multilayer ceramic capacitor of the said background art. 背景技術の積層セラミックコンデンサの他の例を示す外観斜視図である。It is an external appearance perspective view which shows the other example of the multilayer ceramic capacitor of background art. 背景技術の積層セラミックコンデンサの他の例を示す外観斜視図である。It is an external appearance perspective view which shows the other example of the multilayer ceramic capacitor of background art.

符号の説明Explanation of symbols

１０：積層セラミックコンデンサ１１：コンデンサ本体１２，１２Ａ，１２Ｂ：セラミック強誘電体層１３：第１のグループに属する内部電極層１３ａ：静電容量形成部１３ｂ１，１３ｂ２，１３ｂ３，１３ｂ４：引き出し部１４：第２のグループに属する内部電極層１４ａ：静電容量形成部１４ｂ１，１４ｂ２，１４ｂ３，１４ｂ４：引き出し部１６Ａ，１６Ａ１，１６Ａ２，１６Ａ３，１６Ａ４：外部端子電極１６Ｂ，１６Ｂ１，１６Ｂ２，１６Ｂ３，１６Ｂ４：外部端子電極２０：コンデンサ実装回路基板２１：回路基板２５Ａ：第１の配線２５Ｂ：第２の配線２６Ａ：ランド電極２６Ｂ：ランド電極２７：半田２７’：予備半田層３０：積層セラミックコンデンサ３１：コンデンサ本体３２，３２Ａ，３２Ｂ：セラミック強誘電体層３３：第１のグループに属する内部電極層３３ａ：静電容量形成部３３ｂ１，３３ｂ２，３３ｂ３，３３ｂ４，３３ｂ５：引き出し部３４：第２のグループに属する内部電極層３４ａ：静電容量形成部３４ｂ１，３４ｂ２，３４ｂ３，３４ｂ４，３４ｂ５：引き出し部３６Ａ，３６Ａ１，３６Ａ２，３６Ａ３，３６Ａ４，３６Ａ５：外部電極３６Ｂ，３６Ｂ１，３６Ｂ２，３６Ｂ３，３６Ｂ４，３６Ｂ５：外部電極４０：コンデンサ実装回路基板４１：回路基板４５Ａ：第１の配線４５Ｂ：第２の配線４６Ａ：ランド電極４６Ｂ：ランド電極４７：半田４７’：予備半田層 10: Multilayer ceramic capacitor 11: Capacitor bodies 12, 12A, 12B: Ceramic ferroelectric layer 13: Internal electrode layer 13a belonging to the first group: Capacitance forming portions 13b1, 13b2, 13b3, 13b4: Leading portion 14: Internal electrode layer 14a belonging to the second group: capacitance forming portions 14b1, 14b2, 14b3, 14b4: lead portions 16A, 16A1, 16A2, 16A3, 16A4: external terminal electrodes 16B, 16B1, 16B2, 16B3, 16B4: external Terminal electrode 20: Capacitor-mounted circuit board 21: Circuit board 25A: First wiring 25B: Second wiring 26A: Land electrode 26B: Land electrode 27: Solder 27 ′: Pre-solder layer 30: Multilayer ceramic capacitor 31: Capacitor body 32, 32A, 32B: Ceramic ferroelectric layer 3: Internal electrode layer 33a belonging to the first group: Capacitance forming portions 33b1, 33b2, 33b3, 33b4, 33b5: Leading portion 34: Internal electrode layer 34a belonging to the second group: Capacitance forming portion 34b1, 34b2, 34b3, 34b4, 34b5: Lead portions 36A, 36A1, 36A2, 36A3, 36A4, 36A5: External electrodes 36B, 36B1, 36B2, 36B3, 36B4, 36B5: External electrodes 40: Capacitor-mounted circuit board 41: Circuit board 45A: First wiring 45B: second wiring 46A: land electrode 46B: land electrode 47: solder 47 ′: preliminary solder layer

Claims (3)

略直方体形状のコンデンサ本体と該コンデンサ本体の互いに対向する一対の端面およびその近傍にそれぞれ形成された第１の外部端子電極と第２の外部端子電極とを備え、前記コンデンサ本体は矩形の強誘電体層と内部電極層とが交互に且つ積層軸方向に複数積層されてなり、前記内部電極層は一層置きに第１のグループと第２のグループとに分かれて属し、前記第１のグループに属する内部電極層の端部は前記コンデンサ本体の前記第１の外部端子電極側の端面に露出して該第１の外部端子電極に接続され、前記第２のグループに属する内部電極層の端部は前記コンデンサ本体の前記第２の外部端子電極側の端面に露出して該第２の外部端子電極に接続された積層セラミックコンデンサにおいて、前記第１の外部端子電極は、前記コンデンサ本体の一方の端面に該端面の幅方向に互いに離間して複数設けられるとともに、前記第２の外部端子電極は、前記コンデンサ本体の他方の端面に該端面の幅方向に互いに離間して複数設けられており、前記第１のグループに属する内部電極層は、前記強誘電体層の一方の主面の略中央に配置され前記強誘電体層を挟んで互いに対向する静電容量形成部と、該静電容量形成部から前記一対の端面のうちの一方の端面側のみに突出された複数の引き出し部とを有し、該引き出し部の先端が、対応する前記第１の外部端子電極にそれぞれ接続されており、前記第２のグループに属する内部電極層は、前記静電容量形成部と、該静電容量形成部から前記一対の端面のうちの他方の端面側のみに突出された複数の引き出し部とを有し、該引き出し部の先端が、対応する前記第２の外部端子電極にそれぞれ接続されていることを特徴とする積層セラミックコンデンサ。 A capacitor body having a substantially rectangular parallelepiped shape, and a first external terminal electrode and a second external terminal electrode respectively formed on and near a pair of opposing end surfaces of the capacitor body, the capacitor body having a rectangular ferroelectric shape The body layers and the internal electrode layers are alternately stacked in the stacking axis direction, and the internal electrode layers belong to the first group and the second group, and the internal electrode layers belong to the first group. An end portion of the internal electrode layer belonging to the second group is exposed at an end face of the capacitor main body exposed on the first external terminal electrode side and connected to the first external terminal electrode. Is a multilayer ceramic capacitor exposed on an end face of the capacitor body on the second external terminal electrode side and connected to the second external terminal electrode, wherein the first external terminal electrode is the capacitor A plurality of second external terminal electrodes are provided on one end face of the main body so as to be spaced apart from each other in the width direction of the end face, and a plurality of second external terminal electrodes are provided on the other end face of the capacitor main body so as to be spaced apart from each other in the width direction of the end face. The internal electrode layer belonging to the first group is disposed at substantially the center of one main surface of the ferroelectric layer and is opposed to each other across the ferroelectric layer; and A plurality of lead portions protruding only from one end face side of the pair of end faces from the capacitance forming portion, and the leading ends of the lead portions respectively correspond to the corresponding first external terminal electrodes. The internal electrode layers that are connected and belong to the second group include a plurality of capacitance forming portions and a plurality of protruding from the capacitance forming portions to only the other end face side of the pair of end faces. A drawer part, and the drawer part End, corresponding the second multilayer ceramic capacitor, characterized in that it is connected to the external terminal electrodes. 前記複数の外部端子電極は、前記互いに対向する一対の端面のそれぞれにおいて、該端面の幅方向の中心に近い外部端子電極ほど幅寸法が大きいことを特長とする請求項１記載の積層セラミックコンデンサ。 2. The multilayer ceramic capacitor according to claim 1, wherein each of the plurality of external terminal electrodes has a larger width dimension at each of the pair of end faces facing each other, closer to the center of the end face in the width direction. 回路基板上に前記請求項１記載の積層セラミックコンデンサが搭載されたコンデンサ実装回路基板であって、前記積層セラミックコンデンサの一方の端面の前記第１のグループに属する内部電極層に接続された複数の第１の外部端子電極が前記回路基板上の一対のランド電極のうちの一方のランド電極に共に導電接続されており、前記コンデンサの他方の端面の前記第２のグループに属する内部電極層に接続された複数の第２の外部端子電極が前記回路基板上の一対のランド電極のうちの他方のランド電極に共に導電接続されていることを特徴とするコンデンサ実装回路基板。 A capacitor-mounted circuit board on which the multilayer ceramic capacitor according to claim 1 is mounted on a circuit board, wherein the multilayer ceramic capacitor is connected to an internal electrode layer belonging to the first group on one end face of the multilayer ceramic capacitor. The first external terminal electrode is conductively connected to one of the pair of land electrodes on the circuit board and connected to the internal electrode layer belonging to the second group on the other end face of the capacitor. A capacitor-mounted circuit board, wherein the plurality of second external terminal electrodes are conductively connected together to the other land electrode of the pair of land electrodes on the circuit board.
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