JP2008294330A - チップ内蔵基板 - Google Patents
チップ内蔵基板 Download PDFInfo
- Publication number
- JP2008294330A JP2008294330A JP2007140140A JP2007140140A JP2008294330A JP 2008294330 A JP2008294330 A JP 2008294330A JP 2007140140 A JP2007140140 A JP 2007140140A JP 2007140140 A JP2007140140 A JP 2007140140A JP 2008294330 A JP2008294330 A JP 2008294330A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- semiconductor chip
- built
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】半導体チップ110Aと、この半導体チップ110Aが搭載される第1の基板100と、この第1の基板100に積層される第2の基板200と、第1及び第2の基板100,200を電気的に接続する電極112と、第1及び第2の基板100,200間に配設される封止樹脂115とを有し、第2の基板200に開口部206を形成し、第1の基板100に第2の基板200が積層された際、半導体チップ110Aの少なくとも一部がこの開口部206内に位置するよう構成する。また、第1の基板100に半導体チップ110Aより形状の大きい内蔵部品を搭載し、該内蔵部品が前記開口部内で前記チップ部品の上部に位置するよう構成する。
【選択図】 図6
Description
チップ部品と、
第1の配線が形成されると共に前記チップ部品が搭載される第1の基板と、
第2の配線が形成されると共に前記第1の基板に積層される第2の基板と、
前記第1の基板と前記第2の基板を電気的に接続する接続部材と
前記第1の基板と前記第2の基板の間に配設される封止樹脂とを有し、
前記第2の基板に開口部を形成したチップ内蔵基板であって、
前記第1の基板に前記チップ部品より形状の大きい内蔵部品を搭載し、該内蔵部品の少なくとも一部が前記開口部内に位置し、かつ前記チップ部品の上部に位置するよう構成したチップ内蔵基板により解決することができる。
101 コア基板
102,202 ビアプラグ
103A,103B,203A,203B 配線パターン
103C,203C 内層配線
104A,104B,204A,204B ソルダーレジスト層
109 アンダーフィル
110A〜110C 半導体チップ
111,121 はんだボール
112 電極
113 銅コア
114 はんだ被膜
115 封止樹脂
120A 第1の半導体チップ
120B 第2の半導体チップ
125 ワイヤ
126 段差部
130 シリコンインターポーザ
140 ヒートシンク
141 熱伝導性接着シート
200,200A 第2の基板
201 コア基板
206 開口部
300A〜300G チップ内蔵基板
Claims (8)
- チップ部品と、
第1の配線が形成されると共に前記チップ部品が搭載される第1の基板と、
第2の配線が形成されると共に前記第1の基板に積層される第2の基板と、
前記第1の基板と前記第2の基板を電気的に接続する接続部材と
前記第1の基板と前記第2の基板の間に配設される封止樹脂とを有し、
前記第2の基板に開口部を形成したチップ内蔵基板であって、
前記第1の基板に前記チップ部品より形状の大きい内蔵部品を搭載し、該内蔵部品の少なくとも一部が前記開口部内に位置し、かつ前記チップ部品の上部に位置するよう構成したチップ内蔵基板。 - 前記内蔵部品の前記開口部内における背面と、前記第2の基板の表面とが面一となるよう構成した請求項1に記載のチップ内蔵基板。
- 前記封止樹脂の前記開口部内における表面と、前記第2の基板の表面とが面一となるよう構成した請求項1に記載のチップ内蔵基板。
- 前記内蔵部品の少なくとも一部が、前記開口部内に位置する構成とした請求項1に記載のチップ内蔵基板。
- 前記内蔵部品は前記第1の基板にフリップチップ接合されている請求項1乃至4のいずれか一項に記載のチップ内蔵基板。
- 前記チップ部品は、半導体チップである請求項1乃至5のいずれか一項に記載のチップ内蔵基板。
- 前記内蔵部品は、シリコン基板に配線が形成されたインターポーザ基板である請求項1乃至5のいずれか一項に記載のチップ内蔵基板。
- 前記内蔵部品は、ヒートシンクである請求項1乃至5のいずれか一項に記載のチップ内蔵基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007140140A JP5128180B2 (ja) | 2007-05-28 | 2007-05-28 | チップ内蔵基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007140140A JP5128180B2 (ja) | 2007-05-28 | 2007-05-28 | チップ内蔵基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008294330A true JP2008294330A (ja) | 2008-12-04 |
JP5128180B2 JP5128180B2 (ja) | 2013-01-23 |
Family
ID=40168721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007140140A Active JP5128180B2 (ja) | 2007-05-28 | 2007-05-28 | チップ内蔵基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5128180B2 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010147153A (ja) * | 2008-12-17 | 2010-07-01 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2010157656A (ja) * | 2009-01-05 | 2010-07-15 | Hitachi Metals Ltd | 半導体装置およびその製造方法 |
JP2016511552A (ja) * | 2013-03-15 | 2016-04-14 | クアルコム,インコーポレイテッド | 低減された高さのパッケージオンパッケージ構造 |
JP2017503361A (ja) * | 2014-12-16 | 2017-01-26 | インテル コーポレイション | スタック型電子装置を含む電子アセンブリ |
CN115884526A (zh) * | 2022-09-06 | 2023-03-31 | 珠海越亚半导体股份有限公司 | 一种高散热混合基板制作方法及半导体结构 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101965039B1 (ko) * | 2014-04-30 | 2019-04-02 | 인텔 코포레이션 | 성형 화합물을 갖는 집적 회로 어셈블리 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60227492A (ja) * | 1984-04-25 | 1985-11-12 | 松下電工株式会社 | 電子回路ブロツク |
JPH0587982U (ja) * | 1992-04-30 | 1993-11-26 | 太陽誘電株式会社 | 発熱部品を有する混成集積回路装置 |
JP2004247637A (ja) * | 2003-02-17 | 2004-09-02 | Nec Saitama Ltd | 電子部品の三次元実装構造および方法 |
JP2004304159A (ja) * | 2003-03-19 | 2004-10-28 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
-
2007
- 2007-05-28 JP JP2007140140A patent/JP5128180B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60227492A (ja) * | 1984-04-25 | 1985-11-12 | 松下電工株式会社 | 電子回路ブロツク |
JPH0587982U (ja) * | 1992-04-30 | 1993-11-26 | 太陽誘電株式会社 | 発熱部品を有する混成集積回路装置 |
JP2004247637A (ja) * | 2003-02-17 | 2004-09-02 | Nec Saitama Ltd | 電子部品の三次元実装構造および方法 |
JP2004304159A (ja) * | 2003-03-19 | 2004-10-28 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010147153A (ja) * | 2008-12-17 | 2010-07-01 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2010157656A (ja) * | 2009-01-05 | 2010-07-15 | Hitachi Metals Ltd | 半導体装置およびその製造方法 |
JP2016511552A (ja) * | 2013-03-15 | 2016-04-14 | クアルコム,インコーポレイテッド | 低減された高さのパッケージオンパッケージ構造 |
JP2017503361A (ja) * | 2014-12-16 | 2017-01-26 | インテル コーポレイション | スタック型電子装置を含む電子アセンブリ |
US9633937B2 (en) | 2014-12-16 | 2017-04-25 | Intel Corporation | Electronic assembly that includes stacked electronic devices |
CN115884526A (zh) * | 2022-09-06 | 2023-03-31 | 珠海越亚半导体股份有限公司 | 一种高散热混合基板制作方法及半导体结构 |
CN115884526B (zh) * | 2022-09-06 | 2023-09-15 | 珠海越亚半导体股份有限公司 | 一种高散热混合基板制作方法及半导体结构 |
Also Published As
Publication number | Publication date |
---|---|
JP5128180B2 (ja) | 2013-01-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5324051B2 (ja) | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 | |
US10177130B2 (en) | Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener | |
TWI508196B (zh) | 具有內建加強層之凹穴基板之製造方法 | |
KR101376265B1 (ko) | 배선 기판 및 그 제조 방법 | |
US9947625B2 (en) | Wiring board with embedded component and integrated stiffener and method of making the same | |
US9338886B2 (en) | Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device | |
TWI495026B (zh) | 晶片封裝基板和結構及其製作方法 | |
US7678681B2 (en) | Electronic component built-in substrate and method of manufacturing the same | |
US9754870B2 (en) | Compound carrier board structure of flip-chip chip-scale package and manufacturing method thereof | |
JP2017108019A (ja) | 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法 | |
JP2004022730A (ja) | 半導体装置及びその製造方法 | |
JP2008218979A (ja) | 電子パッケージ及びその製造方法 | |
JP2015041773A (ja) | インターポーザ基板およびその製造方法 | |
CN107154388B (zh) | 半导体封装件及其制造方法 | |
JP5054440B2 (ja) | 電子部品内蔵基板の製造方法及び電子部品内蔵基板 | |
TW201524283A (zh) | 印刷電路板及其製造方法與使用其之半導體封裝件 | |
JP5128180B2 (ja) | チップ内蔵基板 | |
TW201325343A (zh) | 用於嵌入式晶粒封裝的高精密度自我對準晶粒 | |
US20180359886A1 (en) | Methods of making interconnect substrate having stress modulator and crack inhibiting layer and making flip chip assembly thereof | |
US20120048914A1 (en) | Wiring substrate manufacturing method | |
JP2006228897A (ja) | 半導体装置 | |
TW201413842A (zh) | 層疊封裝結構及其製作方法 | |
KR20100002870A (ko) | 반도체 패키지의 제조 방법 | |
US8125074B2 (en) | Laminated substrate for an integrated circuit BGA package and printed circuit boards | |
JP2007115789A (ja) | 積層型半導体装置および積層型半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100205 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110908 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110920 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111116 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120522 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120810 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20120821 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121023 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121031 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 5128180 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151109 Year of fee payment: 3 |