JP2008288607A - Method for manufacturing electronic parts packaging structure - Google Patents

Method for manufacturing electronic parts packaging structure Download PDF

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Publication number
JP2008288607A
JP2008288607A JP2008175380A JP2008175380A JP2008288607A JP 2008288607 A JP2008288607 A JP 2008288607A JP 2008175380 A JP2008175380 A JP 2008175380A JP 2008175380 A JP2008175380 A JP 2008175380A JP 2008288607 A JP2008288607 A JP 2008288607A
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film
electronic component
pad
connection pad
insulating film
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Masahiro Haruhara
昌宏 春原
Hiroshi Murayama
啓 村山
Naohiro Mashino
直寛 真篠
Mitsutoshi Azuma
光敏 東
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing an electronic parts packaging structure, in which face-up mounted electronic parts are embedded in an insulating film on a wiring substrate, capable of forming via holes on connection pads of the electronic parts without occurrence of faults. <P>SOLUTION: The method includes a step of preparing an electronic part 20 having connection pads 18 composed of aluminum pads 12 and etching stop layers 16 formed thereon, a step of mounting the electronic part 20 on a mounting target body 24 to direct the connection pads 18 upward, a step of forming an insulating film 28a covering the electronic part 20, a step of forming via holes 28y by etching the insulating film 28a on the connection pads 18 by laser, and a step of forming a wiring pattern 26b connected to the connection pads 18 through the via holes 28y. The etching stop layers 16 are formed on the connection pads selectively by nonelectrolytic plating. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は電子部品実装構造の製造方法に係り、より詳しくは、電子部品が絶縁膜に埋設された状態で配線基板上に実装される電子部品実装構造の製造方法に関する。   The present invention relates to a method for manufacturing an electronic component mounting structure, and more particularly to a method for manufacturing an electronic component mounting structure in which an electronic component is mounted on a wiring board in a state of being embedded in an insulating film.

マルチメディア機器を実現するためのキーテクノロジーであるＬＳＩ技術はデータ伝送の高速化、大容量化に向かって着実に開発が進んでいる。これに伴って、ＬＳＩと電子機器とのインターフェイスとなる実装技術の高密度化が進められている。   LSI technology, which is a key technology for realizing multimedia devices, is steadily being developed for higher data transmission speed and capacity. Along with this, the density of packaging technology that serves as an interface between LSI and electronic devices is being increased.

さらなる高密度化の要求から、配線基板上に半導体チップが絶縁膜に埋設された状態で実装された半導体装置がある。その一例として、特許文献１には、配線基板上に薄型化された半導体チップが絶縁膜に埋設された状態でフェイスアップで実装され、半導体チップの電極パッドがその上の絶縁膜に形成されたビアホールなどを介して、配線基板の両面に設けられた外部接続端子に接続された半導体装置が記載されている。
特開２００１−２１７３３７号公報 Due to the demand for higher density, there is a semiconductor device mounted on a wiring board in a state where a semiconductor chip is embedded in an insulating film. As an example, Patent Document 1 discloses that a semiconductor chip thinned on a wiring board is mounted face up in an embedded state in an insulating film, and an electrode pad of the semiconductor chip is formed on the insulating film thereon. A semiconductor device connected to external connection terminals provided on both surfaces of a wiring board through via holes or the like is described.
JP 2001-217337 A

ところで、上記したような半導体装置を製造するには、半導体チップの接続パッド上の絶縁膜をレーザなどによりエッチングしてビアホールを形成する必要がある。このとき、半導体チップの接続パッドがアルミニウム（Ａｌ）膜からなる場合、Ａｌ膜はレーザによりエッチングされやすい特性を有するため、レーザにより絶縁膜を穴明けする際に、露出したＡｌ膜がレーザによりエッチングされて周囲に飛散し、引いては接続パッドの一部が消失してしまうという不具合が発生しやすい。このため、レーザにより接続パッドの近傍下の回路素子にダメージを与えてしまうという問題がある。   Incidentally, in order to manufacture the semiconductor device as described above, it is necessary to form a via hole by etching the insulating film on the connection pad of the semiconductor chip with a laser or the like. At this time, when the connection pad of the semiconductor chip is made of an aluminum (Al) film, the Al film has a characteristic that it is easily etched by a laser. Therefore, when the insulating film is drilled by the laser, the exposed Al film is etched by the laser. In this case, it is likely that a problem occurs in that the connection pad is scattered and a part of the connection pad is lost. For this reason, there is a problem that the circuit element under the vicinity of the connection pad is damaged by the laser.

なお、上記した特許文献１では上記したような半導体チップの接続パッド（Ａｌ膜）上の絶縁膜をレーザによりエッチングする際の問題に関しては何ら考慮されていない。   In the above-mentioned Patent Document 1, no consideration is given to the problem in etching the insulating film on the connection pad (Al film) of the semiconductor chip as described above by laser.

本発明は以上の課題を鑑みて創作されたものであり、配線基板上に、電子部品が絶縁膜内に埋設され、かつフェイスアップで実装された電子部品実装構造の製造方法において、不具合が発生することなく、電子部品の接続パッド上にビアホールを形成できる電子部品実装構造の製造方法を提供することを目的とする。   The present invention was created in view of the above problems, and in the manufacturing method of an electronic component mounting structure in which an electronic component is embedded in an insulating film and mounted face-up on a wiring board, problems occur. It is an object of the present invention to provide a method for manufacturing an electronic component mounting structure that can form a via hole on a connection pad of the electronic component without doing so.

上記課題を解決するため、本発明は電子部品実装構造に係り、電子部品が実装される被実装体と、前記被実装体の上に、最上にエッチングストップ層を備えた積層膜から構成される接続パッドを有する前記電子部品の該接続パッドが上向きになって実装された前記電子部品と、前記電子部品を被覆する絶縁膜と、少なくとも前記電子部品の接続パッド上における前記絶縁膜の所定部に形成されたビアホールと、前記ビアホールを介して前記接続パッドに接続された配線パターンとを有することを特徴とする。   In order to solve the above-described problems, the present invention relates to an electronic component mounting structure, and includes a mounted body on which an electronic component is mounted, and a stacked film having an etching stop layer on top of the mounted body. The electronic component having the connection pad mounted with the connection pad facing upward, an insulating film covering the electronic component, and at least a predetermined portion of the insulating film on the connection pad of the electronic component It has a formed via hole and a wiring pattern connected to the connection pad through the via hole.

本発明の電子部品実装構造では、電子部品が、その接続パッドが上向きになって（フェイスアップ）、かつ絶縁膜内に埋設された状態で被実装体上に実装されている。そして、電子部品の接続パッドは、その最上にエッチングストップ層を備えた積層膜により構成されている。   In the electronic component mounting structure of the present invention, the electronic component is mounted on the mounted body with its connection pads facing upward (face-up) and embedded in the insulating film. And the connection pad of an electronic component is comprised by the laminated film provided with the etching stop layer on the top.

接続パッドの一つの好適な例としては、それぞれ下から順に、アルミニウム膜／ニッケル膜／銅膜、アルミニウム膜／ニッケル膜／金膜、アルミニウム膜／ニッケル膜／銅膜／金膜、アルミニウム膜／ニッケル膜／銀膜、アルミニウム膜／クロム膜／銅膜、及びアルミニウム膜／導電性ペースト膜、アルミニウム膜／チタン膜／導電性ペースト膜、アルミニウム膜／クロム膜／導電性ペースト膜、及びアルミニウム膜／チタン膜／銅膜の群から選択されるいずれかの積層膜により構成される。   As a suitable example of the connection pad, aluminum film / nickel film / copper film, aluminum film / nickel film / gold film, aluminum film / nickel film / copper film / gold film, aluminum film / nickel, respectively, in order from the bottom. Film / silver film, aluminum film / chromium film / copper film, and aluminum film / conductive paste film, aluminum film / titanium film / conductive paste film, aluminum film / chromium film / conductive paste film, and aluminum film / titanium It is composed of any laminated film selected from the group of film / copper film.

また、電子部品の接続パッド上の絶縁膜にはスルーホールが形成されていて、この絶縁膜上にはビアホールを介して接続パッドに接続された配線パターンが形成されている。   A through hole is formed in the insulating film on the connection pad of the electronic component, and a wiring pattern connected to the connection pad through the via hole is formed on the insulating film.

本発明の電子部品実装構造では、電子部品の接続パッド上の絶縁膜にレーザによりビアホールが形成される際に、接続パッドの最上膜がレーザプロセスでのエッチングストップ層として機能するようにしている。すなわち、エッチングストップ層としての銅膜、金膜、銀膜又は導電性ペースト膜などは、接続パッドの一般的な材料であるＡｌ膜よりレーザでのエッチングレートが極めて低い特性を有するからである。   In the electronic component mounting structure of the present invention, when a via hole is formed in the insulating film on the connection pad of the electronic component by a laser, the uppermost film of the connection pad functions as an etching stop layer in the laser process. That is, a copper film, a gold film, a silver film, or a conductive paste film as an etching stop layer has a characteristic that an etching rate with a laser is extremely lower than that of an Al film which is a general material of a connection pad.

従って、最上層がＡｌ膜からなる接続パッドを使用する場合と違って、ビアホール下の接続パッドが消失したり、接続パッドの近傍下の回路素子にダメージを与えたりする恐れがなくなる。   Therefore, unlike the case where the uppermost layer is a connection pad made of an Al film, there is no possibility that the connection pad under the via hole disappears or the circuit element near the connection pad is damaged.

このように、電子部品の接続パッド上の絶縁膜に形成されるビアホールは、一般的なレーザプロセスにより、何ら不具合が発生することなく容易に形成される。従って、電子部品が被実装体上にフェイスアップで絶縁膜内に埋設された状態で実装され、かつ電子部品の接続パッドがビアホールを介して配線パターンに接続された電子部品実装構造がコスト上昇を招くことなく、かつ歩留りが高い状態で容易に製造される。   As described above, the via hole formed in the insulating film on the connection pad of the electronic component is easily formed without any problem by a general laser process. Therefore, the electronic component mounting structure in which the electronic component is mounted in a state where it is embedded in the insulating film face-up on the mounted body, and the connection pad of the electronic component is connected to the wiring pattern through the via hole increases the cost. It is easily manufactured without incurring and with a high yield.

以下、本発明の実施の形態について、添付の図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

最初に、半導体チップが絶縁膜に埋設されて実装された半導体装置の製造における不具合な点について説明する。図１は半導体チップが絶縁膜に埋設されて実装された半導体装置の製造における不具合な点を示す断面図である。   First, problems in manufacturing a semiconductor device in which a semiconductor chip is embedded and mounted in an insulating film will be described. FIG. 1 is a cross-sectional view showing problems in manufacturing a semiconductor device in which a semiconductor chip is embedded and mounted in an insulating film.

図１（ａ）に示すように、まず、所定の配線パターン（不図示）を備えたベース基板１００上に第１層間絶縁膜１０２が形成され、第１層間絶縁膜１０２に形成されたビアホール（不図示）を介して、ベース基板１００の配線パターンに接続されたＣｕ配線１０４が形成される。このＣｕ配線１０４上には接着層１０６を介してＡｌパッド１０８ａを備えた半導体チップ１０８がその接続端子１０８ａが上側になった状態（フェイスアップ）で固着される。   As shown in FIG. 1A, first, a first interlayer insulating film 102 is formed on a base substrate 100 having a predetermined wiring pattern (not shown), and a via hole formed in the first interlayer insulating film 102 ( Cu wirings 104 connected to the wiring pattern of the base substrate 100 are formed through (not shown). On this Cu wiring 104, the semiconductor chip 108 provided with the Al pad 108a is fixed via the adhesive layer 106 with the connection terminal 108a on the upper side (face up).

続いて、図１（ｂ）に示すように、半導体チップ１０８及びＣｕ配線１０４上に第２層間絶縁膜１１０が形成される。その後に、半導体チップ１０８のＡｌパッド１０８ａ上の第２層間絶縁膜１１０の所定部がレーザによりエッチングされてビアホール１１０ａが形成される。   Subsequently, as shown in FIG. 1B, a second interlayer insulating film 110 is formed on the semiconductor chip 108 and the Cu wiring 104. Thereafter, a predetermined portion of the second interlayer insulating film 110 on the Al pad 108a of the semiconductor chip 108 is etched by a laser to form a via hole 110a.

このとき、第２層間絶縁膜１１０のエッチングを終えてオーバーエッチングを行なう際、半導体チップ１０８のＡｌパッド１０８ａはレーザによりエッチングされやすい特性を有するため、Ａｌパッド１０８のＡｌがビアホール１１０の周囲に飛び散り、引いてはビアホール１１０ａの底部のＡｌが消失してしまうことがある。   At this time, when the etching of the second interlayer insulating film 110 is finished and overetching is performed, the Al pad 108a of the semiconductor chip 108 has a characteristic that it is easily etched by the laser, so that Al of the Al pad 108 is scattered around the via hole 110. If pulled, Al at the bottom of the via hole 110a may disappear.

さらには、Ａｌパッド１０８がレーザによりやられてしまうことに伴って、Ａｌパッド１０８の近傍の下側に形成された回路素子にダメージを与えてしまう。これは、半導体装置のチップ歩留りを低下させる要因になる。   Further, as the Al pad 108 is burned by the laser, the circuit element formed on the lower side in the vicinity of the Al pad 108 is damaged. This becomes a factor of reducing the chip yield of the semiconductor device.

本発明の実施形態の電子部品実装構造は上記した課題を解決することができる。   The electronic component mounting structure according to the embodiment of the present invention can solve the above-described problems.

（第１の実施の形態）
次に、本発明の第１実施形態の電子部品実装構造の製造方法を説明する。図２〜図５は本発明の第１実施形態の電子部品実装構造の製造方法を示す部分断面図、図６〜図８は同じく電子部品実装構造に係る接続パッドの変形例を示す部分断面図である。 (First embodiment)
Next, the manufacturing method of the electronic component mounting structure according to the first embodiment of the present invention will be described. 2 to 5 are partial cross-sectional views illustrating a method of manufacturing the electronic component mounting structure according to the first embodiment of the present invention, and FIGS. 6 to 8 are partial cross-sectional views illustrating modifications of the connection pads according to the electronic component mounting structure. It is.

図２（ａ）に示すように、まず、所定のトランジスタや多層配線（不図示）などが形成され、厚みが４００μｍ程度のシリコンウェハ１０（半導体ウェハ）を用意する。このシリコンウェハ１０の上面にはアルミニウム（Ａｌ）又はＡｌ合金からなるＡｌパッド１２が露出していて、Ａｌパッド１２以外の部分はシリコン窒化膜やポリイミド樹脂などからなるパシベーション膜１１で被覆されている。   As shown in FIG. 2A, first, a silicon wafer 10 (semiconductor wafer) having a predetermined transistor, multilayer wiring (not shown) and the like and having a thickness of about 400 μm is prepared. An Al pad 12 made of aluminum (Al) or an Al alloy is exposed on the upper surface of the silicon wafer 10, and a portion other than the Al pad 12 is covered with a passivation film 11 made of a silicon nitride film or a polyimide resin. .

その後、図２（ｂ）に示すように、シリコンウェハ１０のＡｌパッド１２上に無電解めっきによりニッケル（Ｎｉ）膜１４を形成する。その形成方法の一例について詳しく説明すると、まず、シリコンウェハ１０を、酸性浸漬脱脂材を含む前処理液（１）で処理して脱脂した後、過硫酸アンモニウム液又は過酸化水素水と硫酸との混合液などの前処理液（２）でソフトエッチングする。   Thereafter, as shown in FIG. 2B, a nickel (Ni) film 14 is formed on the Al pad 12 of the silicon wafer 10 by electroless plating. An example of the forming method will be described in detail. First, the silicon wafer 10 is treated with a pretreatment liquid (1) containing an acidic immersion degreasing material, degreased, and then mixed with an ammonium persulfate solution or a hydrogen peroxide solution and sulfuric acid. Soft etching is performed with a pretreatment liquid (2) such as a liquid.

続いて、シリコンウェハ１０を塩酸又は希硫酸などの前処理液（３）で処理して酸洗浄した後、さらにパラジウム系の触媒付与材を含む前処理液（４）でアクチベータ処理する。   Subsequently, the silicon wafer 10 is treated with a pretreatment liquid (3) such as hydrochloric acid or dilute sulfuric acid and washed with an acid, and then further activated with a pretreatment liquid (4) containing a palladium-based catalyst imparting material.

このようにして、シリコンウェハ１０のＡｌパッド１２にＮｉ膜１４を無電解めっきするための前処理が施される。なお、Ａｌパッド１２は上記した前処理液（１）〜（４）に耐性をもっており、Ａｌパッド１２が前処理液でエッチングされて不具合が発生するようなことはない。   In this way, pretreatment for electroless plating of the Ni film 14 on the Al pad 12 of the silicon wafer 10 is performed. The Al pad 12 is resistant to the above-described pretreatment liquids (1) to (4), and the Al pad 12 is not etched by the pretreatment liquid so that a problem does not occur.

続いて、例えば、スルファミン酸ニッケル（４００ｇ／リットル）、ニッケル（１００ｇ／リットル）、臭化ニッケル（１５ｇ／リットル）、ホウ酸（４０ｇ／リットル）の組成のめっき液（温度：６０℃程度）に、シリコンウェハ１０を浸漬させることにより、シリコンウェハ１０のＡｌパッド１２上に膜厚が１〜３μｍ程度のＮｉ膜１４を選択的に成膜する。   Subsequently, for example, a plating solution (temperature: about 60 ° C.) having a composition of nickel sulfamate (400 g / liter), nickel (100 g / liter), nickel bromide (15 g / liter), boric acid (40 g / liter). By immersing the silicon wafer 10, the Ni film 14 having a film thickness of about 1 to 3 μm is selectively formed on the Al pad 12 of the silicon wafer 10.

次いで、同じく図２（ｂ）に示すように、シリコンウェハ１０のＮｉ膜１４上に無電解めっきにより銅（Ｃｕ）膜１６を形成する。その形成方法の一例について詳しく説明すると、まず、シリコンウェハ１０を、界面活性材を含む前処理液（１）でコンディショニング処理した後、過硫酸アンモニウム又は過酸化水素水と硫酸との混合液などの前処理液（２）でソフトエッチングする。   Next, as shown in FIG. 2B, a copper (Cu) film 16 is formed on the Ni film 14 of the silicon wafer 10 by electroless plating. An example of the forming method will be described in detail. First, the silicon wafer 10 is conditioned with a pretreatment liquid (1) containing a surface active material, and then pretreated with ammonium persulfate or a mixed liquid of hydrogen peroxide and sulfuric acid. Soft etching is performed with the treatment liquid (2).

続いて、シリコンウェハ１０を塩酸又は希硫酸などの前処理液（３）で酸洗浄した後、パラジウムコロイド液を含む前処理液（４）でアクチベータ処理する。その後に、シリコンウェハ１０を塩酸又は希硫酸などの前処理液（５）でアクセラレータ処理する。   Subsequently, the silicon wafer 10 is acid cleaned with a pretreatment liquid (3) such as hydrochloric acid or dilute sulfuric acid, and then activated with a pretreatment liquid (4) containing a palladium colloid liquid. Thereafter, the silicon wafer 10 is accelerated by a pretreatment liquid (5) such as hydrochloric acid or dilute sulfuric acid.

このようにして、シリコンウェハ１０のＮｉ膜１４にＣｕ膜を無電解めっきするための前処理が施される。なお、Ｎｉ膜１４は上記した前処理液（１）〜（５）に耐性をもっており、Ｎｉ膜１４が前処理液でエッチングされて不具合が発生するようなことはない。   In this way, pretreatment for electroless plating of the Cu film on the Ni film 14 of the silicon wafer 10 is performed. Note that the Ni film 14 is resistant to the pretreatment liquids (1) to (5) described above, and the Ni film 14 is not etched by the pretreatment liquid so that a problem does not occur.

次いで、同じく図２（ｂ）に示すように、例えば、硫酸銅、水酸化ナトリウム、ホルムアルデヒド、ロッシェル塩及び界面活性剤を含むめっき液（温度：４５℃程度）にシリコンウェハ１０を浸漬することにより、Ｎｉ膜１４上に膜厚が１〜５μｍ程度のＣｕ膜１６を選択的に成膜する。   Next, as shown in FIG. 2B, for example, the silicon wafer 10 is immersed in a plating solution (temperature: about 45 ° C.) containing copper sulfate, sodium hydroxide, formaldehyde, Rochelle salt and a surfactant. Then, a Cu film 16 having a thickness of about 1 to 5 μm is selectively formed on the Ni film 14.

これにより、Ａｌパッド１２上にＮｉ膜１４及びＣｕ膜１６が選択的に形成されて接続パッド１８が得られる。接続パッド１８の最上層のＣｕ膜１６は、Ａｌパッド１２上に形成される層間絶縁膜にレーザによりビアホールを形成する際のエッチングストップ層として機能する。Ｃｕ膜はＡｌ膜に比べてレーザによるエッチングレートが著しく低い特性を有するからである。   As a result, the Ni film 14 and the Cu film 16 are selectively formed on the Al pad 12 to obtain the connection pad 18. The uppermost Cu film 16 of the connection pad 18 functions as an etching stop layer when a via hole is formed by laser in an interlayer insulating film formed on the Al pad 12. This is because the Cu film has a characteristic that the etching rate by laser is remarkably lower than that of the Al film.

なお、Ａｌパッド１２上にＮｉ膜１４を介さないでＣｕ膜１６を直接成膜する方法もあるが、Ａｌパッド１２が露出した状態でＣｕ膜１６の無電解めっきにおける上記した一連の前処理を行なうとＡｌパッド１２が腐食する恐れがあるため好ましくない。   Although there is a method of directly forming the Cu film 16 on the Al pad 12 without the Ni film 14, the above-described series of pretreatments in the electroless plating of the Cu film 16 with the Al pad 12 exposed is performed. This is not preferable because the Al pad 12 may corrode.

上記した形態では、接続パッド１８として、最上層にレーザでのエッチングレートが低いＣｕ膜１６が形成されたものを例示したが、レーザでのエッチングレートが低い金属としてＣｕ膜の他に金（Ａｕ）膜又は銀（Ａｇ）膜などが挙げられる。   In the above-described embodiment, the connection pad 18 is exemplified by a Cu film 16 having a low etching rate with a laser formed on the uppermost layer. However, as a metal with a low etching rate with a laser, gold (Au ) Film or silver (Ag) film.

従って、接続パッド１８の構造を以下のような構造としてもよい。すなわち、接続パッド１８の変形例１としては、図６に示すように、下から順に、Ａｌパッド１２、膜厚が１〜３μｍ程度のＮｉ膜１４、及び膜厚が０．０５〜０．１５μｍの金（Ａｕ）膜１７から構成されるようにしてもよい。この場合、例えば、金（１０ｇ／リットル）、クエン酸や酢酸などの有機酸（１００ｇ／リットル）、ＫＯＨやＮａＯＨなどの水酸化物（５０ｇ／リットル）、コバルト又はニッケル（１００ｍｇ／リットル）を含むめっき液（温度：５０℃程度）にＮｉ膜１４が形成されたシリコンウェハ２０を浸漬することにより、Ｎｉ膜１４上にＡｕ膜１７を選択的に成膜する。   Therefore, the structure of the connection pad 18 may be as follows. That is, as Modification 1 of the connection pad 18, as shown in FIG. 6, the Al pad 12, the Ni film 14 having a thickness of about 1 to 3 μm, and the thickness of 0.05 to 0.15 μm are sequentially arranged from the bottom. The gold (Au) film 17 may be used. In this case, for example, gold (10 g / liter), organic acid such as citric acid or acetic acid (100 g / liter), hydroxide such as KOH or NaOH (50 g / liter), cobalt or nickel (100 mg / liter) are included. An Au film 17 is selectively formed on the Ni film 14 by immersing the silicon wafer 20 on which the Ni film 14 is formed in a plating solution (temperature: about 50 ° C.).

また、接続パッドの変形例２としては、図７に示すように、下から順に、Ａｌパッド１２、膜厚が１〜３μｍ程度のＮｉ膜１４、膜厚が１〜５μｍ程度のＣｕ膜及び膜厚が０．０５μｍ程度のＡｕ膜１７から構成されるものを使用してもよい。   As a modification 2 of the connection pad, as shown in FIG. 7, in order from the bottom, an Al pad 12, a Ni film 14 having a film thickness of about 1 to 3 μm, a Cu film and a film having a film thickness of about 1 to 5 μm. A film composed of an Au film 17 having a thickness of about 0.05 μm may be used.

さらに、変形例３としては、図８に示すように、下から順に、Ａｌパッド１２、膜厚が１〜３μｍ程度のＮｉ膜１４、膜厚が１〜５μｍ程度の銀（Ａｇ）膜１９から構成されるものを使用してもよい。Ａｇ膜１９は一般的な無電解めっきによりＮｉ膜１４上に選択的に成膜される。   Furthermore, as a third modification, as shown in FIG. 8, in order from the bottom, the Al pad 12, the Ni film 14 having a film thickness of about 1 to 3 μm, and the silver (Ag) film 19 having a film thickness of about 1 to 5 μm. What is configured may be used. The Ag film 19 is selectively formed on the Ni film 14 by general electroless plating.

このようにして、本実施形態に係る接続パッド１８では、その最上にレーザでのエッチングレートがＡｌ膜より低い金属膜（Ｃｕ膜１６、Ａｕ膜１７又はＡｇ膜１９など）が被覆された状態で形成される。しかも、本実施形態では、Ａｌパッド１２上に形成される金属膜はマスク工程を使用することなく無電解めっきにより選択的に形成される。なお、上記した積層構造の接続パッド１８の例以外の変形例も適用できることはもちろんである。   Thus, in the connection pad 18 according to the present embodiment, a metal film (Cu film 16, Au film 17 or Ag film 19 or the like) whose etching rate with a laser is lower than that of the Al film is coated on the top thereof. It is formed. Moreover, in the present embodiment, the metal film formed on the Al pad 12 is selectively formed by electroless plating without using a mask process. Of course, modifications other than the example of the connection pad 18 having the laminated structure described above can be applied.

次いで、図２（ｃ）に示すように、シリコンウェハ１０の素子不形成面（以下、背面という）をグラインダーにより研削することにより、４００μｍ程度の厚みのシリコンウェハ１０を１０〜１５０μｍ程度の厚みに薄型化する。   Next, as shown in FIG. 2C, the element non-formation surface (hereinafter referred to as the back surface) of the silicon wafer 10 is ground by a grinder, so that the silicon wafer 10 having a thickness of about 400 μm is formed to a thickness of about 10 to 150 μm. Thinner.

続いて、図２（ｄ）に示すように、シリコンウェハ１０をダイシングすることにより、個片化された複数の半導体チップ２０（電子部品）を得る。なお、電子部品として半導体チップ２０を例示したが、シリコンチップの一方の面にコンデンサ素子や抵抗を備えたものなどの各種電子部品を用いてもよい。   Subsequently, as shown in FIG. 2D, the silicon wafer 10 is diced to obtain a plurality of individual semiconductor chips 20 (electronic components). In addition, although the semiconductor chip 20 was illustrated as an electronic component, you may use various electronic components, such as a thing provided with the capacitor | condenser element and resistance on one side of the silicon chip.

次に、上記した半導体チップ１１が実装される配線基板の一例について説明する。図３（ａ）に示すように、まず、ビルドアップ配線基板を製造するためのベース基板２４を用意する。このベース基板２４は樹脂などの絶縁性材料から構成されている。またベース基板２４にはスルーホール２４ａが設けられていて、このスルーホール２４ａにはその内面にベース基板２４上の第１配線パターン２６に繋がるスルーホールめっき層２４ｂが形成され、その孔は樹脂体２４ｃで埋め込まれている。   Next, an example of a wiring board on which the semiconductor chip 11 described above is mounted will be described. As shown in FIG. 3A, first, a base substrate 24 for manufacturing a build-up wiring substrate is prepared. The base substrate 24 is made of an insulating material such as resin. The base substrate 24 is provided with a through hole 24a. A through hole plating layer 24b connected to the first wiring pattern 26 on the base substrate 24 is formed on the inner surface of the through hole 24a. 24c is embedded.

その後、第１配線パターン２６を被覆する第１層間絶縁膜２８を形成する。第１層間絶縁膜２８としては、エポキシ系、ポリイミド系又はポリフェニレンエーテル系などの樹脂フィルムを使用することができる。例えば、第１配線パターン２６上にこれらの樹脂フィルムをラミネートした後、８０〜１００℃で熱処理して硬化させることにより、膜厚が３０〜５０μｍ程度の樹脂層を形成する。   Thereafter, a first interlayer insulating film 28 that covers the first wiring pattern 26 is formed. As the first interlayer insulating film 28, a resin film such as epoxy, polyimide, or polyphenylene ether can be used. For example, after laminating these resin films on the first wiring pattern 26, heat treatment is performed at 80 to 100 ° C. to cure, thereby forming a resin layer having a thickness of about 30 to 50 μm.

なお、第１層間絶縁膜２８としての樹脂膜は、上記した樹脂フィルムをラミネートする方法の他に、樹脂膜をスピンコート法又は印刷により形成するようにしてもよい。また、第１層間絶縁膜２８として樹脂膜の他に、ＣＶＤ法により形成されたシリコン酸化膜などを使用してもよい。   The resin film as the first interlayer insulating film 28 may be formed by spin coating or printing in addition to the method of laminating the resin film described above. In addition to the resin film, the first interlayer insulating film 28 may be a silicon oxide film formed by a CVD method.

次いで、第１配線パターン２６上の第１層間絶縁膜２８の所定部に第１ビアホール２８ｘを形成する。   Next, a first via hole 28 x is formed in a predetermined portion of the first interlayer insulating film 28 on the first wiring pattern 26.

続いて、第１層間絶縁膜２８上にセミアディティブ法により第２配線パターン２６ａを形成する。詳しく説明すると、第１ビアホール２８ｘの内面及び第１層間絶縁膜２８上に無電解めっきによりシードＣｕ層（不図示）を形成した後、所定パターンの開口部を有するレジスト膜（不図示）を形成する。次いで、シードＣｕ膜をめっき給電層に用いた電解めっきによりレジスト膜の開口部にＣｕ膜を形成する。続いて、レジスト膜を除去した後に、Ｃｕ膜をマスクにしてシードＣｕ膜をエッチングする。これにより第１配線パターン２６に第１ビアホール２８ｘを介して接続された第２配線パターン２６ａが形成される。   Subsequently, a second wiring pattern 26a is formed on the first interlayer insulating film 28 by a semi-additive method. More specifically, after a seed Cu layer (not shown) is formed on the inner surface of the first via hole 28x and the first interlayer insulating film 28 by electroless plating, a resist film (not shown) having openings of a predetermined pattern is formed. To do. Next, a Cu film is formed in the opening of the resist film by electrolytic plating using the seed Cu film as a plating power feeding layer. Subsequently, after removing the resist film, the seed Cu film is etched using the Cu film as a mask. As a result, the second wiring pattern 26a connected to the first wiring pattern 26 through the first via hole 28x is formed.

なお、セミアディティブ法の代わりに、サブトラクティブ法又はフルアディティブ法により第２配線パターン２６ａを形成してもよい。   Note that the second wiring pattern 26a may be formed by a subtractive method or a full additive method instead of the semi-additive method.

続いて、図３（ｂ）に示すように、前述した半導体チップ２０の背面を第２配線パターン２６ａ上に接着層２７を介して固着する。これにより、半導体チップ２０は、その接続パッド１８が上面になった状態（フェイスアップ）で実装される。   Subsequently, as illustrated in FIG. 3B, the back surface of the semiconductor chip 20 described above is fixed onto the second wiring pattern 26 a via the adhesive layer 27. As a result, the semiconductor chip 20 is mounted with the connection pads 18 on the upper surface (face-up).

次いで、図３（ｃ）に示すように、半導体チップ２０及び第２配線パターン２６ａ上に前述した第１層間絶縁膜２８と同様な樹脂層などからなる第２層間絶縁膜２８ａを形成する。続いて、半導体チップ２０の接続パッド１８上の第２層間絶縁膜２８ａの所定部をレーザによりエッチングして第２ビアホール２８ｙを形成する。この工程では、第２配線パターン２６ａ上の第２層間絶縁膜２８ａの所定部もレーザによりエッチングされて第２ビアホール２８ｙが形成される。   Next, as shown in FIG. 3C, a second interlayer insulating film 28a made of the same resin layer as the first interlayer insulating film 28 described above is formed on the semiconductor chip 20 and the second wiring pattern 26a. Subsequently, a predetermined portion of the second interlayer insulating film 28a on the connection pad 18 of the semiconductor chip 20 is etched with a laser to form a second via hole 28y. In this step, a predetermined portion of the second interlayer insulating film 28a on the second wiring pattern 26a is also etched by the laser to form the second via hole 28y.

このとき、第２層間絶縁膜２８ａをレーザでエッチングした後のオーバーエッチング時に、接続パッド１８の最上層がレーザに曝される。しかしながら、接続パッド１８の最上層はレーザによるエッチンレートが低いＣｕ膜１６であるため、Ｃｕ膜１６がエッチングストップ層として機能する。従って、接続パッドがＡｌ膜からなる場合と違って、接続パッド１８からその周囲にＡｌが飛び散ったり、接続パッド１８の近傍下の回路素子にダメージが入ったりすることが回避される。なお、接続パッド１８の最上層がＡｕ膜１７やＡｇ膜１９などからなる場合（図６〜図８）も同様な効果を奏する。   At this time, the uppermost layer of the connection pad 18 is exposed to the laser during over-etching after etching the second interlayer insulating film 28a with the laser. However, since the uppermost layer of the connection pad 18 is the Cu film 16 having a low etch rate by laser, the Cu film 16 functions as an etching stop layer. Therefore, unlike the case where the connection pad is made of an Al film, it is possible to prevent Al from splashing around the connection pad 18 and damage to the circuit elements near the connection pad 18. The same effect can be obtained when the uppermost layer of the connection pad 18 is made of the Au film 17 or the Ag film 19 (FIGS. 6 to 8).

レーザとしては、ＣＯ2レーザ（波長：１０．６４ｎｍ）、ＹＡＧレーザ（第３高周波（波長：０．３５５ｎｍ））、又は、ＫｒＦエキシマレーザ（波長：０．２４８ｎｍ）などが使用される。 As the laser, a CO 2 laser (wavelength: 10.64 nm), a YAG laser (third high frequency (wavelength: 0.355 nm)), a KrF excimer laser (wavelength: 0.248 nm), or the like is used.

接続パッド１８の最上層がＣｕ膜１６からなる場合、Ｃｕ膜１８のエッチングレートが他のレーザより低いＣＯ2レーザを使用することが好ましい。また、接続パッド１８の最上層がＡｇ膜１９からなる場合、Ａｇ膜１９のエッチングレートが他のレーザより低いＹＡＧレーザを使用することが好ましい。 When the uppermost layer of the connection pad 18 is made of the Cu film 16, it is preferable to use a CO 2 laser whose etching rate of the Cu film 18 is lower than that of other lasers. Further, when the uppermost layer of the connection pad 18 is made of an Ag film 19, it is preferable to use a YAG laser whose etching rate of the Ag film 19 is lower than that of other lasers.

また、エッチングストップ層（Ｃｕ膜１６など）は、熱伝導性を大きしてレーザ照射時の発熱を抑えるために、その膜厚ができるだけ厚く、しかもそのパッド面積ができるだけ大きくなるように設定されることが好ましい。このような観点からの好適な一例としては、Ｃｕ膜１６の膜厚が３μｍ程度以上、接続パッド１８のパッド面積が８０μｍ□〜１００μｍ□程度、第２ビアホール２８ｙの口径が５０〜６０μｍ程度に設定される。   In addition, the etching stop layer (Cu film 16 or the like) is set so that its film thickness is as large as possible and its pad area is as large as possible in order to increase thermal conductivity and suppress heat generation during laser irradiation. It is preferable. As a suitable example from such a viewpoint, the film thickness of the Cu film 16 is set to about 3 μm or more, the pad area of the connection pad 18 is set to about 80 μm □ to 100 μm □, and the diameter of the second via hole 28y is set to about 50 to 60 μm. Is done.

なお、レーザの代わりに、ＲＩＥ（Reactive Ion Etching）を用いてビアホールを形成する場合においても、上記した構成の接続パッド１８を使用することにより、Ａｌパッドを使用する場合と比較してオーバーエッチング時に接続パッド１８の材料のスパッタリングが抑制されるため都合がよい。   Even when the via hole is formed by using RIE (Reactive Ion Etching) instead of the laser, the connection pad 18 having the above-described configuration is used during over-etching compared to the case of using the Al pad. This is convenient because sputtering of the material of the connection pad 18 is suppressed.

次いで、図４（ａ）に示すように、半導体チップ２０の接続パッド１８が露出した構造体（図３（ｃ））上に、無電解めっきによりシードＣｕ膜３０ａを形成する。このとき、接続パッド１８がＡｌ膜のみからなる場合、接続パッド１８とシードＣｕ膜３０ａとの密着性において不具合が発生する恐れがある。しかしながら、本実施形態では、シードＣｕ膜３０ａは接続パッド１８の最上層のエッチングストップ層（図４（ａ）の例ではＣｕ膜１６）上に成膜されるため、接続パッド１８とシードＣｕ膜３０ａとの密着性を向上させることができる。   Next, as shown in FIG. 4A, a seed Cu film 30a is formed by electroless plating on the structure (FIG. 3C) where the connection pads 18 of the semiconductor chip 20 are exposed. At this time, when the connection pad 18 is made of only an Al film, there is a possibility that a problem may occur in the adhesion between the connection pad 18 and the seed Cu film 30a. However, in this embodiment, since the seed Cu film 30a is formed on the uppermost etching stop layer (Cu film 16 in the example of FIG. 4A) of the connection pad 18, the connection pad 18 and the seed Cu film are formed. Adhesiveness with 30a can be improved.

その後、図４（ｂ）に示すように、第３配線パターンに対応する開口部３２ａを有するレジスト膜３２をシードＣｕ膜３０ａ上にフォトリソグラフィにより形成する。続いて、シードＣｕ膜３０ａをめっき給電層に利用した電解めっきにより、レジスト膜３２の開口部３２にＣｕ膜パターン３０ｂを形成する。   Thereafter, as shown in FIG. 4B, a resist film 32 having an opening 32a corresponding to the third wiring pattern is formed on the seed Cu film 30a by photolithography. Subsequently, a Cu film pattern 30b is formed in the opening 32 of the resist film 32 by electrolytic plating using the seed Cu film 30a as a plating power feeding layer.

次いで、図４（ｃ）に示すように、レジスト膜３２を除去した後に、Ｃｕ膜パターン３０ｂをマスクにしてシードＣｕ膜３０ａをウェットエッチングすることにより、第３配線パターン２６ｂとする。なお、この工程の後に、図３（ｂ）〜図４（ｃ）までの工程を所定回繰り返すことにより、半導体チップ２０を内蔵した層間絶縁膜及び配線パターンを多層化して形成するようにしてもよい。   Next, as shown in FIG. 4C, after removing the resist film 32, the seed Cu film 30a is wet-etched using the Cu film pattern 30b as a mask to form a third wiring pattern 26b. After this step, the steps from FIG. 3B to FIG. 4C are repeated a predetermined number of times so that the interlayer insulating film and the wiring pattern containing the semiconductor chip 20 are formed in multiple layers. Good.

次いで、図５に示すように、第３配線パターン２６ｂ上にその接続部２６ｘに開口部３４ａを有するソルダレジスト膜３４を形成する。続いて、バンプ３６を備えた半導体チップ２０ａを用意し、第３配線パターン２６ｂの接続部２６ｘに半導体チップ２０ａのバンプ３６をフリップチップ接合する。このとき、第３配線パターン２６ｂの接続部２６ｘにはＮｉ／Ａｕめっきが施されている。   Next, as shown in FIG. 5, a solder resist film 34 having an opening 34a in the connection portion 26x is formed on the third wiring pattern 26b. Subsequently, the semiconductor chip 20a provided with the bumps 36 is prepared, and the bumps 36 of the semiconductor chip 20a are flip-chip bonded to the connection portions 26x of the third wiring pattern 26b. At this time, Ni / Au plating is applied to the connection portion 26x of the third wiring pattern 26b.

なお、ソルダレジスト３４の開口部３４ａにはんだボールを搭載するなどしてバンプを形成し、半導体チップ２０ａの接続端子をこのバンプに接合するようにしてもよい。また、図５の構造体を所定数の半導体チップ２０を含むようにして分割する必要がある場合は、半導体チップ２０ａをフリップチップ実装する前又は後に分割するようにしてもよい。   Note that bumps may be formed by mounting solder balls in the openings 34a of the solder resist 34, and the connection terminals of the semiconductor chip 20a may be bonded to the bumps. In addition, when it is necessary to divide the structure of FIG. 5 so as to include a predetermined number of semiconductor chips 20, the semiconductor chip 20a may be divided before or after flip-chip mounting.

以上により、本実施形態の電子部品実装構造１が完成する。   Thus, the electronic component mounting structure 1 of the present embodiment is completed.

第１実施形態の電子部品実装構造１では、ベース基板２４上方の第２配線パターン２６ａ上に第２層間絶縁膜に２８ａに埋設された状態で半導体チップ２０がフェイスアップで実装されている。この半導体チップ２０の接続パッド１８は、その最上層にレーザでエッチングされにくい材料からなるエッチングストップ層（Ｃｕ膜１６など）を備えている。この半導体チップ２０の接続パッド１８上の第２層間絶縁膜２８ｂにはレーザで穴明けされた第２ビアホール２８ｙが形成されている。   In the electronic component mounting structure 1 of the first embodiment, the semiconductor chip 20 is mounted face up on the second wiring pattern 26a above the base substrate 24 in a state of being embedded in the second interlayer insulating film 28a. The connection pad 18 of the semiconductor chip 20 is provided with an etching stop layer (Cu film 16 or the like) made of a material that is difficult to be etched by a laser on the uppermost layer. The second interlayer insulating film 28b on the connection pad 18 of the semiconductor chip 20 is formed with a second via hole 28y drilled with a laser.

半導体チップ２０の接続パッド１８に接続された第３配線パターン２６ｂは、第２ビアホール２８ｙを介して第２配線パターン２６ａに電気的に接続されている。さらに、第３配線パターン２６ｂの接続部２６ｘに開口部３４ａを有するソルダレジスト膜３４が形成されており、半導体チップ２０ａのバンプ３６が第３配線パターン２６ｂの接続部２６ｘにフリップチップ実装されている。このようにして、半導体チップ２０は、その接続パッド１８が配線基板の所定の配線パターンに接続されていると共に、上側に配置された半導体チップ２０ａと相互接続されている。   The third wiring pattern 26b connected to the connection pad 18 of the semiconductor chip 20 is electrically connected to the second wiring pattern 26a through the second via hole 28y. Further, a solder resist film 34 having an opening 34a is formed at the connection portion 26x of the third wiring pattern 26b, and the bump 36 of the semiconductor chip 20a is flip-chip mounted on the connection portion 26x of the third wiring pattern 26b. . In this way, the semiconductor chip 20 has the connection pads 18 connected to the predetermined wiring pattern of the wiring board and is interconnected with the semiconductor chip 20a disposed on the upper side.

なお、本実施形態では、半導体チップ２０が、配線基板の第２配線パターン２６ａ上に第２層間絶縁膜２８ａに埋設された状態で実装された形態を例示したが、半導体チップ２０が第１配線パターン２６又は第３配線パターン２６ｂ上に同様にして層間絶縁膜に埋設されて実装された形態としてもよい。あるいは、半導体チップ２０がベース基板２４上、第１又は第２層間絶縁膜２８，２８ａ上に実装された形態としてもよい。つまり、半導体チップ２０が実装される被実装体としては、ベース基板２４、第１〜第３配線パターン２６〜２６ｂ、又は第１、第２層間絶縁膜２８，２８ａなどである。   In the present embodiment, the semiconductor chip 20 is illustrated as being mounted on the second wiring pattern 26a of the wiring board while being embedded in the second interlayer insulating film 28a. Similarly, the pattern 26 or the third wiring pattern 26b may be embedded in an interlayer insulating film and mounted. Alternatively, the semiconductor chip 20 may be mounted on the base substrate 24 and the first or second interlayer insulating films 28 and 28a. That is, the mounted body on which the semiconductor chip 20 is mounted is the base substrate 24, the first to third wiring patterns 26 to 26b, or the first and second interlayer insulating films 28 and 28a.

さらに、複数の半導体チップ２０が複数の層間絶縁膜にそれぞれ同様に埋設されて３次元的に多層化されて実装され、それらの半導体チップ２０が複数のビアホールを介して相互接続された形態としてもよい。   Further, a plurality of semiconductor chips 20 may be similarly embedded in a plurality of interlayer insulating films and mounted in a three-dimensional multilayer, and the semiconductor chips 20 may be interconnected via a plurality of via holes. Good.

本実施形態の電子部品実装構造１では、前述したように、半導体チップ２０の接続パッド１８がその最上層にレーザプロセスでのエッチングストップ層（Ｃｕ膜１６、Ａｕ膜１７又はＡｇ膜１９など）を備えているので、一般的なレーザビア形成方法で何ら不具合が発生することなく第２層間絶縁膜２８ａに第２ビアホール２８ｙが形成される。このため、レーザビア形成工程において、半導体チップ２０の接続パッド１８が消失したり、接続パッド１８の近傍下の回路素子にダメージを与えたりする恐れがなくなる。   In the electronic component mounting structure 1 of the present embodiment, as described above, the connection pad 18 of the semiconductor chip 20 has an etching stop layer (Cu film 16, Au film 17 or Ag film 19 or the like) in the laser process as the uppermost layer. Therefore, the second via hole 28y is formed in the second interlayer insulating film 28a without causing any trouble in a general laser via forming method. For this reason, in the laser via formation process, there is no possibility that the connection pad 18 of the semiconductor chip 20 disappears or the circuit element near the connection pad 18 is damaged.

以上のことから、電子部品実装構造１がコスト上昇を招くことなく、かつ歩留りが高い状態で容易に製造される。さらに、半導体チップ２０が内蔵された層間絶縁膜及び配線パターンを多層化して形成して高密度な電子部品実装構造を製造する場合も、高性能なものを信頼性が高い状態で製造することができるようになる。   From the above, the electronic component mounting structure 1 is easily manufactured without increasing the cost and in a high yield state. Furthermore, even when a high-density electronic component mounting structure is manufactured by forming an interlayer insulating film and a wiring pattern in which the semiconductor chip 20 is built in multiple layers, a high-performance one can be manufactured with high reliability. become able to.

（第２の実施の形態）
図９〜図１１は本発明の第２実施形態の電子部品実装構造の製造方法を示す部分断面図、図１２は同じく電子部品実装構造に係る接続パッドの形成方法の変形例１を示す部分断面図、図１３は同じく電子部品実装構造に係る接続パッドの形成方法の変形例２を示す部分断面図である。 (Second Embodiment)
9 to 11 are partial cross-sectional views illustrating a method for manufacturing an electronic component mounting structure according to a second embodiment of the present invention, and FIG. 12 is a partial cross-sectional view illustrating Modification 1 of the method for forming connection pads according to the electronic component mounting structure. FIGS. 13A and 13B are partial sectional views showing a second modification of the connection pad forming method according to the electronic component mounting structure.

第２実施形態が第１実施形態と異なる点は、Ａｌパッド１２上にエッチングストップ層を選択的に形成する方法として、無電解めっきを用いるのではなく、フォトリソグラフィを用いることにある。図９〜図１３において、図２〜図５と同一要素及び同一工程についてはその詳しい説明を省略する。   The second embodiment is different from the first embodiment in that photolithography is used instead of electroless plating as a method for selectively forming an etching stop layer on the Al pad 12. 9 to 13, detailed descriptions of the same elements and steps as those in FIGS. 2 to 5 are omitted.

本発明の第２実施形態の電子部品実装構造の製造方法は、まず、図９（ａ）に示すように、第１実施形態と同様な方法により、図２（ａ）と同様に、Ａｌパッド１２が露出し、それ以外の部分がパシベーション膜１１で被覆された構造を有するシリコンウェハ１０（半導体ウェハ）を用意する。   The manufacturing method of the electronic component mounting structure according to the second embodiment of the present invention, first, as shown in FIG. 9A, by the same method as in the first embodiment, the Al pad as in FIG. A silicon wafer 10 (semiconductor wafer) having a structure in which 12 is exposed and the other part is covered with a passivation film 11 is prepared.

その後、図９（ｂ）に示すように、Ａｌパッド１２及びパシベーション膜１１上にスパッタ法などにより膜厚が０．０５μｍ程度のクロム（Ｃｒ）膜１３を成膜する。なお、クロム（Ｃｒ）膜１３の代わりにチタン（Ｔｉ）膜を用いてもよい。続いて、Ｃｒ膜１３上にスパッタ法などにより膜厚が０．０５〜２μｍ程度のＣｕ膜１６ｘを成膜する。   Thereafter, as shown in FIG. 9B, a chromium (Cr) film 13 having a film thickness of about 0.05 μm is formed on the Al pad 12 and the passivation film 11 by sputtering or the like. Note that a titanium (Ti) film may be used instead of the chromium (Cr) film 13. Subsequently, a Cu film 16x having a thickness of about 0.05 to 2 μm is formed on the Cr film 13 by sputtering or the like.

次いで、図９（ｃ）に示すように、フォトリソグラフィにより、Ａｌパッド１２に対応する部分を被覆するようにパターニングされたレジスト膜１５をＣｕ膜１６ｘ上に形成する。その後、レジスト膜１５をマスクにして、臭化水素（ＨＢｒ）と過硫酸アンモニウムとを含む溶液（常温）を用いたウェットエッチングによりＣｕ膜１６ｘをエッチングする。続いて、同じくレジスト膜１５をマスクにして、三塩化鉄（ＦｅＣｌ3）と塩酸（ＨＣｌ）を含む溶液（４０℃）を用いたウェットエッチングによりＣｒ膜１３をエッチングする。その後に、レジスト膜１５を除去する。 Next, as shown in FIG. 9C, a resist film 15 patterned so as to cover a portion corresponding to the Al pad 12 is formed on the Cu film 16x by photolithography. Thereafter, using the resist film 15 as a mask, the Cu film 16x is etched by wet etching using a solution (room temperature) containing hydrogen bromide (HBr) and ammonium persulfate. Subsequently, using the resist film 15 as a mask, the Cr film 13 is etched by wet etching using a solution (40 ° C.) containing iron trichloride (FeCl 3 ) and hydrochloric acid (HCl). Thereafter, the resist film 15 is removed.

これにより、図９（ｄ）に示すように、Ａｌパッド１２上にＣｒ膜１３及びＣｕ膜１６ｘが選択的に形成されて第２実施形態に係る接続パッド１８ｘが得られる。   As a result, as shown in FIG. 9D, the Cr film 13 and the Cu film 16x are selectively formed on the Al pad 12, and the connection pad 18x according to the second embodiment is obtained.

次に、第２実施形態に係る接続パッド１８ｘの形成方法の変形例について説明する。変形例１としては、図１２（ａ）に示すように、まず、図９（ａ）の構造を有するシリコンウェハ１０上に、Ａｌパッド１２に対応する部分に開口部１５ａを有するレジスト膜１５をフォトリソグラフィにより形成する。   Next, a modification of the method for forming the connection pad 18x according to the second embodiment will be described. As a first modification, as shown in FIG. 12A, first, a resist film 15 having an opening 15a in a portion corresponding to the Al pad 12 is formed on a silicon wafer 10 having the structure of FIG. 9A. It is formed by photolithography.

その後、図１２（ｂ）に示すように、前述した方法と同様なスパッタ法などにより、Ａｌパッド１２及びレジスト膜１５上にＣｒ膜１３及びＣｕ膜１６ｘを順次成膜する。   Thereafter, as shown in FIG. 12B, a Cr film 13 and a Cu film 16x are sequentially formed on the Al pad 12 and the resist film 15 by a sputtering method similar to the method described above.

続いて、レジスト剥離液によりレジスト膜１５を除去する。これにより、図１２（ｃ）に示すように、いわゆるリフトオフ法により、レジスト膜１５上に成膜されたＣｒ膜１３及びＣｕ膜１６ｘがレジスト膜１５と同時に除去されると共に、Ａｌパッド１２上に成膜されたＣｒ膜１３（又はＴｉ膜）及びＣｕ膜１６ｘが残されて上記した接続パッド１８ｘと同様な構成のものが得られる。変形例１においても、Ｃｒ膜１３の代わりにＴｉ膜を用いるようにしてもよい。   Subsequently, the resist film 15 is removed with a resist stripping solution. As a result, as shown in FIG. 12C, the Cr film 13 and the Cu film 16x formed on the resist film 15 are removed simultaneously with the resist film 15 by a so-called lift-off method, and at the same time, on the Al pad 12. The deposited Cr film 13 (or Ti film) and Cu film 16x are left to obtain the same configuration as the connection pad 18x described above. Also in the first modification, a Ti film may be used instead of the Cr film 13.

また、変形例２としては、図１３（ａ）に示すように、まず、図９（ａ）と同一構造のシリコンウェハ１０のＡｌパッド１２及びパシベーション膜１１上に、膜厚が０．０５μｍ程度のＣｒ膜１３及び膜厚が０．０５μｍ程度の第１Ｃｕ膜１６ｘをスパッタ法などにより順次成膜する。   As a second modification, as shown in FIG. 13A, first, a film thickness of about 0.05 μm is formed on the Al pad 12 and the passivation film 11 of the silicon wafer 10 having the same structure as FIG. The Cr film 13 and the first Cu film 16x having a thickness of about 0.05 μm are sequentially formed by sputtering or the like.

その後、図１３（ｂ）に示すように、Ａｌパッド１２に対応する第１Ｃｕ膜１６ｘの部分に開口部１５ａを有するレジスト膜１５をフォトリソグラフィにより形成する。続いて、図１３（ｃ）に示すように、第１Ｃｕ膜１６ｘをめっき給電層に利用した電解めっきにより、レジスト膜１５をマスクにして、レジスト膜１５の開口部１５ａに膜厚が５〜１０μｍ程度の第２Ｃｕ膜１６ｙを形成する。   Thereafter, as shown in FIG. 13B, a resist film 15 having an opening 15a in the portion of the first Cu film 16x corresponding to the Al pad 12 is formed by photolithography. Subsequently, as shown in FIG. 13C, by electrolytic plating using the first Cu film 16x as a plating power feeding layer, the resist film 15 is used as a mask, and the film thickness is 5 to 10 μm in the opening 15a of the resist film 15. The second Cu film 16y is formed to the extent.

次いで、レジスト膜１５を除去した後、第２Ｃｕ膜１６ｙをマスクにして、前述した方法と同様なエッチャントを用いたウェットエッチングにより、第１Ｃｕ膜１６ｘ及びＣｒ膜１３を順次エッチングする。   Next, after removing the resist film 15, the first Cu film 16x and the Cr film 13 are sequentially etched by wet etching using an etchant similar to the above-described method using the second Cu film 16y as a mask.

これにより、図１３（ｄ）に示すように、Ａｌパッド１２上に、Ｃｒ膜１３、第１Ｃｕ膜１６ｘ及び第２Ｃｕ膜１６ｙが選択的に形成されて、接続パッド１８ｘが得られる。変形例２においても、Ｃｒ膜１３の代わりにＴｉ膜を用いてもよい。   Thereby, as shown in FIG. 13D, the Cr film 13, the first Cu film 16x, and the second Cu film 16y are selectively formed on the Al pad 12, and the connection pad 18x is obtained. In the second modification, a Ti film may be used instead of the Cr film 13.

第１実施形態で説明したように接続パッド１８ｘの熱伝導性を向上させるなどの目的で厚膜（３μｍ程度以上）のＣｕ膜を形成する場合、前述したスパッタ法とフォトリソグラフィによる形成方法では、成膜やウェットエッチングにおけるスループットなどが問題になる場合が想定される。このため、変形例２では、まず、スパッタ法で薄膜のＣｒ膜１３及び第１Ｃｕ膜１６ｘを形成した後に、電解めっきによりＡｌパッド１２の上方に厚膜の第２Ｃｕ膜１６ｙを選択的に形成する。その後、厚膜の第２Ｃｕ膜１６ｙをマスクにして第１Ｃｕ膜１６ｘ及びＣｒ膜１３をエッチングすることにより接続パッド１８ｘを形成するようにしている。   As described in the first embodiment, when forming a thick Cu film (about 3 μm or more) for the purpose of improving the thermal conductivity of the connection pad 18x, the above-described sputtering method and photolithography forming method include: A case where throughput in film formation or wet etching becomes a problem is assumed. For this reason, in the second modification, first, after forming the thin Cr film 13 and the first Cu film 16x by sputtering, the thick second Cu film 16y is selectively formed above the Al pad 12 by electrolytic plating. . Thereafter, the first Cu film 16x and the Cr film 13 are etched using the thick second Cu film 16y as a mask to form the connection pad 18x.

このようにすることにより、スパッタ法とフォトリソグラフィを用いる第２実施形態においても、膜厚の厚いエッチングストップ層を有する接続パッド１８ｘを容易に形成することができる。   By doing so, also in the second embodiment using the sputtering method and photolithography, the connection pad 18x having the thick etching stop layer can be easily formed.

以上のように、変形例１又は変形例２の形成方法を用いて接続パッド１８ｘを形成するようにしてもよい。   As described above, the connection pad 18x may be formed using the forming method of the first modification or the second modification.

次いで、図１０（ａ）に示すように、第１実施形態と同様に、接続パッド１８ｘが形成されたシリコンウェハ１０の背面をグラインダーにより研削することにより、シリコンウェハ１０の厚みを１０〜１５０μｍに薄型化する。   Next, as shown in FIG. 10A, the thickness of the silicon wafer 10 is reduced to 10 to 150 μm by grinding the back surface of the silicon wafer 10 on which the connection pads 18x are formed with a grinder, as in the first embodiment. Thinner.

続いて、図１０（ｂ）に示すように、第１実施形態と同様に、接続パッド１８ｘが形成されたシリコンウェハ１０をダイシングすることにより、個片化された複数の半導体チップ２０ｘを得る。   Subsequently, as shown in FIG. 10B, as in the first embodiment, the silicon wafer 10 on which the connection pads 18x are formed is diced to obtain a plurality of individual semiconductor chips 20x.

次いで、図１１に示すように、この半導体チップ２０ｘを使用して、第１実施形態の図３（ａ）〜図５までの工程と同様な工程を遂行することにより、第２実施形態の電子部品実装構造１ａが得られる。   Next, as shown in FIG. 11, by using the semiconductor chip 20x, the same processes as those in FIGS. 3A to 5 of the first embodiment are performed, whereby the electronic device of the second embodiment is performed. A component mounting structure 1a is obtained.

第２実施形態の電子部品実装構造１ａは、第１実施形態と同様な効果を奏する。   The electronic component mounting structure 1a of the second embodiment has the same effects as those of the first embodiment.

なお、第２実施形態においても、第１実施形態で説明した各種の変形や変更を行なった形態としてもよい。   In the second embodiment, various modifications and changes described in the first embodiment may be used.

（第３の実施の形態）
図１４は本発明の第３実施形態の電子部品実装構造の製造方法を示す部分断面図である。第３実施形態が第１実施形態と異なる点は、Ａｌパッド１２上に導電性ペースト膜を形成してレーザプロセスでのエッチングストップ層とすることである。第３実施形態では第１実施形態と同一工程についてはその詳しい説明を省略する。 (Third embodiment)
FIG. 14 is a partial cross-sectional view showing the method for manufacturing the electronic component mounting structure according to the third embodiment of the present invention. The third embodiment is different from the first embodiment in that a conductive paste film is formed on the Al pad 12 to form an etching stop layer in a laser process. In the third embodiment, detailed description of the same steps as those in the first embodiment is omitted.

本発明の第３実施形態の電子部品実装構造の製造方法は、図１４（ａ）に示すように、まず、第１実施形態と同様なＡｌパッド１２を備えたシリコンウェハ１０（半導体ウェハ）を用意する。その後、図１４（ｂ）に示すように、Ａｌパッド１２上に導電性ペースト膜３８を選択的に形成する。例えば、スクリーン印刷などにより導電性ペースト材がＡｌパッド１２上に塗布された後に、キュアされて導電性ペースト膜３８となる。これにより、Ａｌパッド１２と導電性ペースト膜３８とにより構成される接続パッド１８ｙが得られる。   In the manufacturing method of the electronic component mounting structure according to the third embodiment of the present invention, as shown in FIG. 14A, first, a silicon wafer 10 (semiconductor wafer) having an Al pad 12 similar to that in the first embodiment is used. prepare. Thereafter, as shown in FIG. 14B, a conductive paste film 38 is selectively formed on the Al pad 12. For example, after a conductive paste material is applied on the Al pad 12 by screen printing or the like, it is cured to form the conductive paste film 38. As a result, the connection pad 18y constituted by the Al pad 12 and the conductive paste film 38 is obtained.

導電性ペースト３８としては、例えば、エポキシ系樹脂又はポリイミド系樹脂の中に銅（Ｃｕ）、銀（Ａｇ）、金（Ａｕ）又はニッケル（Ｎｉ）などの導電性粒子が分散されたものが使用される。第３実施形態では、この導電性ペースト膜３８が第１実施形態で説明したＣｕ膜１６などと同様にレーザプロセスでのエッチングストップ層として機能する。   As the conductive paste 38, for example, a paste in which conductive particles such as copper (Cu), silver (Ag), gold (Au), or nickel (Ni) are dispersed in an epoxy resin or a polyimide resin is used. Is done. In the third embodiment, the conductive paste film 38 functions as an etching stop layer in a laser process, like the Cu film 16 described in the first embodiment.

導電性ペースト膜３８を用いることにより、１０μｍ程度の厚膜のエッチングストップ層を複雑な工程を必要とすることなく短時間で簡易に形成することができる。   By using the conductive paste film 38, an etching stop layer having a thickness of about 10 μm can be easily formed in a short time without requiring a complicated process.

なお、Ａｌパッド１２と導電性ペースト膜３８との間にＣｒ膜又はＴｉ膜が形成された形態としてもよい。このＣｒ膜又はＴｉ膜は、スパッタ及びフォトリソグラフィ、あるいは電解めっきによりＡｌパッド１２上に選択的に形成される。   Note that a Cr film or a Ti film may be formed between the Al pad 12 and the conductive paste film 38. This Cr film or Ti film is selectively formed on the Al pad 12 by sputtering and photolithography or electrolytic plating.

次いで、図１４（ｃ）に示すように、第１実施形態と同様に、接続パッド１８ｙが形成されたシリコンウェハ１０の背面をグラインダーにより研削することにより、シリコンウェハ１０の厚みを１０〜１５０μｍに薄型化する。   Next, as shown in FIG. 14C, the thickness of the silicon wafer 10 is reduced to 10 to 150 μm by grinding the back surface of the silicon wafer 10 on which the connection pads 18 y are formed with a grinder, as in the first embodiment. Thinner.

続いて、図１４（ｄ）に示すように、第１実施形態と同様に、接続パッド１８ｙが形成されたシリコンウェハ１０をダイシングすることにより、個片化された複数の半導体チップ２０ｙを得る。   Subsequently, as shown in FIG. 14D, as in the first embodiment, the silicon wafer 10 on which the connection pads 18y are formed is diced to obtain a plurality of individual semiconductor chips 20y.

次いで、図１５に示すように、この半導体チップ２０ｙを使用して、第１実施形態の図３（ａ）〜図５までの工程と同様な工程を遂行することにより、第３実施形態の電子部品実装構造１ｂが得られる。   Next, as shown in FIG. 15, the semiconductor chip 20y is used to perform the same steps as the steps from FIG. 3A to FIG. A component mounting structure 1b is obtained.

第３実施形態の電子部品実装構造１ｂは、第１実施形態と同様な効果を奏する。   The electronic component mounting structure 1b of the third embodiment has the same effects as those of the first embodiment.

なお、第３実施形態においても、第１実施形態で説明した各種の変形や変更を行なった形態としてもよい。   In the third embodiment, various modifications and changes described in the first embodiment may be used.

以上、第１〜第３実施形態により、本発明の詳細を説明したが、本発明の範囲は前述の実施形態に具体的に示した例に限られるものではなく、この発明を逸脱しない要旨の範囲における上記の実施形態の変更は本発明の範囲に含まれる。   The details of the present invention have been described above with reference to the first to third embodiments. However, the scope of the present invention is not limited to the examples specifically shown in the above-described embodiments, and the gist that does not depart from the present invention. Variations of the above-described embodiments in scope are within the scope of the invention.

本発明は、半導体チップの本来の金属パッド（例えばＡｌパッド）上に該金属パッドよりレーザでのエッチングレートが低いエッチングストップ層を設けるようにしたことを特徴の一つとしている。   One feature of the present invention is that an etching stop layer having a laser etching rate lower than that of the metal pad is provided on the original metal pad (for example, Al pad) of the semiconductor chip.

従って、実施形態ではＡｌパッド上にレーザでのエッチングレートが低い金属膜や導電性ペースト膜を設けた形態を例示したが、Ａｌ以外の金属パッド上にそれよりレーザでのエッチングレートが低い金属膜や導電性ペースト膜を形成した形態としてもよい。つまり、Ａｌパッド以外の所要の各種金属パッドを備えた電子部品にも本発明を適用することができる。   Therefore, in the embodiment, the metal film having a low etching rate by laser or the conductive paste film is provided on the Al pad, but the metal film having a lower etching rate by laser on the metal pad other than Al. Alternatively, a conductive paste film may be formed. That is, the present invention can also be applied to electronic parts having various required metal pads other than Al pads.

図１は半導体チップが絶縁膜に埋設されて実装された半導体装置の製造における不具合な点を示す断面図である。FIG. 1 is a cross-sectional view showing problems in manufacturing a semiconductor device in which a semiconductor chip is embedded and mounted in an insulating film. 図２は本発明の第１実施形態の電子部品実装構造の製造方法を示す部分断面図（その１）である。FIG. 2 is a partial cross-sectional view (No. 1) showing the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. 図３は本発明の第１実施形態の電子部品実装構造の製造方法を示す部分断面図（その２）である。FIG. 3 is a partial cross-sectional view (part 2) illustrating the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. 図４は本発明の第１実施形態の電子部品実装構造の製造方法を示す部分断面図（その３）である。FIG. 4 is a partial cross-sectional view (part 3) illustrating the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. 図５は本発明の第１実施形態の電子部品実装構造の製造方法を示す部分断面図（その４）である。FIG. 5 is a partial cross-sectional view (part 4) illustrating the method for manufacturing the electronic component mounting structure according to the first embodiment of the present invention. 図６は本発明の第１実施形態の電子部品実装構造に係る接続パッドの変形例１を示す部分断面図である。FIG. 6 is a partial cross-sectional view showing Modification Example 1 of the connection pad according to the electronic component mounting structure of the first embodiment of the present invention. 図７は本発明の第１実施形態の電子部品実装構造に係る接続パッドの変形例２を示す部分断面図である。FIG. 7 is a partial cross-sectional view showing Modification Example 2 of the connection pad according to the electronic component mounting structure of the first embodiment of the present invention. 図８は本発明の第１実施形態の電子部品実装構造に係る接続パッドの変形例３を示す部分断面図である。FIG. 8 is a partial cross-sectional view showing Modification Example 3 of the connection pad according to the electronic component mounting structure of the first embodiment of the present invention. 図９は本発明の第２実施形態の電子部品実装構造の製造方法を示す部分断面図（その１）である。FIG. 9 is a partial cross-sectional view (part 1) illustrating the method for manufacturing the electronic component mounting structure according to the second embodiment of the present invention. 図１０は本発明の第２実施形態の電子部品実装構造の製造方法を示す部分断面図（その２）である。FIG. 10 is a partial cross-sectional view (part 2) illustrating the method for manufacturing the electronic component mounting structure according to the second embodiment of the present invention. 図１１は本発明の第２実施形態の電子部品実装構造の製造方法を示す部分断面図（その３）である。FIG. 11: is a fragmentary sectional view (the 3) which shows the manufacturing method of the electronic component mounting structure of 2nd Embodiment of this invention. 図１２は本発明の第２実施形態の電子部品実装構造に係る接続パッドの形成方法の変形例１を示す部分断面図である。FIG. 12 is a partial cross-sectional view showing a first modification of the connection pad forming method according to the electronic component mounting structure of the second embodiment of the present invention. 図１３は本発明の第２実施形態の電子部品実装構造に係る接続パッドの形成方法の変形例２を示す部分断面図である。FIG. 13: is a fragmentary sectional view which shows the modification 2 of the formation method of the connection pad which concerns on the electronic component mounting structure of 2nd Embodiment of this invention. 図１４は本発明の第３実施形態の電子部品実装構造の製造方法を示す部分断面図（その１）である。FIG. 14 is a partial cross-sectional view (part 1) illustrating the method for manufacturing the electronic component mounting structure according to the third embodiment of the present invention. 図１５は本発明の第３実施形態の電子部品実装構造の製造方法を示す部分断面図（その２）である。FIG. 15: is a fragmentary sectional view (the 2) which shows the manufacturing method of the electronic component mounting structure of 3rd Embodiment of this invention.

符号の説明Explanation of symbols

１，１ａ…電子部品実装構造、１０…シリコン基板（半導体ウェハ）、１１…パシベーション膜、１２…Ａｌパッド、１３…Ｃｒ膜、１４…Ｎｉ膜、１６，１６ｘ，１６ｙ…Ｃｕ膜、１７…Ａｕ膜、１８，１８ｘ…接続パッド、１９…Ａｇ膜、２０，２０ａ，２０ｘ…半導体チップ（電子部品）、２４…ベース基板、２４ａ…スルーホール、２４ｂ…スルーホールめっき層、２４ｃ…樹脂、２６…第１配線パターン、２６ａ…第２配線パターン、２６ｂ…第３配線パターン、２７…接着層、２８…第１層間絶縁膜、２８ａ…第２層間絶縁膜、２８ｘ…第１ビアホール、２８ｙ…第２ビアホール、３０ａ…シードＣｕ膜、３０ｂ…Ｃｕ膜パターン、１５，３２…レジスト膜、１５ａ，３２ａ，３４ａ…開口部、３４…ソルダレジスト膜、３６…バンプ、３８…導電性ペースト膜。 DESCRIPTION OF SYMBOLS 1,1a ... Electronic component mounting structure, 10 ... Silicon substrate (semiconductor wafer), 11 ... Passivation film, 12 ... Al pad, 13 ... Cr film, 14 ... Ni film, 16, 16x, 16y ... Cu film, 17 ... Au Membrane, 18, 18x ... connection pad, 19 ... Ag membrane, 20, 20a, 20x ... semiconductor chip (electronic component), 24 ... base substrate, 24a ... through hole, 24b ... through hole plating layer, 24c ... resin, 26 ... 1st wiring pattern, 26a ... 2nd wiring pattern, 26b ... 3rd wiring pattern, 27 ... Adhesive layer, 28 ... 1st interlayer insulation film, 28a ... 2nd interlayer insulation film, 28x ... 1st via hole, 28y ... 2nd Via hole, 30a ... seed Cu film, 30b ... Cu film pattern, 15, 32 ... resist film, 15a, 32a, 34a ... opening, 34 ... solder resist film, 36 ... Amplifier, 38 ... conductive paste film.

Claims (1)

接続パッドがアルミニウム又はアルミニウム合金からなるアルミニウムパッドと、前記アルミニウムパッドの上に形成されたエッチングストップ層とから構成される前記接続パッドを有する電子部品を用意する工程であって、
前記エッチングストップ層は、それぞれ下から順に、ニッケル膜／銅膜、ニッケル膜／金膜、ニッケル膜／銅膜／金膜、又はニッケル膜／銀膜であり、
前記電子部品を用意する工程は、
前記アルミニウムパッドを備えた半導体ウェハの該アルミニウムパッド上に、無電解めっきにより前記ニッケル膜を選択的に形成する工程と、
前記ニッケル膜上に、無電解めっきにより、前記銅膜、前記金膜、前記銅膜／金膜、又は前記銀膜を選択的に形成して前記接続パッドとする工程と、
前記半導体ウェハの背面を研削して薄型化する工程と、
前記半導体ウェハをダイシングすることにより前記電子部品を得る工程とを含み、
被実装体の上に、前記電子部品を、該接続パッドを上向きにした状態で実装する工程であって、前記被実装体は、配線パターンを備えたベース基板、又は該ベース基板上に絶縁膜と配線パターンとが所定数積層された構造体であり、
前記電子部品を被覆する絶縁膜を形成する工程と、
前記接続パッド上の前記絶縁膜の所定部、及び前記電子部品の下側の前記配線パターン上の前記絶縁膜の所定部をレーザによりエッチングすることにより、ビアホールを形成する工程と、
前記ビアホールを介して前記接続パッドに接続されると共に、前記ビアホールを介して前記電子部品の下側の前記配線パターンに接続される配線パターンを前記絶縁膜の上に形成する工程とを有し、
前記エッチングストップ層は、レーザによって前記絶縁層に前記ビアホールを形成する際のストップ層として機能し、前記ビアホールは前記エッチングストップ層を介して前記アルミニウムパッドに接続されることを特徴とする電子部品実装構造の製造方法。 A step of preparing an electronic component having the connection pad composed of an aluminum pad made of aluminum or an aluminum alloy and an etching stop layer formed on the aluminum pad;
The etching stop layer is, in order from the bottom, nickel film / copper film, nickel film / gold film, nickel film / copper film / gold film, or nickel film / silver film,
The step of preparing the electronic component includes:
Selectively forming the nickel film on the aluminum pad of the semiconductor wafer provided with the aluminum pad by electroless plating;
A step of selectively forming the copper film, the gold film, the copper film / gold film, or the silver film on the nickel film by electroless plating to form the connection pad;
Grinding and thinning the back surface of the semiconductor wafer;
Obtaining the electronic component by dicing the semiconductor wafer,
A step of mounting the electronic component on a mounted body with the connection pads facing upward, wherein the mounted body is a base substrate provided with a wiring pattern, or an insulating film on the base substrate And a structure in which a predetermined number of wiring patterns are laminated,
Forming an insulating film covering the electronic component;
Forming a via hole by etching a predetermined portion of the insulating film on the connection pad and a predetermined portion of the insulating film on the wiring pattern below the electronic component with a laser; and
Forming on the insulating film a wiring pattern connected to the connection pad via the via hole and connected to the wiring pattern on the lower side of the electronic component via the via hole;
The etching stop layer functions as a stop layer when the via hole is formed in the insulating layer by a laser, and the via hole is connected to the aluminum pad via the etching stop layer. Structure manufacturing method.
JP2008175380A 2008-07-04 2008-07-04 Method for manufacturing electronic parts packaging structure Pending JP2008288607A (en)

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EP2386193A1 (en) * 2009-01-09 2011-11-16 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Printed circuit board element having at least one laser beam stop element and method for producing a printed circuit board element
JP2012514859A (en) * 2009-01-09 2012-06-28 エイティー アンド エス オーストリア テヒノロギー ウント ズュステームテヒニーク アクチエンゲゼルシャフト Printed circuit board element having at least one laser beam stop element and method for making a printed circuit board element
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