JP2008277495A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2008277495A
JP2008277495A JP2007118407A JP2007118407A JP2008277495A JP 2008277495 A JP2008277495 A JP 2008277495A JP 2007118407 A JP2007118407 A JP 2007118407A JP 2007118407 A JP2007118407 A JP 2007118407A JP 2008277495 A JP2008277495 A JP 2008277495A
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polishing
film
polished
polishing process
interlayer insulating
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Noritaka Kamikubo
徳貴 上久保
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Sharp Corp
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Priority to PCT/JP2008/056857 priority patent/WO2008136240A1/en
Priority to TW97113542A priority patent/TW200908120A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents

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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Organic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a planarization method which suppresses defects on a surface of a polished film and can control a thickness of the polished film, and to provide a manufacturing method of a semiconductor device using such the planarization method. <P>SOLUTION: An interlayer insulating film 3 is formed on a semiconductor substrate 1 formed with a semiconductor element 2. When this takes place, a projected part 4 having a higher position than a periphery and a non-projected part 5 having a lower position than the projected part 4 exist on a surface of the formed interlayer insulating film 3. For such the interlayer insulating film 3, first, a first polishing processing is conducted by use of abrasive grains having non-Prestonian characteristics to planarize the projected part 4. Thereafter, a second polishing processing in which a polishing pressure is set to 1.5 times or more is executed on the surface of the interlayer insulating film 3. Thus, the number of defects remaining on the surface of the interlayer insulating film 3 after polishing can be suppressed, and further a control of a film thickness of the interlayer insulating film 3 which is desired to remain is facilitated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置の製造方法であって、特に成膜後に表面を平坦化するための平坦化方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a planarization method for planarizing a surface after film formation.

半導体集積回路装置の高集積化に伴い、その製造過程において、微細なパターンを高精度に形成するために基板表面を均一に平坦化する平坦化技術が重要となっている。このような平坦化技術としては、従来、研磨液（スラリー）を用いて基板を研磨布（パッド）へ押し付けて摩擦研磨するＣＭＰ（Chemical Mechanical Polishing ：化学機械研磨）法が広く用いられている。   Along with the high integration of semiconductor integrated circuit devices, in the manufacturing process, in order to form a fine pattern with high accuracy, a flattening technique for uniformly flattening the substrate surface has become important. As such a planarization technique, a CMP (Chemical Mechanical Polishing) method in which a substrate is pressed against a polishing cloth (pad) using a polishing liquid (slurry) and friction-polished is widely used.

このＣＭＰ法による平坦化を行うに際し、特に高い平坦性が要求されるような場合、例えば、ＳＴＩ（Shallow Trench Isolation）法によって素子分離領域を形成するに際し当該方法により形成されるトレンチ内の埋め込み絶縁膜の余剰分を研磨除去するような場合には、下記特許文献１に記載のように、酸化セリウム（「セリア」とも称される）を砥粒としたスラリーが広く用いられている。   When performing planarization by this CMP method, particularly when high planarity is required, for example, when forming an element isolation region by STI (Shallow Trench Isolation) method, buried insulation in a trench formed by this method is used. In the case where the excess of the film is removed by polishing, as described in Patent Document 1 below, a slurry using cerium oxide (also referred to as “ceria”) as abrasive grains is widely used.

これは、酸化セリウムを砥粒とし、適切な有機化合物を添加剤としたスラリーを用いることにより、従来一般に用いられてきた酸化シリコン（シリカ）を砥粒としたスラリーを用いた場合と比較して、より高いシリコン酸化膜の研磨速度と、研磨ストッパー膜として用いられる窒化ケイ素膜に対するより高い研磨速度選択性が得られることによるものである。また、酸化セリウムが、研磨圧力が一定値より低い場合に研磨速度が小さくなる、いわゆる非プレストニアン特性を有しているため、研磨ストッパー膜が露出した段階で、素子分離領域のシリコン酸化膜が余剰に研磨されるのを抑制することが可能となる。これにより、パターン依存性の少ない、高平坦性を有する研磨を実現することができる。   Compared to the case of using a slurry of silicon oxide (silica), which has been conventionally used, by using a slurry containing cerium oxide as an abrasive and an appropriate organic compound as an additive. This is because higher polishing rate of the silicon oxide film and higher polishing rate selectivity with respect to the silicon nitride film used as the polishing stopper film can be obtained. In addition, since cerium oxide has a so-called non-Prestonian characteristic in which the polishing rate decreases when the polishing pressure is lower than a certain value, the silicon oxide film in the element isolation region is exposed at the stage where the polishing stopper film is exposed. It is possible to suppress excessive polishing. As a result, it is possible to realize polishing having high flatness with little pattern dependency.

さらに近年では、下記特許文献２に示されるように、研磨圧力（研磨時の押し付け圧力）が一定値より低い場合の研磨速度が毎分２０〜５０ｎｍ程度の、非プレストニアン特性の強い研磨材が提供されている。このような研磨材を用いて凸部を有する形状の被研磨膜表面を研磨する場合、凸部が存在する状況下においては、毎分１００〜１０００ｎｍ程度の研磨速度で研磨が行われていたのに対し、凸部が平坦化されて被研磨膜表面がほぼ平坦となった段階で、研磨速度は毎分５０ｎｍ程度以下に急激に低下し、通常に用いられる研磨速度に比してほとんど研磨が進行しなくなる。   Further, in recent years, as shown in Patent Document 2 below, an abrasive having a strong non-Prestonian property with a polishing rate of about 20 to 50 nm per minute when the polishing pressure (pressing pressure at the time of polishing) is lower than a certain value has been developed. Is provided. When polishing the surface of a film to be polished having a convex portion using such an abrasive, polishing was performed at a polishing rate of about 100 to 1000 nm per minute in the situation where the convex portion exists. On the other hand, at the stage where the convex portion is flattened and the surface of the film to be polished is almost flat, the polishing rate rapidly decreases to about 50 nm or less per minute, and the polishing is almost less than the polishing rate normally used. It will not progress.

すなわち、このような非プレストニアン特性の強い砥粒（研磨材）を用いることで、半導体素子や金属配線形成後に成膜された凸部を有する層間絶縁膜等のように、被研磨膜と異なる材料の研磨ストッパー膜が存在しない場合においても、凸部が平坦化された段階で自動的に研磨速度が急激に低下する（ほとんど進行しない、オートストップ）ため、このような層間絶縁膜に対しても高平坦性を有する研磨処理を実現することができる。   In other words, by using such abrasive grains (abrasive material) having strong non-Prestonian characteristics, it is different from a film to be polished, such as an interlayer insulating film having a convex portion formed after forming a semiconductor element or a metal wiring. Even in the absence of a material polishing stopper film, the polishing rate automatically decreases sharply when the projections are flattened (almost no progress, auto-stop). A polishing process having high flatness can be realized.

特開２００１−３１０２５６号公報JP 2001-310256 A 特開２００６−２７９０５０号公報JP 2006-279050 A

しかしながら、上記のような非プレストニアン特性の強い砥粒を用いて凸部を有する被研磨膜に対する平坦化処理（研磨処理）を実行した場合、凸部が平坦化されることで被研磨膜表面がほぼ平坦化されると、自動的に研磨がほとんど進行しなくなる。このため、被研磨膜表面に生じたスクラッチ等の欠陥が存在していても、当該欠陥が除去されること無くそのまま残存してしまうので、平坦化処理後の被研磨膜表面の欠陥密度が非常に大きくなるという問題が生ずる。また、凸部の平坦化後は研磨速度が非常に遅いため、予め測定したＣＭＰ処理の前段階での成膜量に応じて、ＣＭＰ処理時の研磨量を処理ロット毎に制御することが困難であるという問題が生ずる。   However, when a flattening process (polishing process) is performed on a film to be polished having a convex part using abrasive grains having a strong non-Prestonian characteristic as described above, the surface of the film to be polished is caused by the flattening of the convex part. When the film is almost flattened, the polishing hardly proceeds automatically. For this reason, even if there are defects such as scratches generated on the surface of the film to be polished, the defects remain as they are without being removed. Therefore, the defect density on the surface of the film to be polished after the planarization process is extremely high. The problem of becoming large arises. In addition, since the polishing rate is very slow after the flattening of the projections, it is difficult to control the polishing amount at the time of CMP processing for each processing lot according to the film formation amount at the previous stage of the CMP processing measured in advance. The problem arises.

本発明は、上記の問題点に鑑み、成膜された被研磨膜の表面を非プレストニアン特性の強い材料を砥粒として平坦化するに際し、当該被研磨膜表面に存する欠陥を抑制するとともに、被研磨膜厚を制御可能な平坦化方法を提供し、かかる平坦化方法を用いた半導体装置の製造方法を提供することを目的とする。   In view of the above problems, the present invention suppresses defects existing on the surface of the film to be polished when the surface of the film to be polished is flattened with abrasive material having a strong non-Prestonian property, An object of the present invention is to provide a planarization method capable of controlling the film thickness to be polished, and to provide a method for manufacturing a semiconductor device using the planarization method.

上記目的を達成するための本発明に係る半導体装置の製造方法は、半導体基板上に絶縁膜または導電膜で構成される被研磨膜を成膜する成膜工程と、前記成膜工程終了後、前記被研磨膜の成膜表面を平坦化する平坦化工程と、を有する半導体装置の製造方法であって、前記平坦化工程が、非プレストニアン特性を有する砥粒を用いて前記被研磨膜の表面に対して研磨処理を行う第１研磨処理と、前記第１研磨処理を終了後、前記第１研磨処理と比較して１．５倍以上の研磨圧力の下で前記被研磨膜の表面に対して研磨処理を行う第２研磨処理と、を有し、前記第１研磨処理が、前記被研磨膜の成膜表面を、少なくとも前記半導体基板面に垂直な方向の高さまたは深さが１００ｎｍ以上の凸部または凹部が存在しない第１表面状態に変化させた段階で終了することを第１の特徴とする。   In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes: a film forming process for forming a film to be polished formed of an insulating film or a conductive film on a semiconductor substrate; A planarization step of planarizing a film-forming surface of the film to be polished, wherein the planarization step is performed using abrasive grains having non-Prestonian characteristics. A first polishing process for polishing the surface, and after finishing the first polishing process, the surface of the film to be polished is subjected to a polishing pressure of 1.5 times or more compared to the first polishing process. A second polishing process for performing a polishing process on the surface of the film to be polished, the height or depth of the film to be polished being at least perpendicular to the semiconductor substrate surface is 100 nm. It was changed to the first surface state where the above convex part or concave part does not exist. The first, characterized in that ends at floor.

本発明に係る半導体装置の製造方法の上記第１の特徴によれば、研磨圧力が相対的に小さい第１研磨処理によって、被研磨膜表面に存する凸部または凹部を平坦化するとともに、研磨圧力が相対的に大きい第２研磨処理によって、第１研磨処理後に被研磨膜表面に発生した欠陥が存在する領域を研磨することで、研磨後の表面に損する欠陥数を削減することができる。これにより、成膜された被研磨膜を過剰に研磨することなく、当該被研磨膜表面に対する平坦化処理が行えるとともに、研磨後の被研磨膜内に存する欠陥量を従来よりも大きく減少することができる。   According to the first feature of the method of manufacturing a semiconductor device according to the present invention, the first polishing process with a relatively low polishing pressure flattens the convex portion or the concave portion existing on the surface of the film to be polished, and the polishing pressure. By polishing the region where defects generated on the surface of the film to be polished exist after the first polishing process by the relatively large second polishing process, the number of defects lost on the polished surface can be reduced. As a result, the surface of the film to be polished can be flattened without excessively polishing the film to be polished, and the amount of defects existing in the film to be polished after polishing can be greatly reduced as compared with the prior art. Can do.

さらに、第１研磨処理の後で行われる第２研磨処理は、第１研磨処理と比較して研磨圧力が大きいため、第１表面状態の被研磨膜表面に対しても監視可能な速度で研磨を行うことができる。これにより、あらかじめ定められた膜厚だけ研磨した時点で第２研磨処理を終了させる制御が可能となり、残存させたい被研磨膜の膜厚の調整を容易に行うことができる。   Furthermore, since the second polishing process performed after the first polishing process has a higher polishing pressure than the first polishing process, the surface of the film to be polished in the first surface state is polished at a speed that can be monitored. It can be performed. This makes it possible to control the second polishing process to end when the predetermined film thickness is polished, and to easily adjust the film thickness of the film to be polished.

また、本発明に係る半導体装置の製造方法は、上記第１の特徴に加えて、前記第１研磨処理において、前記第１表面状態を示す成膜表面に対する研磨速度が、開始直後の研磨速度の１／４以下であることを第２の特徴とする。   The semiconductor device manufacturing method according to the present invention, in addition to the first feature, in the first polishing process, the polishing rate for the film-forming surface showing the first surface state is the polishing rate immediately after the start. The second characteristic is that it is 1/4 or less.

本発明に係る半導体装置の製造方法の上記第２の特徴によれば、第１研磨処理によって凸部または凹部に対して平坦化が施され、被研磨膜表面が第１表面状態となった段階で、研磨速度が大きく減少するため、第１研磨処理の終了タイミングを容易に認識することができる。また、第１表面状態となった被研磨膜表面に対する研磨速度が十分遅いため、凸部または凹部に対する平坦化処理が完了した後、過剰に被研磨膜を研磨するということがない。   According to the second feature of the method for manufacturing a semiconductor device according to the present invention, the surface of the film to be polished is brought into the first surface state by planarizing the convex portion or the concave portion by the first polishing process. Since the polishing rate is greatly reduced, the end timing of the first polishing process can be easily recognized. Further, since the polishing rate for the surface of the film to be polished in the first surface state is sufficiently slow, the film to be polished is not excessively polished after the planarization process for the convex portion or the concave portion is completed.

また、本発明に係る半導体装置の製造方法は、上記第１または第２の特徴に加えて、前記第２研磨処理が、前記第１表面状態を示す成膜表面に対して毎分２００ｎｍ以上の研磨が可能な研磨条件で行われることを第３の特徴とする。   In addition to the first or second feature, the method for manufacturing a semiconductor device according to the present invention may be configured such that the second polishing process is performed at a rate of 200 nm or more per minute with respect to the film formation surface indicating the first surface state. The third feature is that the polishing is performed under polishing conditions.

本発明に係る半導体装置の製造方法の上記第３の特徴によれば、第１研磨処理後に被研磨膜表面に存する欠陥が含まれる成膜領域を、第１研磨処理と比較して研磨後に残存する欠陥数を減少させながら研磨することができる。また、第１表面状態の被研磨膜表面に対しても監視可能な研磨速度で研磨することができるため、研磨膜厚の制御が容易化される。これによって、第１研磨処理後に発生した欠陥が多く含まれる成膜領域のみを研磨した後第２研磨処理を終了させる制御を行うことで、過剰に研磨することなく研磨後の被研磨膜に残存する欠陥数を抑制することができる。   According to the third feature of the method for manufacturing a semiconductor device according to the present invention, a film formation region including defects present on the surface of the film to be polished after the first polishing process is left after polishing compared to the first polishing process. Polishing can be performed while reducing the number of defects. Further, since the surface of the film to be polished in the first surface state can be polished at a polishing rate that can be monitored, the control of the polishing film thickness is facilitated. As a result, the second polishing process is controlled after polishing only the film formation region containing many defects generated after the first polishing process, so that it remains in the polished film without being excessively polished. The number of defects to be suppressed can be suppressed.

また、本発明に係る半導体装置の製造方法は、上記第１〜第３のいずれか一の特徴に加えて、前記第１研磨処理が、前記第１表面状態を示す成膜表面に対して毎分５０ｎｍ以下の研磨が可能な研磨条件で行われることを第４の特徴とする。   Further, in addition to any one of the first to third features, the method for manufacturing a semiconductor device according to the present invention performs the first polishing process every time on the film formation surface showing the first surface state. A fourth feature is that the polishing is performed under polishing conditions that allow polishing of 50 nm or less.

本発明に係る半導体装置の製造方法の上記第４の特徴によれば、第１表面状態となった被研磨膜表面に対する研磨速度が十分遅いため、凸部または凹部に対する平坦化処理が完了した後に、過剰に被研磨膜を研磨することがない。これにより、第１研磨処理で過剰に研磨することなく第２研磨処理に移行することができる。   According to the fourth feature of the method of manufacturing a semiconductor device according to the present invention, the polishing rate for the surface of the film to be polished that is in the first surface state is sufficiently slow, so that the planarization process for the convex portion or the concave portion is completed. The film to be polished is not excessively polished. Thereby, it can transfer to a 2nd grinding | polishing process, without grind | polishing excessively by a 1st grinding | polishing process.

また、本発明に係る半導体装置の製造方法は、上記第１〜第４のいずれか一の特徴に加えて、前記第２研磨処理が、前記被研磨膜に対して膜厚３０ｎｍ以上研磨を施して終了することを第５の特徴とする。   In the semiconductor device manufacturing method according to the present invention, in addition to any one of the first to fourth features, the second polishing treatment polishes the polishing target film with a film thickness of 30 nm or more. This is the fifth feature.

本発明に係る半導体装置の製造方法の上記第５の特徴によれば、第２研磨処理後の被研磨膜に残存する欠陥数を、その後の製造工程に支障のない範囲内に抑制することができる。   According to the fifth feature of the method for manufacturing a semiconductor device according to the present invention, the number of defects remaining in the film to be polished after the second polishing process is suppressed within a range that does not hinder subsequent manufacturing processes. it can.

また、本発明に係る半導体装置の製造方法は、上記第１〜第５のいずれか一の特徴に加えて、前記被研磨膜が、ＨＤＰ（High-Density Plasma：高密度プラズマ）法により成膜されたシリコン酸化膜であることを第６の特徴とする。   Further, in the semiconductor device manufacturing method according to the present invention, in addition to any one of the first to fifth features, the film to be polished is formed by an HDP (High-Density Plasma) method. A sixth feature is that the silicon oxide film is formed.

本発明に係る半導体装置の製造方法の上記第６の特徴によれば、第１研磨処理において、第１表面状態となった被研磨膜に対する研磨速度を十分遅くすることができ、これによって過剰に被研磨膜が研磨されるのを抑制することができる。   According to the sixth feature of the method for manufacturing a semiconductor device according to the present invention, the polishing rate for the film to be polished in the first surface state can be sufficiently slowed in the first polishing process. Polishing of the film to be polished can be suppressed.

本発明の構成によれば、平坦化後の被研磨膜表面に存する欠陥数を削減することができるとともに、平坦化後の被研磨膜の残存膜厚の制御が容易化される。   According to the configuration of the present invention, the number of defects existing on the surface of the film to be polished after planarization can be reduced, and the remaining film thickness of the film to be polished after planarization can be easily controlled.

以下において、本発明に係る半導体装置の製造方法（以下、適宜「本発明方法」と称する）の実施形態について、以下の図１〜図３の各図を参照して説明する。   In the following, an embodiment of a method for manufacturing a semiconductor device according to the present invention (hereinafter referred to as “the method of the present invention” as appropriate) will be described with reference to the following FIGS.

図１は、本発明方法の各工程における概略断面構造図を模式的に示したものであり、工程毎に図１（ａ）〜（ｄ）に分けて図示している。また、図２は、本発明方法の製造工程をフローチャートにしたものであり、以下の文中の各ステップは図２に示されるフローチャートの各ステップを表すものとする。なお、図１に示される概略断面構造図は、あくまで模式的に図示されたものであり、実際の構造の寸法の縮尺と図面の縮尺とは必ずしも一致するものではない。   FIG. 1 schematically shows a schematic cross-sectional structure diagram in each step of the method of the present invention, which is divided into FIGS. 1A to 1D for each step. FIG. 2 is a flowchart of the manufacturing process of the method of the present invention, and each step in the following sentence represents each step of the flowchart shown in FIG. Note that the schematic cross-sectional structure diagram shown in FIG. 1 is merely schematically illustrated, and the scale of the actual structure does not necessarily match the scale of the drawing.

まず、図１（ａ）に示すように、半導体基板１上に半導体素子あるいは金属配線層（以下、単に「半導体素子２」と記載）を形成し、その上面に層間絶縁膜３を堆積する（ステップ＃１）。層間絶縁膜３としては、プラズマシリコン酸化膜（Ｐ−ＳｉＯ膜）を、ＨＤＰ（High-Density Plasma：高密度プラズマ）法によって、成膜温度２００〜７００℃程度、圧力０．０１〜１０Ｐａ程度の下で膜厚１００〜２０００ｎｍ程度堆積する。なお、層間絶縁膜３を堆積する膜厚は、少なくとも前記半導体素子２の高さより大きいものとする。   First, as shown in FIG. 1A, a semiconductor element or a metal wiring layer (hereinafter simply referred to as “semiconductor element 2”) is formed on a semiconductor substrate 1, and an interlayer insulating film 3 is deposited on the upper surface thereof (see FIG. 1A). Step # 1). As the interlayer insulating film 3, a plasma silicon oxide film (P-SiO film) is formed at a film formation temperature of about 200 to 700 ° C. and a pressure of about 0.01 to 10 Pa by HDP (High-Density Plasma) method. A film thickness of about 100 to 2000 nm is deposited below. The film thickness for depositing the interlayer insulating film 3 is at least larger than the height of the semiconductor element 2.

このステップ＃１に係る層間絶縁膜３の堆積によって、図１（ａ）に示すように、半導体素子２が形成されている領域の上部と、それ以外の領域の上部との間で、表面に一定の凹凸が生じる。以下では、これらの凹凸部を、それぞれ「凸部４」、「非凸部５」と称する。   By depositing the interlayer insulating film 3 according to Step # 1, as shown in FIG. 1A, the surface is formed between the upper portion of the region where the semiconductor element 2 is formed and the upper portion of the other region. Certain irregularities occur. Hereinafter, these uneven portions are referred to as “convex portion 4” and “non-convex portion 5”, respectively.

なお、ここで想定している凹凸部とは、層間絶縁膜の成膜表面において、半導体基板１の基板面に垂直な方向に１００ｎｍ以上高さ位置が相違する領域を指すものとする。すなわち、前記凸部４は、最上面の高さ位置が、隣接する非凸部５の最上面の高さ位置よりも１００ｎｍ以上高いものとする。   In addition, the uneven | corrugated | grooved part assumed here shall refer to the area | region where the height position differs 100 nm or more in the direction perpendicular | vertical to the substrate surface of the semiconductor substrate 1 in the film-forming surface of an interlayer insulation film. That is, the convex part 4 has a height position of 100 nm or more higher than the height position of the uppermost surface of the adjacent non-convex part 5.

次に、図１（ｂ）及び（ｃ）に示すように、ＣＭＰ法により、酸化セリウムを砥粒として含む研磨材を用いた研磨処理（以下、「第１研磨処理」と称する）を基板面に対して行う（ステップ＃２）。これにより、層間絶縁膜３の上面に形成されている凸部４の平坦化を行う。なお、図１（ｂ）は第１研磨処理を実行途中の断面図、図１（ｃ）は第１研磨処理の完了時の断面図をそれぞれ示している。図１（ｃ）に示されるように、第１研磨処理が完了した時点では、層間絶縁膜３の表面は、凸部４が存在しない状態（以下、適宜「第１表面状態」と称する）となっている。   Next, as shown in FIGS. 1B and 1C, a polishing process using a polishing material containing cerium oxide as abrasive grains (hereinafter referred to as “first polishing process”) is performed by CMP. (Step # 2). Thereby, the convex part 4 formed on the upper surface of the interlayer insulating film 3 is flattened. 1B is a cross-sectional view in the middle of executing the first polishing process, and FIG. 1C is a cross-sectional view when the first polishing process is completed. As shown in FIG. 1C, when the first polishing process is completed, the surface of the interlayer insulating film 3 is in a state in which the convex portion 4 does not exist (hereinafter referred to as “first surface state” as appropriate). It has become.

当該ステップ＃２に係る第１研磨処理工程では、一般的に行なわれる酸化セリウムを砥粒として含む研磨材によるＣＭＰ法のように、凸部４に対し高い研磨速度を持ち、第１表面状態（図１（ｃ）の状態）において、研磨速度が自動的に低下してオートストップが生じるような条件下で研磨処理を行う。   In the first polishing process according to Step # 2, the first surface state (which has a high polishing rate with respect to the convex portion 4 as in the CMP method using a polishing material generally containing cerium oxide as abrasive grains, is performed. In the state shown in FIG. 1 (c), the polishing process is performed under conditions such that the polishing rate automatically decreases and auto-stop occurs.

本ステップ＃１における、より具体的な研磨条件としては、例えば、旭硝子株式会社製の酸化セリウム砥粒を含む研磨材ＣＥＳ−３３３−２．０を毎分約２００ｍｌ滴下し、研磨時の押し付け圧力（以下、単に「研磨圧力」と称する）を約３ｐｓｉ（重量ポンド毎平方インチ、およそ２１ｋＰａ）程度、基板（ヘッド）の回転速度を約１２０ｒｐｍ、研磨布（プラテン）の回転速度を約１３０ｒｐｍとして研磨処理を行う。図３は、半導体素子２の厚みを約１８０ｎｍとし、層間絶縁膜３としてＰ−ＳｉＯ膜をＨＤＰ法で膜厚約１０００ｎｍ程度成膜したサンプルに対し、前記の研磨条件の下で第１研磨処理を実行した場合の、凸部４及び非凸部５の半導体基板１の上面からの高さ位置の変化を示したものである。高さ位置の測定は、分光エリプソメトリ法もしくは分光干渉反射率法による層間絶縁膜３の光学的膜厚測定法と、原子間力顕微鏡法による層間絶縁膜３表面の段差測定法により算出したものであり、直径約２００ｍｍの半導体基板（ウェハ）上の面内における異なる９点の測定値の平均を示している。なお、各点の誤差棒は、上記面内９点の測定値の上限から下限に至るバラツキを示すものである。   As more specific polishing conditions in Step # 1, for example, approximately 200 ml of abrasive CES-333-2.0 containing cerium oxide abrasive grains manufactured by Asahi Glass Co., Ltd. is dropped every minute, and the pressing pressure during polishing (Hereinafter simply referred to as “polishing pressure”) is about 3 psi (weight pound per square inch, about 21 kPa), substrate (head) rotation speed is about 120 rpm, and polishing cloth (platen) rotation speed is about 130 rpm. Process. FIG. 3 shows a first polishing process under the above-described polishing conditions for a sample in which the thickness of the semiconductor element 2 is about 180 nm and a P-SiO film is formed as the interlayer insulating film 3 by the HDP method to a thickness of about 1000 nm. 7 shows changes in the height position of the convex portion 4 and the non-convex portion 5 from the upper surface of the semiconductor substrate 1 when the above is executed. The height position was measured by an optical film thickness measurement method of the interlayer insulating film 3 by a spectroscopic ellipsometry method or a spectral interference reflectance method, and a step measurement method of the surface of the interlayer insulating film 3 by an atomic force microscope method. It shows the average of the measured values at nine different points in the plane on the semiconductor substrate (wafer) having a diameter of about 200 mm. Note that the error bars at each point indicate variations from the upper limit to the lower limit of the measured values at the nine points in the plane.

ここで、実際には、１０秒以上の第１研磨処理を施した段階で、層間絶縁膜３の表面状態は前記第１表面状態となっており、すでに凸部４は存在しない状態であるが、以下の説明では、第１研磨処理開始前に存在していた凸部４と非凸部５の高さ位置が、第１研磨処理の実行によってどのように変化していくかについての説明を行う都合上、第１研磨処理の開始前に凸部４が形成されていた領域を「凸部４」と記載し、第１研磨処理の開始前に非凸部５が形成されていた領域を「非凸部５」と記載している。   Here, in practice, the surface state of the interlayer insulating film 3 is the first surface state when the first polishing process is performed for 10 seconds or more, and the convex portion 4 is not already present. In the following description, it will be described how the height positions of the convex portions 4 and the non-convex portions 5 that existed before the start of the first polishing process are changed by the execution of the first polishing process. For convenience, the region where the convex portion 4 was formed before the start of the first polishing process is referred to as “convex portion 4”, and the region where the non-convex portion 5 was formed before the start of the first polishing process is described. "Non-convex part 5" is described.

図３において、黒塗りの四角でプロットされた点は、凸部４の高さ位置を示しており、変化の状態を実線１１で示している。一方、白抜きの丸でプロットされた点は、非凸部５の高さ位置を示しており、変化の状態を破線１２で示している。また、各プロット位置において上下方向に示されている矢印は、複数のサンプルに対して同一の条件下で第１研磨処理を実行した際のサンプル間の高さ位置のバラツキを示しており、実線の矢印が凸部４の高さ位置のバラツキを、破線の矢印が非凸部５の高さ位置のバラツキをそれぞれ示している。   In FIG. 3, the points plotted with black squares indicate the height positions of the convex portions 4, and the state of change is indicated by the solid line 11. On the other hand, the points plotted with white circles indicate the height positions of the non-convex portions 5, and the state of change is indicated by a broken line 12. In addition, the arrows shown in the vertical direction at each plot position indicate variations in the height position between samples when the first polishing process is performed on a plurality of samples under the same conditions. The arrows indicate the variations in the height position of the convex portion 4, and the broken arrows indicate the variations in the height position of the non-convex portion 5.

まず、第１研磨処理開始時（研磨時間０秒）において、凸部４の高さ位置と非凸部５の高さ位置の差は、半導体素子２の厚みにほぼ等しく、図３のグラフでは約１８０ｎｍを示している。   First, at the start of the first polishing process (polishing time 0 second), the difference between the height position of the convex portion 4 and the height position of the non-convex portion 5 is substantially equal to the thickness of the semiconductor element 2, and in the graph of FIG. About 180 nm is shown.

次に、約１０秒間第１研磨処理を実行することで、非凸部５に比べて凸部４に対して多くの研磨処理が施され、これによって凸部４の上面位置が徐々に非凸部５の上面位置に近付いている。そして、凸部４と非凸部５の上面位置がほぼ等しくなって以後、第１研磨処理を行っても両領域の上面位置はほとんど変化をしておらず、このことは、研磨が進行していないことを示唆している。すなわち、前記のオートストップが発生していると考えられ、凸部４に対する平坦化が完了（すなわち図１（ｃ）の状態）し、層間絶縁膜４の表面が前記第１表面状態となったことを示唆していると言える。   Next, by executing the first polishing process for about 10 seconds, a larger amount of polishing processing is performed on the convex portion 4 than on the non-convex portion 5, whereby the upper surface position of the convex portion 4 is gradually non-convex. It approaches the upper surface position of the part 5. After the top surface positions of the convex portions 4 and the non-convex portions 5 become substantially equal, even if the first polishing process is performed, the top surface positions of both regions hardly change, which means that the polishing progresses. Suggests not. That is, it is considered that the auto-stop has occurred, the flattening of the convex portion 4 is completed (that is, the state of FIG. 1C), and the surface of the interlayer insulating film 4 is in the first surface state. It can be said that it suggests.

なお、第１表面状態（研磨時間１０秒が経過した後）での層間絶縁膜３の表面における研磨速度はおよそ毎分２３ｎｍであり、第１研磨処理を開始してからの約１０秒間に凸部４が約１８０ｎｍ研磨されているのに比して、十分遅い研磨速度であると言うことができる。   Note that the polishing rate on the surface of the interlayer insulating film 3 in the first surface state (after the polishing time of 10 seconds elapses) is approximately 23 nm per minute, and protrudes about 10 seconds after the first polishing process is started. It can be said that the polishing rate is sufficiently slow as compared with the portion 4 being polished by about 180 nm.

上述したように、この第１研磨処理は、研磨材として酸化セリウム砥粒を利用しており、研磨圧力が一定値より低い場合には研磨速度が遅くなる、いわゆる非プレストニアン特性を有している。そして、このような性質を利用することで、平坦化が完了した後においても、過剰に研磨されることがないという特徴を有する。従って、かかる特徴を利用するためには、凸部４が存在している状況下における研磨速度を、凸部４に対する平坦化が完了した後の研磨速度と比較して十分大きくすることが好ましく、このような条件下で第１研磨処理を行うことで、層間絶縁膜３を過剰に研磨することなく表面の平坦化を行うことができる。   As described above, this first polishing process uses cerium oxide abrasive grains as an abrasive, and has a so-called non-Prestonian characteristic in which the polishing rate becomes slow when the polishing pressure is lower than a certain value. Yes. And by utilizing such a property, even after the planarization is completed, there is a feature that excessive polishing is not performed. Therefore, in order to utilize such a feature, it is preferable that the polishing rate in the situation where the convex portion 4 exists is sufficiently larger than the polishing rate after the flattening of the convex portion 4 is completed, By performing the first polishing process under such conditions, the surface can be planarized without excessively polishing the interlayer insulating film 3.

すなわち、第１研磨処理が、所定の閾値を上回る研磨圧力の下では研磨速度が速く、当該閾値を下回る研磨圧力の下では研磨速度が十分遅くなるという特徴を有しているため、かかる特徴を十分に発揮させるためには、凸部４が存在している成膜表面に対しては研磨圧力が前記閾値を上回り、逆に、凸部４が存しなくなった第１表面状態の成膜表面に対しては研磨圧力が前記閾値を下回るように、研磨条件を調整することが必要である。具体的には、平坦化処理が完了した後の第１表面状態の層間絶縁膜３の表面に対する研磨速度は毎分５０ｎｍ以下であり、平坦化処理前の凸部４が存在する状況下ではその４倍以上の研磨速度で層間絶縁膜３の表面に対して研磨処理が行われることが好ましい。   That is, the first polishing process has a feature that the polishing rate is high under a polishing pressure exceeding a predetermined threshold, and the polishing rate is sufficiently low under a polishing pressure below the threshold. In order to fully exhibit, the film-forming surface in which the convex portion 4 is present has a polishing pressure higher than the threshold value, and conversely, the film-forming surface in the first surface state in which the convex portion 4 no longer exists. In contrast, it is necessary to adjust the polishing conditions so that the polishing pressure falls below the threshold value. Specifically, the polishing rate for the surface of the interlayer insulating film 3 in the first surface state after the planarization process is completed is 50 nm or less per minute, and in the situation where the convex part 4 before the planarization process exists, It is preferable that the polishing process is performed on the surface of the interlayer insulating film 3 at a polishing rate of 4 times or more.

ところで、凸部４に対する平坦化処理が完了した後の層間絶縁膜３に対する研磨速度は、砥粒として利用される材料の他、被研磨対象となる層間絶縁膜３の膜種によっても変化する。例えば、ＰＥ−ＣＶＤ（プラズマＣＶＤ）法によって形成したＰ−ＴＥＯＳ膜である場合、平坦化処理後の研磨速度は毎分３１ｎｍ程度であり、上述したＨＤＰ法で成膜したＰ−ＳｉＯ膜が示す毎分２３ｎｍの研磨速度よりは高速であるものの、毎分５０ｎｍ以下の十分遅い研磨速度であるため、かかる材料を層間絶縁膜３として利用することで、過剰に研磨されることなく凸部４に対する平坦化が可能であると言える。一方、熱ＣＶＤ法によって成膜したＢ及びＰをドープしたＢＰＳＧ膜においては、平坦化処理後の研磨速度が毎分４５０ｎｍ以上となるため、第１研磨処理の被研磨対象としては適さないと言える。   By the way, the polishing rate for the interlayer insulating film 3 after the flattening process for the convex part 4 is completed varies depending on the film type of the interlayer insulating film 3 to be polished as well as the material used as the abrasive grains. For example, in the case of a P-TEOS film formed by the PE-CVD (plasma CVD) method, the polishing rate after the planarization process is about 31 nm per minute, and the P-SiO film formed by the HDP method described above shows Although the polishing rate is higher than the polishing rate of 23 nm per minute, it is a sufficiently slow polishing rate of 50 nm or less per minute. Therefore, by using such a material as the interlayer insulating film 3, the protrusion 4 is not polished excessively. It can be said that flattening is possible. On the other hand, in the BPSG film doped with B and P formed by the thermal CVD method, the polishing rate after the flattening process is 450 nm or more per minute, so it can be said that it is not suitable as the object to be polished in the first polishing process. .

このように、第１研磨処理において、凸部４が存在する状況下での研磨速度に対して、凸部４に対する平坦化が完了した後の研磨速度が十分遅い場合には、例えば、一般的に用いられるように、基板（ヘッド）回転トルクまたは研磨布（プラテン）回転トルクの経時変化を連続的に監視することにより、平坦化が完了したことを知ることができる。このようにして平坦化の完了を確認した時点で、第１研磨処理を終了することにより、過剰な研磨をすることなく凸部４に対する平坦化を実行することができる。   As described above, in the first polishing process, when the polishing rate after the flattening of the convex portion 4 is sufficiently slow with respect to the polishing rate in the situation where the convex portion 4 exists, for example, As described above, it is possible to know that the planarization has been completed by continuously monitoring the change with time of the substrate (head) rotation torque or the polishing cloth (platen) rotation torque. When the completion of the planarization is confirmed in this way, the first polishing process is terminated, whereby the planarization of the convex portion 4 can be performed without excessive polishing.

しかしながら、平坦化が完了した後の第１研磨処理の研磨速度は十分遅いため、図１（ｃ）に示されるように、当該第１研磨処理完了後の層間絶縁膜３の上面には研磨時に生じたスクラッチ等の欠陥６が残存した状態である。   However, since the polishing rate of the first polishing process after the planarization is completed is sufficiently slow, as shown in FIG. 1C, the upper surface of the interlayer insulating film 3 after the completion of the first polishing process is not polished. The defect 6 such as a generated scratch remains.

ここで、ステップ＃２に係る第１研磨処理と比べて、研磨圧力を１．５倍以上として層間絶縁膜３に対して改めて研磨処理を行う（以下、「第２研磨処理」と称する。ステップ＃３）。かかる第２研磨処理によって、層間絶縁膜３の上面を研磨し、上面に残存する欠陥６を取り除く。この第２研磨処理においては、第１研磨処理から研磨材及び研磨布（プラテン）を変える必要は無く、第１研磨処理に引き続き連続的に行うことも可能である。例えば、約６ｐｓｉ（およそ４１ｋＰａ）の研磨圧力にて約４０秒間研磨を行うことで、約１００ｎｍ程度の膜厚の層間絶縁膜３を除去する。下記表１は、第２研磨処理における層間絶縁膜３の研磨除去量に対する研磨後の層間絶縁膜３の表面に存在する欠陥数を示す表である。   Here, as compared with the first polishing process according to Step # 2, the polishing process is performed again on the interlayer insulating film 3 at a polishing pressure of 1.5 times or more (hereinafter referred to as “second polishing process”). # 3). By the second polishing process, the upper surface of the interlayer insulating film 3 is polished, and the defects 6 remaining on the upper surface are removed. In the second polishing process, it is not necessary to change the abrasive and the polishing cloth (platen) from the first polishing process, and it is possible to perform the second polishing process continuously following the first polishing process. For example, by polishing for about 40 seconds at a polishing pressure of about 6 psi (about 41 kPa), the interlayer insulating film 3 having a thickness of about 100 nm is removed. Table 1 below shows the number of defects present on the surface of the interlayer insulating film 3 after polishing with respect to the polishing removal amount of the interlayer insulating film 3 in the second polishing process.

Figure 2008277495
Figure 2008277495

なお、上記表１に示される欠陥数とは、適切な洗浄を施した後に、欠陥の大きさ（欠陥領域を上面から見たときの平面形状の外接長方体の長辺と短辺の平均値）が約１００ｎｍ以上を示す欠陥の、直径約２００ｍｍの半導体基板（ウェハ）１枚当たりの数によって表している。以下では、欠陥数としてカウントされる範囲内の欠陥を「欠陥６」と記載する。   It should be noted that the number of defects shown in Table 1 above is the size of the defect (the average of the long side and the short side of the circumscribed cuboid in a planar shape when the defect region is viewed from above) after appropriate cleaning. Value) is represented by the number of defects having a value of about 100 nm or more per semiconductor substrate (wafer) having a diameter of about 200 mm. Hereinafter, the defect within the range counted as the number of defects is referred to as “defect 6”.

サンプルＳ１は、第１研磨処理のみを実行し、第２研磨処理を実行しない場合の欠陥数を測定したものである。また、サンプルＳ２〜Ｓ４は、同一の条件下で第１研磨処理を実行後、それぞれ第２研磨処理の研磨量を変化させたときの欠陥数を測定したものである。また、サンプルＳ５は、第１研磨処理を行わず、研磨圧力を大きくした第２研磨処理のみを行って凸部４の平坦化処理を行ったときの欠陥数を測定したものである。なお、各サンプルＳ２〜Ｓ５の第２研磨処理の研磨量は、それぞれサンプルＳ２が２８ｎｍ、サンプルＳ３が５７ｎｍ、サンプルＳ４が８５ｎｍ、サンプルＳ５が１１３ｎｍである。   Sample S1 is obtained by measuring the number of defects when only the first polishing process is performed and the second polishing process is not performed. Samples S2 to S4 are obtained by measuring the number of defects when the polishing amount of the second polishing process is changed after the first polishing process is performed under the same conditions. Sample S5 is obtained by measuring the number of defects when the flattening process of the convex portion 4 is performed by performing only the second polishing process with an increased polishing pressure without performing the first polishing process. The polishing amount of the second polishing process for each of the samples S2 to S5 is 28 nm for the sample S, 57 nm for the sample S3, 85 nm for the sample S4, and 113 nm for the sample S5.

サンプルＳ１の場合、第１研磨処理を実行した直後の層間絶縁膜３の表面には３００００個を超える非常に多くの欠陥６が存在していることが分かる。従って、第１研磨処理のみを実行することによってＣＭＰ工程を完了させ、その後の工程を行った場合、層間絶縁膜３の上面に残存する多くの欠陥６によって、例えば、配線用金属膜堆積時に欠陥６に入り込んだ金属材料が、配線パターン形成のためのエッチング工程において正常にエッチングされない不良が生じたり、あるいは、フォトリソグラフィ工程において欠陥６上部の領域のパターン消失や不要パターンの残存などの不良が生じたりし、配線やヴィアホールが所望の形状とならない等の種々の支障を生じさせることが懸念される。   In the case of the sample S1, it can be seen that a very large number of defects 6 exceeding 30000 exist on the surface of the interlayer insulating film 3 immediately after the first polishing process. Therefore, when the CMP process is completed by performing only the first polishing process and the subsequent processes are performed, many defects 6 remaining on the upper surface of the interlayer insulating film 3 may cause defects during the deposition of the wiring metal film, for example. The metal material that has entered 6 has a defect that is not normally etched in the etching process for forming the wiring pattern, or a defect such as the disappearance of the pattern in the region above the defect 6 or the remaining unnecessary pattern occurs in the photolithography process. However, there is a concern that various troubles such as a wiring or a via hole not having a desired shape may be caused.

一方、サンプルＳ２の結果によれば、第１研磨処理を実行後、第２研磨処理によって層間絶縁膜３を膜厚２８ｎｍ除去することにより、欠陥数はウェハ１枚あたりおよそ３００個にまで減少する。このことから、第１研磨処理で生じた欠陥数は非常に多いものの、第１研磨処理終了後の層間絶縁膜３の上面位置から深さ３０ｎｍ以下の位置に存在するものが大半であり、第２研磨処理によって３０ｎｍ程度の層間絶縁膜３を除去することで、効率的に欠陥６が除去されていると考えられる。また、このことより、第１研磨処理によって生じる欠陥６は、研磨装置の状態により変動するのはもちろんであるものの、一般的な研磨砥粒の大きさに比して小さな欠陥であり、通常の装置管理方法のみで欠陥自体を抑制することは困難であることを示唆するものであると言うことができる。   On the other hand, according to the result of the sample S2, the number of defects is reduced to about 300 per wafer by removing the interlayer insulating film 3 with a film thickness of 28 nm by the second polishing process after the first polishing process. . For this reason, although the number of defects generated in the first polishing process is very large, most of the defects are present at a depth of 30 nm or less from the upper surface position of the interlayer insulating film 3 after the completion of the first polishing process. 2 It is considered that the defect 6 is efficiently removed by removing the interlayer insulating film 3 of about 30 nm by the polishing process. In addition, from this, the defect 6 caused by the first polishing treatment is a defect that is small compared to the size of a general polishing abrasive grain, although it naturally varies depending on the state of the polishing apparatus. It can be said that it is difficult to suppress the defect itself only by the device management method.

また、サンプルＳ４の結果によれば、第２研磨処理によって層間絶縁膜３の除去量を８５ｎｍ程度にまで増加させれば、欠陥数はウェハ１枚あたりおよそ１００個以下にまで減少させることができ、サンプルＳ５のように、第２研磨処理のみでＣＭＰ工程を行う場合とほとんど同程度の欠陥数に抑制することができる。   Further, according to the result of the sample S4, if the removal amount of the interlayer insulating film 3 is increased to about 85 nm by the second polishing process, the number of defects can be decreased to about 100 or less per wafer. As in sample S5, the number of defects can be suppressed to almost the same as when the CMP process is performed only by the second polishing process.

なお、サンプルＳ５のように第２研磨処理のみを実行した場合、上記表１に示すように欠陥数を最も減少させることはできるものの、第１研磨処理と比較して研磨圧力が大きいために凸部４が存在しなくなった第１表面状態になった後も、大きく研磨処理が実行される結果、過剰に研磨処理を実行してしまう懸念がある。すなわち、本発明方法のように、第１研磨処理によって平坦化処理を行うことで、研磨膜厚を最小限に抑えながら成膜表面を第１表面状態にした後、欠陥数を減少させるために必要な最小限の研磨処理を第２研磨処理によって実行することで、研磨処理後に残存する欠陥数の減少と研磨される膜厚の抑制とを両立することが可能となる。   When only the second polishing process is performed as in the sample S5, the number of defects can be reduced most as shown in Table 1 above, but the convexity is higher because the polishing pressure is larger than the first polishing process. Even after the first surface state in which the portion 4 no longer exists, there is a concern that the polishing process is excessively performed as a result of the large polishing process being performed. That is, in order to reduce the number of defects after making the film formation surface into the first surface state while minimizing the polishing film thickness by performing the planarization process by the first polishing process as in the method of the present invention. By executing the necessary minimum polishing process by the second polishing process, it is possible to achieve both reduction in the number of defects remaining after the polishing process and suppression of the film thickness to be polished.

ここで、上記表１の結果によれば、第２研磨処理によって層間絶縁膜３を研磨する研磨量は３０ｎｍ程度以上であることが望ましく、また８０ｎｍ以上であればより望ましいことが分かる。   Here, according to the results in Table 1, it is found that the polishing amount for polishing the interlayer insulating film 3 by the second polishing process is preferably about 30 nm or more, and more preferably 80 nm or more.

また、第２研磨処理は、第１研磨処理よりも研磨圧力が大きいため、第１表面状態を有する層間絶縁膜３に対して行われる第１研磨処理と比較して研磨速度が速い。従って、第２研磨処理を、層間絶縁膜３の膜厚を一般的な光学的手法等で監視しながら行うことで、残存させたい層間絶縁膜３の膜厚を容易に制御することができ、これにより、層間絶縁膜３を所望の膜厚だけ残存させてＣＭＰ工程を完了することができる。従って、層間絶縁膜３の形成工程のバラツキや、ＣＭＰ装置の研磨速度のバラツキを抑制することが可能となる。   Further, since the second polishing process has a higher polishing pressure than the first polishing process, the polishing rate is higher than that of the first polishing process performed on the interlayer insulating film 3 having the first surface state. Therefore, by performing the second polishing process while monitoring the film thickness of the interlayer insulating film 3 by a general optical method or the like, it is possible to easily control the film thickness of the interlayer insulating film 3 desired to remain, Thereby, the CMP process can be completed while leaving the interlayer insulating film 3 to a desired thickness. Accordingly, it is possible to suppress variations in the formation process of the interlayer insulating film 3 and variations in the polishing rate of the CMP apparatus.

ステップ＃３に係る第２研磨処理を終了後は、配線工程、層間絶縁膜堆積工程等の所定の工程を行う。これにより、層間絶縁膜の表面に存する欠陥数を減少させるとともに、残存させたい層間絶縁膜３の膜厚を容易に制御することができる。   After the second polishing process in step # 3 is completed, predetermined processes such as a wiring process and an interlayer insulating film deposition process are performed. Thereby, the number of defects existing on the surface of the interlayer insulating film can be reduced, and the film thickness of the interlayer insulating film 3 desired to remain can be easily controlled.

以上、本発明方法によれば、被研磨膜表面に存する凸部を平坦化するために行う第１研磨処理と、表面に損する欠陥数を減少させるために行う第２研磨処理とを、それぞれ研磨条件を異ならせて実行することにより、成膜された被研磨膜を過剰に研磨することなく、当該被研磨膜表面に対する平坦化処理が行えるとともに、研磨後の表面に存する欠陥量を従来よりも大きく減少することができる。さらに、後で行われる第２研磨処理は、第１研磨処理と比較して研磨圧力が大きいため、第１表面状態の被研磨膜表面に対しても監視可能な速度で研磨を行うことができる。これにより、あらかじめ定められた膜厚だけ研磨した時点で第２研磨処理を終了させる制御が可能となり、残存させたい被研磨膜の膜厚の調整を容易に行うことができる。   As described above, according to the method of the present invention, the first polishing process performed for flattening the convex portion existing on the surface of the film to be polished and the second polishing process performed for reducing the number of defects damaged on the surface are each polished. By performing the process under different conditions, the surface of the film to be polished can be planarized without excessively polishing the film to be polished, and the amount of defects existing on the surface after polishing can be reduced as compared with the prior art. It can be greatly reduced. Furthermore, since the second polishing process to be performed later has a higher polishing pressure than the first polishing process, the surface of the film to be polished in the first surface state can be polished at a monitorable speed. . This makes it possible to control the second polishing process to end when the predetermined film thickness is polished, and to easily adjust the film thickness of the film to be polished.

なお、上述した実施形態では、層間絶縁膜に対する平坦化処理を行う場合を例に挙げて説明を行ったが、研磨対象となる被研磨膜は絶縁膜に限らず、導電膜であっても構わない。また、図１において「凸部」「非凸部」という表現を行ったが、これは成膜表面に形成された凹凸領域の呼称する上での一態様であって、高さ位置が高い領域を基準とすれば「凹部」「非凹部」と記載することも可能である。すなわち、凸部４が存在しない平面状態として定義した前記「第１表面状態」とは、むろん凹部が存在しない平面状態でもあり、これらを総称すれば、成膜表面において半導体基板１の基板面に対して高さ位置または深さ位置が垂直な方向に１００ｎｍ以上変化する領域を有しない表面状態を指すものである。   In the embodiment described above, the case where the planarization process is performed on the interlayer insulating film has been described as an example. However, the film to be polished is not limited to the insulating film but may be a conductive film. Absent. In addition, the expressions “convex portion” and “non-convex portion” are used in FIG. 1, but this is an aspect for naming the uneven region formed on the film formation surface, and is a region having a high height position. Can be described as “concave portion” and “non-concave portion”. That is, the “first surface state” defined as a planar state in which the convex portion 4 does not exist is, of course, a planar state in which no concave portion exists, and these are collectively referred to as the substrate surface of the semiconductor substrate 1 on the film formation surface. On the other hand, it refers to a surface state having no region in which the height position or depth position changes by 100 nm or more in the vertical direction.

本発明に係る半導体装置の製造方法の各工程における概略断面構造図Schematic cross-sectional structure diagram in each step of the semiconductor device manufacturing method according to the present invention 本発明に係る半導体装置の製造方法の工程手順を示すフローチャート6 is a flowchart showing a process procedure of a semiconductor device manufacturing method according to the present invention. 第１研磨処理の研磨時間特性を示すグラフGraph showing the polishing time characteristics of the first polishing process

符号の説明Explanation of symbols

１： 半導体基板
２： 半導体素子
３： 層間絶縁膜
４： 凸部
５： 非凸部 1: Semiconductor substrate 2: Semiconductor element 3: Interlayer insulating film 4: Convex part 5: Non-convex part

Claims (6)

半導体基板上に絶縁膜または導電膜で構成される被研磨膜を成膜する成膜工程と、
前記成膜工程終了後、前記被研磨膜の成膜表面を平坦化する平坦化工程と、を有する半導体装置の製造方法であって、
前記平坦化工程が、
非プレストニアン特性を有する砥粒を用いて前記被研磨膜の表面に対して研磨処理を行う第１研磨処理と、
前記第１研磨処理を終了後、前記第１研磨処理と比較して１．５倍以上の研磨圧力の下で前記被研磨膜の表面に対して研磨処理を行う第２研磨処理と、を有し、
前記第１研磨処理が、
前記被研磨膜の成膜表面を、少なくとも前記半導体基板面に垂直な方向の高さまたは深さが１００ｎｍ以上の凸部または凹部が存在しない第１表面状態に変化させた段階で終了することを特徴とする半導体装置の製造方法。 A film forming process for forming a film to be polished comprising an insulating film or a conductive film on a semiconductor substrate;
A flattening step of flattening a film-forming surface of the film to be polished after the film-forming step,
The planarization step comprises:
A first polishing process for performing a polishing process on the surface of the film to be polished using abrasive grains having non-Prestonian characteristics;
A second polishing process for performing a polishing process on the surface of the film to be polished under a polishing pressure of 1.5 times or more compared with the first polishing process after the first polishing process is completed. And
The first polishing process includes
Finishing at the stage where the film forming surface of the film to be polished is changed to a first surface state in which at least a height or depth in a direction perpendicular to the surface of the semiconductor substrate is not more than 100 nm. A method of manufacturing a semiconductor device. 前記第１研磨処理において、
前記第１表面状態を示す成膜表面に対する研磨速度が、開始直後の研磨速度の１／４以下であることを特徴とする請求項１に記載の半導体装置の製造方法。 In the first polishing process,
2. The method of manufacturing a semiconductor device according to claim 1, wherein a polishing rate for the film-forming surface showing the first surface state is ¼ or less of a polishing rate immediately after the start. 前記第２研磨処理が、前記第１表面状態を示す成膜表面に対して毎分２００ｎｍ以上の研磨が可能な研磨条件で行われることを特徴とする請求項１または請求項２に記載の半導体装置の製造方法。   3. The semiconductor according to claim 1, wherein the second polishing treatment is performed under a polishing condition that enables polishing of 200 nm or more per minute on the film-forming surface showing the first surface state. Device manufacturing method. 前記第１研磨処理が、前記第１表面状態を示す成膜表面に対して毎分５０ｎｍ以下の研磨が可能な研磨条件で行われることを特徴とする請求項１〜請求項３のいずれか１項に記載の半導体装置の製造方法。   The said 1st grinding | polishing process is performed on the grinding | polishing conditions which can grind | polish 50 nm or less per minute with respect to the film-forming surface which shows the said 1st surface state. A method for manufacturing the semiconductor device according to the item. 前記第２研磨処理が、前記被研磨膜に対して膜厚３０ｎｍ以上研磨を施して終了することを特徴とする請求項１〜請求項４のいずれか１項に記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein the second polishing process is finished by polishing the film to be polished by a film thickness of 30 nm or more. 6. 前記被研磨膜が、ＨＤＰ法により成膜されたシリコン酸化膜であることを特徴とする請求項１〜請求項５のいずれか１項に記載の半導体装置の製造方法。
6. The method of manufacturing a semiconductor device according to claim 1, wherein the film to be polished is a silicon oxide film formed by an HDP method.
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TWI820399B (en) * 2021-02-26 2023-11-01 國立臺灣科技大學 Wafer processing method and wafer processing system

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JP2002359216A (en) * 2001-05-30 2002-12-13 Mitsubishi Electric Corp Polishing method using ceria slurry, and method of manufacturing semiconductor device
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JP2006032846A (en) * 2004-07-21 2006-02-02 Sharp Corp Method for manufacturing semiconductor device using cmp

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* Cited by examiner, † Cited by third party
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JP2013031909A (en) * 2011-08-03 2013-02-14 Seiko Instruments Inc Method for polishing glass substrate, method for manufacturing package, piezoelectric vibrator, oscillator, electronic apparatus and radio-controlled timepiece

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